PHP69NLT ETC

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Technical content

Philips Semiconductors Product specification TrenchMOS  transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA

  • ’Trench’ technology VDSS = 25 V
  • Very low on-state resistance
  • Fast switching ID = 69 A
  • Stable off-state characteristics
  • High thermal cycling performance R DS(ON) ≤ 14 mΩ (VGS = 5 V)
  • Low thermal resistance R DS(ON) ≤ 12 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The combination of very low on-state resistance and low switching losses make this device the optimum choice in high The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB69N03LT is supplied in the SOT404 surface mounting package. The PHD69N03LT is supplied in the SOT428 surface mounting package. PINNING SOT78 (TO220AB) SOT404 SOT428 PIN DESCRIPTION 1 gate 2 drain 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 175˚C - 25 V VDGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -2 5 V VGS Gate-source voltage - ± 15 V VGSM Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V ID Continuous drain current Tmb = 25 ˚C; VGS = 5 V - 69 A Tmb = 100 ˚C; VGS = 5 V - 48 A IDM Pulsed drain current T mb = 25 ˚C - 240 A PD Total power dissipation T mb = 25 ˚C - 125 W Tj, Tstg Operating junction and - 55 175 ˚C storage temperature d g s tab tab 12 3 tab 1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages. June 1998 1 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 1.2 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT404 and SOT428 packages, pcb - 50 - K/W mounted, minimum footprint

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 25 - - V voltage T j = -55˚C 22 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 175˚C 0.5 - - V R DS(ON) Drain-source on-state V GS = 10 V; ID = 25 A - 8.5 12 m Ω resistance V GS = 5 V; ID = 25 A - 11 14 m Ω VGS = 5 V; ID = 25 A; Tj = 175˚C - - 26 m Ω gfs Forward transconductance VDS = 25 V; ID = 25 A 12 25 - S IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA IDSS Zero gate voltage drain V DS = 25 V; VGS = 0 V; - 0.05 10 µA current T j = 175˚C - - 500 µA Q g(tot) Total gate charge I D = 20 A; VDD = 24 V; VGS = 10 V - 70 - nC Q gs Gate-source charge - 9 - nC Q gd Gate-drain (Miller) charge - 20 - nC td on Turn-on delay time V DD = 15 V; ID = 25 A; - 10 20 ns tr Turn-on rise time V GS = 10 V; RG = 5 Ω -5 0 7 5 n s td off Turn-off delay time Resistive load - 80 120 ns tf Turn-off fall time - 50 75 ns Ld Internal drain inductance Measured tab to centre of die - 3.5 - nH Ld Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) Ls Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 1700 - pF C oss Output capacitance - 480 - pF C rss Feedback capacitance - 250 - pF June 1998 2 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IS Continuous source current - - 69 A (body diode) ISM Pulsed source current (body - - 240 A diode) VSD Diode forward voltage I F = 25 A; VGS = 0 V - 0.95 1.2 V IF = 69 A; VGS = 0 V - 1.0 - trr Reverse recovery time I F = 69 A; -dIF/dt = 100 A/µs; - 65 - ns Q rr Reverse recovery charge V GS = -10 V; VR = 25 V - 0.1 - µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT W DSS Drain-source non-repetitive ID = 25 A; VDD ≤ 15 V; - 60 mJ unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω ; Tmb = 25 ˚C energy Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Tmb ) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Tmb ); conditions: VGS ≥ 5 V 0 20 40 60 80 100 120 140 160 180 Tmb / C PD% Normalised Power Derating120 110 100 0 20 40 60 80 100 120 140 160 180 Tmb / C ID% Normalised Current Derating 120 110 100 June 1998 3 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET Fig.3. Safe operating area ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS Fig.7. Typical transfer characteristics. ID = f(VGS ) ; conditions: VDS = 25 V; parameter Tj Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ) 1 10 1001 100 1000 7514-30 tp = 10 us 100 us 1 ms 10 msDC RDS(ON) = VDS / ID Tmb = 25 C VDS, Drain-source voltage (Volts) ID, Drain current (Amps) 100 ms 0 1 02 03 04 05 0 0.01 0.02 0.03 0.04 0.05 0.06 PHP69N03LTID, Drain current (Amps) RDS(on), Drain-Source on resistance (Ohms) VGS = 15 V 10 V 5 V 3.2 V3 V2.8 V2.6 V Tj = 25 C 1E-07 1E-05 1E-03 1E-01 1E+01 t / s Zth j-mb / (K/W)10 0.1 0.01 0.001 0.5 0.2 0.1 0.05 0.02 BUKx55-lv D = D = tp tp T TP t D 012345

50 PHP69N03LT

Gate-source voltage, VGS (V) Drain current, ID (A) Tj = 25 C 175 C VDS > RDS(ON) x ID 012345 PHP69N03LT VDS, Drain-Source voltage (Volts) ID, Drain current (Amps) VGS = 2.2 V 2.4 V 2.6 V 2.8 V 3 V

3.2 V5 V

15V 10 V Tj = 25 C 0 1 02 03 04 05 0 PHP69N03LT Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 175 C VDS > RDS(ON) x ID June 1998 4 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ); parameter VDS Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj -100 0 100 2000 0.5 1.5 2 30V TrenchMOS Tj / C a 15050-50 0.1 1 10 100100 1000 10000 9514-30 Drain-source volage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss BUK959-60 -100 -50 0 50 100 150 2000 0.5 1.5 2.5 Tj / C VGS(TO) / V max. typ. min. 0 1 02 03 04 05 06 07 08 0

15 PHP69N03LT

Qg, Gate charge (nC) VGS, Gate-Source voltage (Volts) VDD=24V ID=20A Tj = 25C 0 0.5 1 1.5 2 2.5 31E-05 1E-05 1E-04 1E-03 1E-02 1E-01 Sub-Threshold Conduction 2% typ 98% 0 0.5 1 1.5 20 100 9514-30 VSDS / V IF / A Tj / C = 175 25 June 1998 5 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET Fig.15. Normalised avalanche energy rating. W DSS % = f(Tmb ) Fig.16. Avalanche energy test circuit. 20 40 60 80 100 120 140 160 180 Tmb / C 120 110 100 WDSS% L T.U.T. VDD RGS R 01 VDS -ID/100 shunt VGS W DSS = 0.5⋅LID 2 ⋅BV DSS /(BV DSS − VDD ) June 1998 6 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". 10,3 max 3,7 2,8 3,03,0 max not tinned 1,3 max (2x) 123 2,4 0,6 4,5 max 5,9 min 15,8 max 1,3 2,54 2,54 0,9 max (3x) 13,5 min June 1998 7 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 June 1998 8 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET MECHANICAL DATA Dimensions in mm : Net Mass: 1.4 g Fig.20. SOT428 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm Fig.21. SOT428 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". 6.22 max 2.38 max 0.93 max 6.73 max 0.3 10.4 max 0.5 0.8 max (x2) 2.285 (x2) 0.5 seating plane 1.1 0.5 min 5.4 4 min 4.6 tab 7.0 7.0 2.15 2.5 4.57 1.5 June 1998 9 Rev 1.400

Philips Semiconductors Product specification TrenchMOS transistor PHP69N03LT, PHB69N03LT, PHD69N03LT Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1998 10 Rev 1.400