PHN1015

PHN1015 PHILIPS

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Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FEATURES SYMBOL QUICK REFERENCE DATA  ’Trench’ technology VDSS = 25 V  Low on-state resistance  Fast switching ID = 10 A  Low-profile surface mount package R DS(ON) ≤ 15 mΩ (VGS = 10 V)  Logic level compatible R DS(ON) ≤ 18 mΩ (VGS = 5 V) GENERAL DESCRIPTION PINNING SOT96-1 (SO8) N-channel enhancement mode PIN DESCRIPTION logic level field-effect power transistor in a surface mounting 1-3 source plastic package using ’trench’ technology. 4 gate Application:- 5-8 drain  High frequency computer motherboard d.c. to d.c. converters The PHN1015 is supplied in the SOT96-1 (SO8) surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS Drain-source voltage T j = 25 ˚C to 150˚C - 25 V VDGR Drain-gate voltage T j = 25 ˚C to 150˚C; - 25 V R GS = 20 kΩ VGS Gate-source voltage (DC) - - ± 15 V VGSM Gate-source voltage (pulse peak - ± 20 V value) ID Drain current (tp ≤ 10 s) T a = 25 ˚C - 10 A Ta = 70 ˚C - 8 A IDM Drain current (pulse peak value) Ta = 25 ˚C - 40 A Ptot Total power dissipation T a = 25 ˚C - 2.5 W Ta = 70 ˚C - 1.6 W Tj, Tstg Operating junction and storage - - 55 150 ˚C temperature THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-a Thermal resistance junction Surface mounted, FR4 board, t ≤ 10 sec - 50 K/W to ambient R th j-a Thermal resistance junction Surface mounted, FR4 board 150 - K/W to ambient d g s 12 34 5678 pin 1 index December 1999 1 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET

ELECTRICAL CHARACTERISTICS

Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 25 - - V voltage T j = -55˚C 22 - - V VGS(TO) Gate threshold voltage V DS = VGS ; ID = 1 mA 1 1.5 2 V Tj = 150˚C 0.6 - - V R DS(ON) Drain-source on-state V GS = 10 V; ID = 10 A - 11 15 m Ω resistance V GS = 5 V; ID = 10 A - 15 18 m Ω VGS = 5 V; ID = 10 A; Tj = 150˚C - - 31 m Ω gfs Forward transconductance VDS = 25 V; ID = 10 A 10 25 - S IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA IDSS Zero gate voltage drain V DS = 25 V; VGS = 0 V; - 0.05 10 µA current T j = 150˚C - - 500 µA Q g(tot) Total gate charge I D = 10 A; VDD = 15 V; VGS = 5 V - 20 - nC Q gs Gate-source charge - 4.5 - nC Q gd Gate-drain (Miller) charge - 6.5 - nC td on Turn-on delay time V DD = 15 V; ID = 25 A; - 7 15 ns tr Turn-on rise time V GS = 10 V; RG = 5 Ω -5 6 8 0 n s td off Turn-off delay time Resistive load - 57 80 ns tf Turn-off fall time - 38 50 ns Ld Internal drain inductance Drain leads to centre of die - 1 - nH Ls Internal source inductance Source leads to source bond pad - 3 - nH C iss Input capacitance V GS = 0 V; VDS = 20 V; f = 1 MHz - 1230 - pF C oss Output capacitance - 354 - pF C rss Feedback capacitance - 254 - pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IDR Continuous source current T a = 25 ˚C, tp ≤ 10 s - - 10 A (body diode) IDRM Pulsed source current (body - - 40 A diode) V SD Diode forward voltage I F = 10 A; VGS = 0 V - 0.8 1.2 V trr Reverse recovery time I F = 10 A; -dIF/dt = 100 A/µs; - 87 - ns Q rr Reverse recovery charge V GS = 0 V; VR = 25 V - 0.1 - µC December 1999 2 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET Fig.1. Normalised power dissipation. PD% = 100⋅PD /PD 25 ˚C = f(Ta) Fig.2. Normalised continuous drain current. ID% = 100⋅ID /ID 25 ˚C = f(Ta); conditions: VGS ≥ 5 V Fig.3. Safe operating area. Ta = 25 ˚C ID & IDM = f(VDS ); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS ); parameter VGS Fig.6. Typical on-state resistance, Tj = 25 ˚C. R DS(ON) = f(ID ); parameter VGS Normalised Power Derating, Ptot (%) 100 0 20 40 60 80 100 120 140 160 Ambient temperature, Ta (C) 0.01 0.1 100 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Transient thermal impedance, Zth j-mb (K/W) single pulse D = 0.5 0.2 0.1 0.05 0.02 tp D = tp/TDP T Normalised Current Derating, ID (%) 100 120 0 20 40 60 80 100 120 140 160 Ambient temperature, Ta (C) Drain-Source Voltage, VDS (V) Drain Current, ID (A) 2.2 V 2.4 V Tj = 25 CVGS = 10 V 2 V 2.6 V 4.5 V 2.8 V 3 V 5 V 0.01 0.1 100 0.1 1 10 100 Drain-Source Voltage, VDS (V) Peak Pulsed Drain Current, IDM (A) D.C. 100 ms 10 ms RDS(on) = VDS/ ID 1 ms tp = 10 us 100 us 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 5 10 15 20 25 30 35 40 45 50 Drain Current, ID (A) Drain-Source On Resistance, RDS(on) (Ohms) VGS =4.5 V 10V Tj = 25 C2.8V 3 V 2.6 V2.2 V 2.4 V 5 V December 1999 3 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET Fig.7. Typical transfer characteristics. ID = f(VGS ) Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID ) Fig.9. Normalised drain-source on-state resistance. a = RDS(ON) /RDS(ON)25 ˚C = f(Tj) Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS ); conditions: VGS = 0 V; f = 1 MHz Gate-source voltage, VGS (V) Drain current, ID (A) VDS > ID X RDS(ON) Tj = 25 C 150 C Threshold Voltage, VGS(TO) (V) 0.25 0.5 0.75 1.25 1.5 1.75 2.25 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) typical maximum minimum 0 5 10 15 20 25 30 35 40 Drain current, ID (A) Transconductance, gfs (S) Tj = 25 C 150 C VDS > ID X RDS(ON) Drain current, ID (A) 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 0 0.5 1 1.5 2 2.5 3 Gate-source voltage, VGS (V) minimum typical maximum VDS = 5 V Normalised On-state Resistance 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 100 1000 10000 0.1 1 10 100 Drain-Source Voltage, VDS (V) Capacitances, Ciss, Coss, Crss (pF) Ciss Coss Crss December 1999 4 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG ) Fig.14. Typical reverse diode current. IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj 0 5 10 15 20 25 30 35 40 45 50 Gate charge, QG (nC) Gate-source voltage, VGS (V) ID = 10A Tj = 25 C VDD = 15 V Source-Drain Voltage, VSDS (V) Source-Drain Diode Current, IF (A) Tj = 25 C 150 C VGS = 0 V December 1999 5 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET MECHANICAL DATA Fig.15. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". UNIT A max. A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 o o 0.25 0.10.25 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 SOT96-1 X w M θ AA 1 A 2 bp D H E Lp Q detail X E Z e c L v M A (A )3 A pin 1 index y 076E03S MS-012AA 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.016 0 2.5 5 mm scale SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 95-02-04 97-05-22 December 1999 6 Rev 1.300

Philips Semiconductors Product specification N-channel TrenchMOS transistor PHN1015 Logic level FET DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1999 7 Rev 1.300