PFS7523-7529 POWERINT

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
  • PDF pages: 37

Technical content

www.power.com April 2025 PFC Controller with Integrated High-Voltage MOSFET and Qspeed Diode Optimized for High PF and Efficiency Across Load Range Key Benefits

  • High efficiency and power factor across load range
  • >95% efficiency from 10% load to full load
  • <60 mW no-load consumption at 230 VAC
  • PF >0.92 easily achievable at 20% load
  • EN61000-3-2 Class C and D compliant
  • Highly integrated for smallest boost PFC form factor
  • Integrated controller, MOSFET and ultra-low reverse recovery loss diode (Qspeed)
  • Packaging optimized for high volume production
  • Eliminates insulating pad/heat-spreader
  • Enhanced features
  • Programmable Power Good (PG) signal
  • User selectable power limit: Enables different HiperPFS-3 family members to be tested in the same design for optimum device selection
  • Integrated non-linear amplifier for fast output OV and UV protection and transient response
  • Digital line peak detection that provides robust performance even with distorted input voltage from UPS or generators
  • Digital power factor enhancer compensates for EMI filter and bridge distortion, providing high-line PF >0.92 @ 20% load
  • Frequency adjusted over line voltage and each line cycle
  • Spread-spectrum across >60 kHz window simplifies EMI filtering requirements
  • Lower boost inductance
  • Provides up to 450 W peak output power for universal applications, 1 kW for high-line only applications
  • Protection features include: UVLO, UV, OV, OTP, brown-in/out, cycle-by-cycle current limit and power limiting for overload protection
  • Halogen free and RoHS compliant

Applications

  • E-bike and EV 2-Wheeler • 80 Plus™ Platinum chargers designs
  • Power tool chargers • High-power adaptors
  • PC • High-power LED lighting
  • P r i n t e r • Industrial and appliance
  • LCD TV • Generic PFC converter
  • Video game consoles

Figure 1. Typical Application Schematic.

90 VAC (Full Power Mode)

180 VAC (Full Power Mode)

Table 1. Output Power Table (See Table 2 on page 11 for Maximum Continuous This Product is Covered by Patents and/or Pending Patent Applications. Figure 2. Package Options.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com

Description

The HiperPFS™-3 devices incorporate a continuous conduction mode (CCM) boost PFC controller, gate driver, ultra-low reverse recovery (Qspeed™) diode and high-voltage power MOSFET in a single, low-profile (GROUND pin connected) power package. HiperPFS-3 devices eliminate the PFC converter’s need for external current sense resistors and the associated power loss, and use an innovative control technique that adjusts the switching frequency over output load, input line voltage, and even input line cycle. This control technique maximizes efficiency over the entire load range of the converter, particularly at light loads. Additionally, it significant - ly minimizes the EMI filtering requirements due to its wide bandwidth spread spectrum effect. The HiperPFS-3 uses advanced digital techniques for line monitoring functions, line feed-forward scaling, and power factor enhancement, while using analog techniques for the core controller in order to maintain extremely low no-load power consumption. The HiperPFS-3 also features an integrated non-linear error amplifier for enhanced load transient response, a user program - mable Power Good (PG) signal as well as user selectable power limit functionality. HiperPFS-3 includes Power Integrations’ standard set of comprehensive protection features, such as integrated UV, OV, brown-in/out, and hysteretic thermal shutdown. HiperPFS-3 also provides cycle-by-cycle current limit and Safe Operating Area (SOA) protection of the power MOSFET, power limiting of the output for overload protection, and pin-to-pin short-circuit protection. HiperPFS-3’s innovative variable frequency continuous conduction mode operation (VF-CCM) minimizes switching losses by maintaining a low average switching frequency, while modulating the switching frequency in order to suppress EMI, the traditional challenge with continuous conduction mode solutions. Systems using HiperPFS-3 typically reduce the total X and Y capacitance requirements of the converter, the inductance of both the boost choke and EMI noise suppression chokes, thereby reducing overall system size and cost. Additionally, HiperPFS-3 devices dramatically reduce component count and board footprint while simplifying system design and enhancing reliability, when compared with designs that use discrete MOSFETs and controllers. The innovative variable frequency, continuous conduction mode controller enables the HiperPFS-3 to realize all of the benefits of continuous conduction mode operation while leverag - ing low-cost, small, simple EMI filters. Many regions mandate high power factor for many electronic products with high power requirements. These rules are combined with numerous application-specific standards that require high power supply efficiency across the entire load range, from full load to as low as 10% load. High efficiency at light load is a challenge for traditional PFC solutions in which fixed MOSFET switching frequencies cause fixed switching losses on each cycle, even at light loads. In addition to featuring relatively flat efficiency across the load range, HiperPFS-3 also enables high power factor of >0.92 at 20% load. HiperPFS-3 simplifies compliance with new and emerging energy-efficiency standards over a broad market space in applications such as PCs, LCD TVs, notebooks, appliances, pumps, motors, fans, printers and LED lighting. HiperPFS-3’s advanced power packaging technology and high efficien- cy simplify the complexity of mounting the IC and thermal manage - ment, while providing very high power capabilities in a single compact package; these devices are suitable for PFC applications from 75 W to 900 W. Product Highlights Protected Power Factor Correction Solution

  • Incorporates high-voltage power MOSFET, ultra-low reverse recovery loss Qspeed diode, controller and gate driver.
  • EN61000-3-2 Class C and Class D compliance.
  • Integrated protection features reduce external component count.
  • Accurate built-in brown-in/out protection.
  • Accurate built-in undervoltage (UV) protection.
  • Accurate built-in overvoltage (OV) protection.
  • Hysteretic thermal shutdown (OTP).
  • Internal power limiting function for overload protection.
  • Cycle-by-cycle power switch current limit.
  • Internal non-linear error amplifier for enhanced load transient response.
  • No external current sense resistor required.
  • Provides ‘lossless’ internal sensing via sense-FET.
  • Reduces component count and system losses.
  • Minimizes high current gate drive loop area.
  • Minimizes output overshoot and stresses during start-up
  • Integrated power limit.
  • Improved dynamic response.
  • Digitally controlled input line feed-forward gain adjustment for flattened loop gain across entire input voltage range.
  • Eliminates up to 40 discrete components for higher reliability and lower cost. Solution for High Efficiency, Low EMI and High PF
  • Continuous conduction mode PFC uses novel constant amp-second [on-time] volt-second [off-time] control engine.
  • High efficiency across load.
  • High power factor across load.
  • Low cost EMI filter.
  • Frequency sliding technique for light load efficiency improvements.
  • >95% efficiency from 10% load to full load achievable at nominal input voltages.
  • Variable switching frequency to simplify EMI filter design.
  • Varies over line input voltage to maximize efficiency and minimize EMI filter requirements.
  • Varies with input line cycle voltage by >60 kHz to maximize spread spectrum effect. Advanced Package for High Power Applications
  • Up to 450 W [universal], 1 kW [high-line only] peak output power capability in a highly compact package.
  • Simple adhesive or clip mounting to heat sink.
  • No insulation pad required and can be directly connected to heat sink.
  • Staggered pin arrangement for simple routing of board traces and high-voltage creepage requirements.
  • Single package solution for PFC converter reduces assembly costs and layout size.

not be tied directly to the SOURCE pin external to the IC. pull-down in the event of an open circuit condition. amplifier and the input to the on-time and off-time controllers. 80 µs time-constant with the bottom resistor, is required. POWER GOOD pin is asserted low. POWER GOOD pin is left unconnected. the negative bulk capacitor terminal connection. Figure 3. Pin Configuration.

Figure 4. Functional Block Diagram. This is the drain connection of the internal power switch. This is the cathode connection of the internal Qspeed Diode. The HiperPFS-3 is a variable switching frequency boost PFC solution. comply with regulatory harmonic current limits (high power factor). boost inductor and thus regulates the output voltage and power.

12 V GATE DRIVER

the fundamental requirement of power factor correction.

Figure 5. Idealized Converter Waveforms. network, thereby improving power factor. switch power limit over the input line range. characteristic as a function of load. the device is operated in the ‘Full’ power mode as shown in Figure 7. output voltage will drop out of regulation in accordance with Figure 6. brown-in, the engine enables switching. the maximum overshoot and undershoot during load transient events. start-up, resulting in a relatively soft controlled start-up.

Figure 9. (a) Frequency Variation over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation over Line Half-Cycle as a Function of Load. Note: Frequency Profiles Shown were Analytically Derived and Reflect CCM Operation Across the Entire Line Cycle.

230 VAC

180 VAC

135 VAC

90 VAC

115 VAC

Figure 10. EcoSmart Frequency Slide V OFF vs. VE and VOFF(MAX) vs. Input Voltage. the average frequency extremes for high input line operation. ripple at light load is an artifact of efficient burst mode operation. high-impedance state (internal switch is in ‘off’ state).

output voltage has fallen below the user programmed V PG- threshold. fallen below the VFB_UV threshold for greater than t FB_UV seconds. with the POWER GOOD pin in a high-impedance state. indication to secondary circuits of an OT fault. Figure 11. Power Good Function Description. output power requirement for increased conversion efficiency. start-up sequence are satisfied. below brown-in and above input peak voltages of 400 V PK.

(NTC) thermistor in series with the input line. expires a shutdown will occur. brown-out shutdown will occur. limited to prevent long term damage to the IC. output short-circuit or overload fault conditions. (except in follower mode, as described in the subsequent sections). premature termination of the MOSFET conduction period. differential is small combined with too little inductor reset time. drop of 10 V) before switching is re-started. suspected short is validated. Figure 12. Line Dependent OCP.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Open FEEDBACK Pin Protection The FEEDBACK pin continuously sinks a static current of I FBPD [VCC > VCCUVLO+] to protect against a fault related to an open FEEDBACK pin or incomplete feedback divider network. The internal current sink introduces a small static offset to the output regulation which can be accounted for in selecting the output feedback regulation components (FEEDBACK pin divider). Hysteretic Thermal Shutdown The thermal shutdown circuitry senses the controller die temperature which is well coupled to the heat sink through the exposed, grounded pad. The threshold is set at 117 °C typical with a 36 °C hysteresis. When the controller die temperature rises above this threshold (OTP), the controller initiates a soft-shutdown and remains disabled until the controller die temperature falls by ~36 °C, at which point the device will re-initiate the start-up sequence. The maximum time delay for soft-shutdown to occur after an OTP event is detected is t OTP beyond the next zero-crossing. HiperPFS-3 Additional Features and Changes Note: HiperPFS-3 is not a pin for pin drop-in replacement of HiperPFS-2 due to functional changes and optimizations.

  • Improved operating supply voltage maximum: 15 V.
  • Reduced external component count.
  • Improved tolerance of key parameters over a wide temperature range.
  • Modified architecture improving noise immunity and operational accuracy.
  • Feedback network voltage divider is decoupled from the loop compensation components.
  • High-line only family of parts added to HiperPFS-3 family.
  • Peak-detector supports deglitch methodology for NTC in-rush current limiting at start-up.
  • Digital Power Factor Enhancer algorithm improves high-line light load power factor.
  • OTA error amplifier replaces voltage error amplifier of HiperPFS-2.
  • NLA implemented via fixed current sources for quick transient response, replaces switched voltage gain in HiperPFS-2.
  • Off-time controller senses actual feedback voltage to calculate off-time to prevent inductor saturation.
  • VOLTAGE MONITOR pin uses voltage-mode sensing rather than current-mode sensing of HiperPFS-2, allowing flexibility in selection of magnitude of resistor divider.
  • Reduced minimum line feed-forward gain supports higher power delivery during line sag events.
  • Line feed-forward gain implemented with true squaring function, versus piece-wise linear approximation.
  • Line voltage functions performed in the digital domain: peak detec - tion, feed-forward, brown-in/brown-out and PF-enhancement.
  • Peak detector incorporates filtering to smooth out cycle-to-cycle variation.
  • Optimized brown-in/brown-out thresholds with tighter tolerances.
  • Most timers are derived from an internal high-speed clock providing accurate timing.
  • eSIP-16 package pinout has been modified for optimal operation and internal grounding.
  • No-load/light-load power consumption optimized by re-engineered burst-mode operation.
  • Reduced control-engine power consumption: standby current reduced by ~4~5× HiperPFS-2 nominal.
  • HiperPFS-3 REFERENCE pin replaces HiperPFS-2 REFERENCE pin; external bypass capacitor replaces external 1% resistor.
  • VFB(REF) reduced to 3.85 V nominal from 6.0 V nominal in HiperPFS-2.
  • Peak detector optimized across maximum operational conditions when operating with distorted waveforms and line drop-outs.
  • Square-wave detector feature for improved UPS operation.
  • Power good function is independent of engine during operation except for OTP events.
  • FBOFF fault check is always enabled during operation.
  • Maximum CCM peak switching frequency has been increased from ~100 kHz to 123 kHz.

90 VAC2

180 VAC2

Table 2. Output Power Table.

  1. See Key Application considerations.
  2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
  3. Recommended lower range of maximum continuous power for best light load efficiency ; HiperPFS-3 will operate and perform below this level.
  4. Internal output power limit.

factor and overall efficiency from light load to full load. components across the input when AC is removed. ously charging output capacitor C17. drain and source of the MOSFET inside U1 at each switching edge. on the POWER GOOD THRESHOLD pin. connected to the REFERENCE pin. used to scale the output voltage and provide feedback to the IC.

250 VAC

320 VAC

275 VAC

Figure 13. 275 W PFC using PFS7527H.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Application Example 2 A High Efficiency, 750 W, 385 VDC High-Line Input PFC The circuit shown in Figure 14 is designed using a device from the HiperPFS- 3 family of integrated PFC controllers. This design is rated for a continuous output power of 750 W and provides a regulated output voltage of 385 VDC nominal, maintaining a high input power factor and overall efficiency from light load to full load. Fuse F1 provides protection to the circuit and isolates it from the AC supply in the event of a fault. Diode bridge BR1 and BR2 rectifies the AC input voltage. Capacitors C32, C33, C35, C36, C37, C38, C60, C61 and C62 together with inductors L1, L2 and L4 form the EMI filter which reduces the common mode and differential mode noise. Resistors R42, R43 and CAPZero, IC U5 are required to discharge the EMI filter capacitors once the circuit is disconnected. CAPZero eliminates static losses in R1 and R2 by only connecting these components across the input when AC is removed. Metal oxide varistor (MOV) RV1 protects the circuit during line surge events by effectively clamping the input voltage seen by the power supply. The boost converter stage consists of inductor T2, and the Hiper - PFS-3 IC U6. This stage functions as a boost converter and controls the input current of the power supply while simultaneously regulating the output DC voltage. Diode D8 prevents a resonant buildup of output voltage at start-up by bypassing inductor T2 while simultane - ously charging output capacitors C40 and C49. Thermistor RT1 limits the inrush input current of the circuit at start-up and prevents saturation of T2. In most high-performance designs, a relay will be used to bypass the thermistor after start-up to improve power supply efficiency. Thermistor RT1 is bypassed by the electro-mechanical relay RL1 after the output voltage is in regulation. Resistor R45, R46 and Q10 drive relay RL1 with a signal from Down Stage DC/DC converter. Diode D9 clamps the relay coil reverse voltage during de-assertion transitions. Capacitor C41 is used for reducing the loop length and area of the output circuit to reduce EMI and overshoot of voltage across the drain and source of the MOSFET inside U6 at each switching edge. The PFS7527H IC requires a regulated supply of 12 V for operation and must not exceed 15 V. Resistors R52, R71, Zener diode VR3, Diode D11 and transistor Q2 form a series pass regulator that prevents the supply voltage to IC U6 from exceeding 15 V. Capacitor C47 filter the supply voltage and provide bypassing and decoupling to ensure reliable operation of IC U6. Resistor R53 programs the output voltage level [via the power good threshold (PGT) pin] below which the power good [PG] pin will go into a high-impedance state. Capacitor C43 provides noise immunity on the POWER GOOD THRESHOLD pin. IC U6 is configured in full power mode by capacitor C44 which is connected to the REFERENCE pin. The rectified AC input voltage of the power supply is sensed by IC U6 using resistors R48, R50, R51 and R56. These resistors values are large to minimize power consumption. Capacitor C45 connected in parallel with the bottom resistor R56 filters noise coupled into the VOLTAGE MONITOR pin. Output voltage divider network comprising of resistors R47, R49, R55 and R57 are used to scale the output voltage and provide feedback to the IC. Capacitor C48 in parallel with resistor R57 attenuates high frequency noise. R54, C46 and C42 are required for shaping the loop response of the feedback network.

50 V R54

320 VAC180 - 264

Figure 14. 750 W PFC using PFS7539L/H.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Design, Assembly, and Layout Considerations Power Table The data sheet power table as shown in Table 2 represents the maximum practical continuous output power based on the following conditions: For the universal input devices (PFS7523L/H – PFS7529H): 1. An input voltage range of 90 VAC to 264 VAC. 2. Overall efficiency of at least 93% at the lowest operating voltage. 3. 385 V nominal output. 4. Sufficient heat sinking to keep device temperature ≤100 ºC. Operation beyond the limits stated above will require derating. Operation at elevated temperatures could result in reduced MTBF and performance degradation, e.g. reduced efficiency, reduced power limit, PF, and potential of observing hysteretic brown-out, etc., and is not recommended. Use of a nominal output voltage higher than 395 V is not recommended for HiperPFS-3 based designs. Operation at voltages higher than 395 V can result in higher than expected drain-source voltage during line and load transients. HiperPFS-3 Selection Selection of the optimum HiperPFS-3 part depends on required maximum output power, PFC efficiency and overall system efficiency (when used with a second stage DC-DC converter), heat sinking constraints, system requirements and cost goals. The HiperPFS-3 part used in a design can be easily replaced with the next higher or lower part in the power table to optimize performance, improve efficiency or for applications where there are thermal design constraints. Minor adjustments to the inductance value and EMI filter components may be necessary in some designs when the next higher or the next lower HiperPFS-3 part is used in an existing design for performance optimization. Every HiperPFS-3 family part has an optimal load level where it offers the most value. Operating frequency of a part will change depending on load level. Change of frequency will result in change in peak to peak current ripple in the inductance used. Change in current ripple will affect input PF and total harmonic distortion of input current. Input Fuse and Protection Circuit The input fuse should be rated for a continuous current above the input current at which the PFC turns-off due to input under- voltage. This voltage is referred to as the brown-out voltage. The fuse should also have sufficient I 2t rating in order to avoid nuisance failures during start-up. At start-up a large current is drawn from the input as the output capacitor charges to the peak of the applied voltage. The charging current is only limited by any inrush limiting thermistors, impedance of the EMI filter inductors and the forward resistance of the input rectifier diodes. A MOV will typically be required to protect the PFC from line surges. Selection of the MOV rating will depend on the energy level (EN1000-4-5 Class level) which the PFC is required to withstand. A suitable NTC thermistor should be used on the input side to provide inrush current limiting. Choice of this thermistor should depend on the inrush current specification for the power supply. NTC thermis - tors may not be placed in any other location in the circuit as they fail to limit the stress on the part in the event of line transients and also fail to limit the inrush current in a predictable manner. The example in Figure 13 shows the circuit configuration that has the inrush limiting NTC thermistor on the input side which is bypassed with a relay after PFC start-up. This arrangement ensures that a consistent inrush limiting performance is achieved by the circuit. Input EMI Filter The variable switching frequency of the HiperPFS-3 effectively modulates the switching frequency and reduces conducted EMI peaks associated with the harmonics of the fundamental switching frequency. This is particularly beneficial for the average detection mode used in EMI measurements. The PFC is a switching converter and will need an EMI filter at the input in order to meet the requirements of most safety agency standards for conducted and radiated EMI. Typically a common mode filter with X capacitors connected across the line will provide the required attenuation of high frequency components of input current to an acceptable level. The leakage reactance of the common mode filter inductor and the X capacitors form a low pass filter. In some designs, additional differential filter inductors may have to be used to supplement the differential mode inductance of the common-mode choke. A filter capacitor with low ESR and high ripple current capability should be connected at the output of the input bridge rectifier. This capacitor reduces the generation of the switching frequency compo- nents of the input current ripple and simplifies EMI filter design. Typically, 0.33 µF per 100 W should be used for universal input designs and 0.15 µF per 100 W of output power should be used for 230 VAC only designs. It is often possible to use a higher value of capacitance after the bridge rectifier and reduce the X capacitance in the EMI filter. Regulatory requirements require use of a discharge resistor to be connected across the input X capacitance on the AC side of the bridge rectifier. This is to ensure that residual charge is dissipated after the input voltage is removed when the capacitance is higher than 0.1 µF. Use of CAPZero integrated circuits from Power Integra - tions, helps eliminate the steady- state losses associated with the use of discharge resistors connected permanently across the X capacitors. Inductor Design For ferrite inductors the optimal design has K P of 0.3 to 0.45. (KP is defined as the current peak-to-peak value divided by the peak value at minimum AC voltage and 90* phase angle, full load). K P <0.3 (more continuous) tends towards excessive inductor size, while higher KP >0.45 tends towards excessive winding AC resistance losses due to large high-frequency AC currents, especially since most ferrite inductor designs will require >3 winding layers. Flux density at maximum current limit should be <3900 gauss to prevent core saturation. If Sendust core material is used, 90µ or 125µ material is recommended, because the higher µ materials tend to produce greater inductance at lower currents, and thus reduced peak- to-peak inductor currents at lower line phase angles (<45*) which reduces losses and improves PF at lighter loads and higher input voltages. The design target is for H at the peak current (low-line, full-load, 90* line phase angle) to be ~60 A-t/cm. Higher H tends towards excessive core loss, and lower than this increases AC copper losses. The HiperPFS-3 design spreadsheet simplifies this process and automatically recommends a core size and design for either ferrite or Sendust. For high performance designs, use of Litz wire is recommended to reduce copper loss due to skin effect and proximity effect. For toroidal inductors the numbers of layers should be less than 3 and for bobbin wound inductors, inter layer insulation should be used to minimize inter layer capacitance.

CO PFC output capacitance in F. PO PFC output power in watts. VOUT Lowest nominal output voltage of the PFC in volts. the end of hold-up time in volts. ΔVO Peak-peak output voltage ripple in volts. ηPFC PFC operating efficiency. IO(MAX) Maximum output current in amps. ately increased to account for ageing and tolerances. requires approximately ICC(ON) maximum for its operation. directly at the IC pin on the circuit board. these resistors. Only 1% tolerance resistors are recommended. directly at the IC pin on the circuit board. are outside the scope of this data sheet. VFB(REF) FEEDBACK pin voltage, 3.85 V. Figure 15. Recommended Feedback Circuit.

Figure 16. Heat Sink Assembly – using Thermally Conductive Adhesive.

  1. Thermally Conductive Adhesive
  2. Eyelet Terminal − Electrical Connection to Heat Sink

PO Maximum continuous output power in watts. VO Nominal PFC output voltage in volts. CO PFC output capacitance in farads. mechanical clip or adhesive thermal compound. source terminal in order to reduce EMI.

the high-voltage and high current nodes to minimize any interference. noise injection can lead to waveform instability or dissymmetry. from the drain node of the PFC inductor. the diode current traversing through the loop. connecting the feedback circuit components to the GROUND pin. output of the bridge rectifier. Figure 19. PCB Layout Example.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Quick Design Checklist As with any power supply design, all HiperPFS-3 designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that peak VDS does not exceed

530 V at lowest input voltage and maximum overload output

power. Maximum overload output power occurs when the output is overloaded to a level just above the highest rated load or before the power supply output voltage starts falling out of regulation. Additional external snubbers should be used if this voltage is exceeded. In most designs, addition of a ceramic capacitor in the range of 33 pF and 100 pF connected across the PFC output diode will reduce the maximum drain-source voltage to a level below the BVDSS rating. When measuring drain-source voltage of the MOSFET, a high-voltage probe should be used. When the probe tip is removed, a silver ring in the vicinity of the probe tip can be seen. This ring is at ground potential and the best ground connection point for making noise free measure - ments. Wrapping stiff wire around the ground ring and then connecting that ground wire into the circuit with the shortest possible wire length, and connecting the probe tip to the point being measured, ensures error free measurement. Probe should be compensated according to probe manufacturer’s guidelines to ensure error-free measurement. 2. Maximum drain current – Drain current can be measured indirectly by monitoring inductor current. A current probe should be inserted between the bridge rectifier and inductor connection. At maximum ambient temperature, minimum input voltage and maximum output load, verify drain current wave - forms at start-up for any signs of inductor saturation. When performing this measurement with Sendust inductor, it is typical to see inductor wave-forms that show exponential increase in current due to permeability drop. This should not be confused with hard saturation. 3. Thermal check – At maximum output power, minimum input voltage and maximum ambient temperature; verify that temperature specifications are not exceeded for the HiperPFS-3, PFC inductor, output diodes and output capacitors. Enough thermal margin should be allowed for the part-to-part variation of the RDS(ON) of HiperPFS-3, as specified in the data sheet. A maximum package temperature of 100 °C is recommended to allow for these variations. 4. Input PF should improve with load, if performance is found to progressively deteriorate with loading, it is a sign of possible noise pick-up by the VOLTAGE MONITOR pin circuit or the feedback divider network and the compensation circuit.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, -40 °C < TJ(C) < 125 °C (Note C) (Unless Otherwise Specified) Pin Min Typ Max Units Currents Undervoltage Current Consumption After Power-Up of Core and Zeners ICC(UVLO) VCC < UVLO+(min) V = 1 V, C = 0 V, FB = 3.85 V VCC 140 µA Standby Current Consumption – No Switching Prior to Brown-In ICC(STBY) V = 1 V, C = 0 V, FB = 3.85 V 0 °C < TJ(C) < 100 °C VCC 320 µA Current Consumption – in Burst Mode, No Switching ICC(BURST) FB = 3.85 V, C < VERR_MIN, V = 1.414 V (or 2.828 V for High-Line Only Parts) VCC 395 470 µA Absolute Maximum Ratings(1,2) Notes: 1. All voltages referenced to SOURCE, T A = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. The absolute maximum rating of the VCC is 17.5 V. This is an absolute maximum condition that must not be exceeded. Voltages between the max operating voltage (15 V) and this abs max rating should be very infrequent and short in duration (e.g. at start-up or temporary fault conditions). It is not intended as a guarantee of the reliability of the product up to the absolute maximum rating, but is a guideline as to the level of applied voltage above which there is a risk of immediate damage to the product. 4. Normally limited by internal circuitry. Applies to Controller T J(C), MOSFET TJ(M) and Diode Junction Temperature TJ(D). 5. 1/16” from case for 5 seconds. 6. Duration less than 15 ns and IDS ≤ IOCP(TYP). 7. TC(D) diode case temperature. Thermal Resistance Thermal Resistance: H/L Package: Notes: 1. Controller junction temperature (TJ(C)) may be less than the MOSFET Junction Temperature (TJ(M)) and Diode Junction Temperature (TJ(D)). Qspeed Diode PFS7523-7529 PFS7533-7535 PFS7536-7539 Peak Repetitive Reverse Voltage (VRRM) 530 V 530 V Average Forward Current IF(AV) TJ(D) = 150 °C 3 A 6 A Non-Repetitive Peak Surge Current (IFSM) 60 Hz, ½ cycle, TC(D) (7) = 25 °C 50 A 100 A Non-Repetitive Peak Surge Current (IFSM) t = 500 µs, TC(D) (7) = 25 °C 130 A 260 A

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units Currents (cont.) Operating Current ICC(ON) No-load on REF Switching at FMIN (TOFF = TOFF(MIN), TON = TON(MAX)) PFS7523 PFS7533 0.64 0.75 0.90 mA PFS7524 PFS7534 0.67 0.79 0.95 PFS7525 PFS7535 0.74 0.88 1.05 PFS7526 PFS7536 0.79 0.93 1.12 PFS7527 PFS7537 0.85 1.00 1.20 PFS7528 PFS7538 0.91 1.07 1.28 PFS7529 PFS7539 0.98 1.15 1.38 Leakage Current in UVLO State Ioz 0 < Pin Voltage < REF 0 °C < TJ(C) < 100 °C V, FB, C, PGT ±10 nA VPG = 12 V PG ±0.1 µA Pull-Down Current on Feedback IFB(PD) Not Active When VCC < UVLO+ FB 100 nA Pull-Down Current on Voltage IV(PD) Not Active When VCC < UVLO+ V 100 nA On-Time Controller Maximum Operating “On”-Time tON(MAX) 0 °C < TJ(C) < 100 °C 29 34 40 µs Off-Time Controller Maximum Operating “Off”-Time tOFF(MAX) 0 °C < TJ(C) < 100 °C 36 43 48 µs Off-Time Accuracy tOFF(ACCURACY) V = 1.414 V (or 2.828 V for High-Line Only) FB = 3.85 V C > = 4 V ±4.0 % Feedback Feedback Voltage Reference VFB(REF) TJ(C) = 25 °C 3.82 3.85 3.88 V 0 °C < TJ(C) < 100 °C 3.75 3.85 3.95 Feedback Error- Amplifier Transconduc- tance Gain GM 3.75 V < VFB < 3.95 V VC = 4 V 75 95 105 µA/V Soft-Shutdown Time tSHUTDWN See Note A 0.86 1.00 1.16 ms FEEDBACK Pin Start-Up/Fault Threshold VFB(OFF) 0 °C < TJ(C) < 100 °C 0.57 0.64 0.71 V

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units Feedback (cont.) FEEDBACK Pin Undervoltage Assertion Threshold VFB(UV) 0 °C < TJ(C) < 100 °C 2.09 2.25 2.36 V FEEDBACK Pin Overvoltage Assertion Threshold FEEDBACK Pin Over- voltage Assertion Relative Threshold VFB(OV+REL_FB) 0 °C < TJ(C) < 100 °C VFBREF +0.19 VFBREF +0.245 VFBREF +0.30 FEEDBACK Pin Overvoltage Deassertion Threshold FEEDBACK Pin Over- voltage Deassertion Relative Threshold VFB(OV-REL_FB) 0 °C < TJ(C) < 100 °C VFBREF +0.11 VFBREF +0.16 VFBREF +0.21 FEEDBACK Pin Overvoltage Hysteresis VFB(OVHYST) 0 °C < TJ(C) < 100 °C 0.070 0.085 0.115 V COMPENSATION Pin PF Enhancer Disable Threshold VLOW(LOAD+) See Note A 1.1 V COMPENSATION Pin PF Enhancer Enable Threshold VLOW(LOAD-) See Note A 1.0 V COMPENSATION Pin PF Enhancer Threshold Hysteresis VLOW(LOAD_HYST) See Note A 0.1 V COMPENSATION Pin Burst Disable Threshold VERR(MIN+) 0 °C < TJ(C) < 100 °C 0.19 V COMPENSATION pin Burst Enable Threshold VERR(MIN-) 0 °C < TJ(C) < 100 °C 0.1 V COMPENSATION Pin Burst Threshold Hysteresis VERR(HYST) 0 °C < TJ(C) < 100 °C 0.09 V Line-Sense/Peak Detector Line-Sense Input Voltage Range VV(RANGE) See Note A 0 4 V Brown-In Threshold Voltage VBR+ Universal Input Devices (PFS7523-PFS7529) 1.08 1.12 1.16 V High-Line Only Input Devices (PFS7533-PFS7539) 2.30 2.35 2.42

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units Line-Sense/Peak Detector (cont.) Brown-Out Threshold Voltage VBR- Universal Input Devices (PFS7523-PFS7529) 0.93 0.97 1.02 V High-Line Only Input Devices (PFS7533-PFS7539) 2.15 2.21 2.27 Brown-In/Out Hysteresis (After NTC Warm-Up Time) VBR(HYS) 0 °C < TJ(C) < 100 °C 0.13 0.145 0.160 V Brown-Out Threshold for High Duty Cycle Square Wave VBR(SQ) Universal Input Devices (PFS7523-PFS7529) 0.86 V High-Line Only Input Devices (PFS7533-PFS7539) 1.93 Start-Up Brown-Out Threshold Voltage (During NTC Warm-Up Time) VBR(NTC) Universal Input Devices (PFS7523-PFS7529) 0.74 V High-Line Only Input Devices (PFS7533-PFS7539) 1.57 Brown-Out NTC Debounce Timer tBRWNOUT(NTC) See Note A 875 1000 1160 ms Brown-Out Debounce Timer tBRWNOUT See Note A 43 54 66 ms Start-Up Timer for Using Lower brown-Out Threshold (V BR-NTC) tSTARTUP See Note A 875 1000 1160 ms VOLTAGE Pin High-Line Assertion Threshold VV(HIGH+) See Note A 2.42 V VOLTAGE Pin High-Line Deassertion Threshold VV(HIGH-) See Note A 2.00 V VOLTAGE Pin Minimum Asserted Peak Value VPK(MIN) See Note A 0.71 V Current Limit/Circuit Protection Over-Current Protection PFS7523L/H di/dt = 250 mA/µs TJ(C) = 25 °C VV < 2 V 3.8 4.1 4.3 A VV > 2.42 V 2.6 2.8 3.0 PFS7524L/H di/dt = 300 mA/µs TJ(C) = 25 °C VV < 2 V 4.5 4.8 5.1 VV > 2.42 V 3.0 3.3 3.5

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specfied) Min Typ Max Units Current Limit/Circuit Protection (cont.) Over-Current Protection IOCP PFS7525L/H di/dt = 400 mA/µs TJ(C) = 25 °C VV < 2 V 5.5 5.9 6.2 A VV > 2.42 V 3.6 4.0 4.4 PFS7526H di/dt = 500 mA/µs TJ(C) = 25 °C VV < 2 V 6.8 7.2 7.5 VV > 2.42 V 4.6 4.9 5.25 PFS7527H di/dt = 650 mA/µs TJ(C) = 25 °C VV < 2 V 8.0 8.4 8.8 VV > 2.42 V 5.35 5.8 6.2 PFS7528H di/dt = 800 mA/µs TJ(C) = 25 °C VV < 2 V 9.0 9.5 9.9 VV > 2.42 V 6.0 6.5 7.1 PFS7529H di/dt = 920 mA/µs TJ(C) = 25 °C VV < 2 V 10 10.5 11 VV > 2.42 V 6.7 7.2 7.7 PFS7533H di/dt = 250 mA/µs TJ(C) = 25 °C 3.8 4.1 4.3 PFS7534H di/dt = 300 mA/µs TJ(C) = 25 °C 4.5 4.8 5.1 PFS7535H di/dt = 400 mA/µs TJ(C) = 25 °C 5.5 5.9 6.2 PFS7536H di/dt = 500 mA/µs TJ(C) = 25 °C 6.8 7.2 7.5 PFS7537H di/dt = 650 mA/µs TJ(C) = 25 °C 8.0 8.4 8.8 PFS7538H di/dt = 800 mA/µs TJ(C) = 25 °C 9.0 9.5 9.9 PFS7539L/H di/dt = 920 mA/µs TJ(C) = 25 °C 10 10.5 11

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection (cont.) Normalized Frequency at Power Limit FLIM CREF = 1.0 µF TJ(C) = 25 °C ±7 SOA Protection Fixed Off-Time tOFF(SOA) TJ(C) = 25 °C 200 250 300 µs Leading Edge Blanking (LEB) Time Period tLEB TJ(C) = 25 °C See Note A 220 ns Minimum On-Time in IOCP tON_OCP(MIN) TJ(C) = 25 °C 400 ns VCC Auxiliary Power Supply VCC Operating Range VCC UVLO+ 12 15 V Start-Up VCC (Rising Edge) VCCUV(LO+) 0 °C < TJ(C) < 100 °C 9.6 9.85 10.1 V Shutdown VCC (Falling Edge) VCCUV(LO-) 0 °C < TJ(C) < 100 °C 9.05 9.3 9.55 V VCC Hysteresis VCC(HYS) 0 °C < TJ(C) < 100 °C 0.50 0.57 0.65 V UVLO Shutdown Delay Timer tUV(LO-) See Note A 500 ns Time From VCC > VCCUVLO+ Until Device Commences Switching tRESET V > VBR+ See Note A 60 75 ms Series Regulator REFERENCE Pin Voltage VREF 0 °C < TJ(C) < 100 °C 4.95 5.25 5.45 V REFERENCE Pin Required Capacitance CREF Full Power Mode 0.8 1.0 µF Efficiency Mode 0.08 0.1 0.2 REFERENCE Pin UVLO Rising Edge REFUV+ See Note A 5.0 V REFERENCE Pin UVLO Falling Edge REFUV- See Note A 4.4 V Power Good Power Good Deasser - tion Threshold Output Reference Current IPG(T) 0 °C < TJ(C) < 100 °C; VPGT = 3.0 V -10.65 -10 -9.35 µA Power Good Delay Time (From FB > VPG+ to PG < 1 V) tPG 0 °C < TJ(C) < 100 °C; PG = 20 kΩ Pull-Up to VCC, See Note A <15 µs Power Good Deglitch Time tPG(D) See Note A 57 81 108 µs

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units Power Good (cont.) Power Good Internal Assertion Threshold VPG(+) 0 °C < TJ(C) < 100 °C 3.55 3.65 3.75 V Power Good Relative Threshold VPG+REL(FB) 0 °C < TJ(C) < 100 °C VFBREF -0.24 VFBREF -0.20 VFBREF -0.16 Power Good Deassertion Threshold VPG(-) V (PGT) = 3 V 0 °C < TJ(C) < 100 °C 2.94 V (PGT) ±30 mV 3.06 V POWER GOOD Pin Leakage Current in Off-State IOZHPG FB < VPG- 0 °C < TJ(C) < 100 °C 500 nA POWER GOOD Pin On-State Voltage VOLPG IPG = 2.0 mA; FB = 3.85 V 2 V Thermal Protection (OTP) Controller Junction Temperature (TJ(C)) for Shutdown TOTP+ See Note A 117 °C Controller Junction Temperature (TJ(C)) for Restart TOTP- See Note A 81 °C Over-Temperature Hysteresis TOTP(HYST) V > VBR+ See Note A 36 °C VTS MOSFET On-State Resistance RDS(ON) ID = 0.5 × IOCP PFS7523 PFS7533 Ω TJ(M) =100 °C 1.10 PFS7524 PFS7534 PFS7525 PFS7535 PFS7526 PFS7536 PFS7527 PFS7537 PFS7528 PFS7538 PFS7529 PFS7539 TJ(M)= 100 °C 0.40

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, (Note C) (Unless Otherwise Specified) Min Typ Max Units VTS MOSFET Effective Output Capacitance Coss TJ(M) = 25 °C VGS = 0 V, VDS = 0 to 80% BVDSS See Note A PFS7523 PFS7533 176 pF PFS7524 PFS7534 210 PFS7525 PFS7535 265 PFS7526 PFS7536 312 PFS7527 PFS7537 369 PFS7528 PFS7538 420 PFS7529 PFS7539 487 Breakdown Voltage BVDSS TJ(M) = 25 °C, VCC = 12 V ID = 250 µA, VFB= VV = 0 V 530 V Breakdown Voltage Temperature Coefficient BVDSS(TC) See Note A 0.048 %/°C Off-State Drain Current Leakage IDSS VDS = 80% BVDSS VCC = 12 V VFB = VV = VC = 0 PFS7523 PFS7533 TJ(M) =100 °C 80 µA PFS7524 PFS7534 TJ(M) =100 °C 100 PFS7525 PFS7535 TJ(M) =100 °C 120 PFS7526 PFS7536 TJ(M) =100 °C 150 PFS7527 PFS7537 TJ(M) =100 °C 170 PFS7528 PFS7538 TJ(M) =100 °C 200 PFS7529 PFS7539 TJ(M) =100 °C 235 Turn-Off Voltage Rise Time tR See Notes A, B, C 50 ns Turn-On Voltage Fall Time tF See Notes A, B, C 100 ns

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions Min Typ Max Units Qspeed Diode (3A) PFS7523-7529/7533-7535 DC Characteristics Reverse Current IR VR = 530 V TJ(D) = 25 °C 0.4 µA TJ(D) = 100 °C 0.07 mA Forward Voltage VF IF = 3 A TJ(D) = 25 °C 1.55 V Junction Capacitance CJ VR = 10 V, 1 MHz 18 pF Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition) Reverse Recovery Time tRR di/dt = 200 A/µs, VR = 400 V IF = 3 A TJ(D) = 25 °C 26.5 ns TJ(D) = 100 °C 32 Reverse Recovery Charge QRR di/dt = 200 A/µs, VR = 400 V IF = 3 A TJ(D) = 25 °C 40.6 nC Maximum Reverse Recovery Current IRRM di/dt = 200 A/µs, VR = 400 V IF = 3 A TJ(D) = 25 °C 2.1 A TJ(D) = 100 °C 3.0 Softness Factor = t B/tA S di/dt = 200 A/µs, VR = 400 V IF = 3 A TJ(D) = 25 °C 1

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com NOTES: A. Not tested parameter. Guaranteed by design. B. Tested in typical Boost PFC application circuit. C. Normally limited by internal circuitry. D. Test under this condition may require pulsed operation due to self-heat. Pulse parameters (duration, repetition) are TBD. E. BVDSS 540 V maximum for 10 ns. Parameter Symbol Conditions Min Typ Max Units Qspeed Diode (6A) PFS7536-7539 DC Characteristics Reverse Current IR VR = 530 V TJ(D) = 25 °C 0.8 µA TJ(D) = 100 °C 0.15 mA Forward Voltage VF IF = 6 A TJ(D) = 25 °C 1.51 V Junction Capacitance CJ VR = 10 V, 1 MHz 41 pF Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition) Reverse Recovery Time tRR di/dt = 200 A/µs, VR = 400 V IF = 6 A TJ(D) = 25 °C 28.5 ns Reverse Recovery Charge QRR di/dt = 200 A/µs, VR = 400 V IF = 6 A TJ(D) = 25 °C 58 nC TJ(D) = 100 °C 105.5 Maximum Reverse Recovery Current IRRM di/dt = 200 A/µs, VR = 400 V IF = 6 A TJ(D) = 25 °C 2.95 A Softness Factor = t B/tA S di/dt = 200 A/µs, VR = 400 V IF = 6 A TJ(D) = 25 °C 0.53

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com PI-7242-010614 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.038 (0.97) 0.076 (1.93) 0.118 (3.00)

0.029 Dia Hole

0.062 Dia Pad

0.020 (0.50) 0.016 (0.41) Ref. Detail A 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.290 (7.37) Ref. 0.047 (1.19) C 1 3 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.076 (1.93) 0.012 (0.30) Ref. 0.207 (5.26) 0.187 (4.75) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.519 (13.18) Ref. FRONT VIEW SIDE VIEW BACK VIEW PCB FOOT PRINT END VIEW eSIP-16D (H Package) Dimensions in inches, (mm). All dimensions are for reference. 0.586 (14.88) Ref. 0.216 (5.49) Ref.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com PI-7256-012114 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 0.038 (0.97) 0.076 (1.93) 0.094 (2.40) FRONT VIEW SIDE VIEW BACK VIEW PCB FOOT PRINT END VIEW eSIP-16G (L Package) 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) Dimensions in inches, (mm). All dimensions are for reference. 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.038 (0.97) Typ. 9 Places 0.056 (1.42) Ref. 468101316 5791114 C 0.128 (3.26) 0.122 (3.10) 0.081 (2.06) 0.077 (1.96) Detail A 0.094 (2.40) 0.047 (1.19) Ref. 0.050 (1.26) Ref. 0.144 (3.66) Ref. 0.290 (7.37) Ref. 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.076 (1.93) Typ. 3 Pieces 0.173 (4.39) 0.163 (4.14) 0.079 (1.99) 0.069 (1.74) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) R0.012 (0.30) Typ., Ref. 0.586 (14.88) Ref. 0.216 (5.49) Ref.

Rev. D 04/25 PFS7523-7529/7533-7539 www.power.com Part Marking Information

  • HiperPFS Product Family
  • HiperPFS-3 Series Number
  • Package Identifier L Plastic eSIP, L Bend H Plastic eSIP Part Ordering Information Part Number Option Quantity PFS7523L/H Tube 30 PFS7524L/H Tube 30 PFS7525L/H Tube 30 PFS7526H Tube 30 PFS7527H Tube 30 PFS7528H Tube 30 PFS7529H Tube 30 PFS7533H Tube 30 PFS7534H Tube 30 PFS7535H Tube 30 PFS7536H Tube 30 PFS7537H Tube 30 PFS7538H Tube 30 PFS7539L/H Tube 30 PFS 7523 L

A Initial Release. 06/15 B Internal review. 02/20 C Added PFS7539L part. 07/24 D Updated Figure 9b and added 750 W application section. 04/25 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at https://www.power.com/company/intellectual-property-licensing/. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2024, Power Integrations, Inc. World Headquarters

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