PFS7324L

PFS7323 POWERINT

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

www.powerint.com June 2013 High Power PFC Controller with Integrated High-Voltage MOSFET and Qspeed™ Diode Key Benefits

• Highly integrated for smallest boost PFC form factor
• Integrated controller and MOSFET in all package options
• Ultra-low reverse recovery loss diode (Qspeed) included in extended eSIP™ package option
• Lossless internal current sense reduces component count and system losses
• EN61000-3-2 Class C and D compliant
• Packaging optimized for high volume production
• Exposed pad connected to GROUND pin (CoolPAD)
• Eliminates insulating pad/heat-spreader
• Enhanced features
• Programmable power good (PG) signal
• User selectable power limit: Enables device swapping in a given design to optimize efficiency/cost
• Integrated non-linear amplifier for fast output OV and UV protection
• High efficiency and power factor across load range
• >95% efficiency from 10% load to full load
• <200 mW no-load consumption at 230 VAC in remote off-state
• Light load PF >0.9 at 20% load on optimized designs >200 W
• PF >0.95 at 50% load
• Enables 80+ Platinum designs
• Frequency adjusted over line voltage and each line cycle
• Spread-spectrum across >60 kHz window simplifies EMI filtering requirements
• Lower boost inductance
• Provides up to 425 W peak output power
• >425 W peak power in power limit voltage regulation mode

Figure 1. Typical Application Schematic.

90 VAC (in Full Mode)

Table 1. Output Power Table (See Table 2 on page 11 for Maximum Continuous

• Protection features include: UV, OV, OTP , brown-in/out, cycle-by-cycle current limit and power limiting for overload protection
• Halogen free and RoHS compliant

Applications

• PC • High-power adaptors
• Printer • High-power LED lighting
• LCD TV • Industrial and appliance
• Video game consoles • Generic PFC converters

Rev. B 06/13 PFS7323-7329 www.powerint.com

Description

The HiperPFS-2 device family members reach a very high level of integration including a continuous conduction mode (CCM) boost PFC controller, gate driver, ultra-low reverse recovery (Qspeed) diode (eeSIP™ package options) and high-voltage power MOSFET in a single, low-profile CoolPAD (GROUND pin connected) power package that is able to provide near unity input power factor. The HiperPFS-2 devices eliminate the PFC converter’s need for external current sense resistors, the power loss associated with those components, and leverages an innovative control technique that adjusts the switching frequency over output load, input line voltage, and even input line cycle. This control technique is designed to maximize efficiency over the entire load range of the converter, particularly at light loads. Additionally, this control technique significantly minimizes the EMI filtering requirements due to its wide bandwidth spread spectrum effect. The HiperPFS-2 also features an integrated non-linear amplifier for enhanced load transient response, a user programmable power good (PG) signal as well as user selectable power limit functionality. HiperPFS-2 includes Power Integrations’ standard set of comprehensive protection features, such as integrated soft-start, UV, OV, brown-in/out, and hysteretic thermal shutdown. HiperPFS-2 also provides cycle-by-cycle current limit for the power MOSFET, power limiting of the output for overload protection, and pin-to-pin short-circuit protection. HiperPFS-2’s innovative variable frequency continuous conduction mode of operation (VF-CCM) minimizes switching losses by maintaining a low average switching frequency, while also varying the switching frequency in order to suppress EMI, the traditional challenge with continuous conduction mode solutions. Systems using HiperPFS-2 typically reduce the total X and Y capacitance requirements of the converter, the inductance of both the boost choke and EMI noise suppression chokes, reducing overall system size and cost. Additionally, compared with designs that use discrete MOSFETs and controllers, HiperPFS-2 devices dramatically reduce component count and board footprint while simplifying system design and enhancing reliability. The innovative variable frequency, continuous conduction mode controller enables the HiperPFS-2 to realize all of the benefits of continuous conduction mode operation while leveraging low-cost, small, simple EMI filters. Many regions mandate high power factor for many electronic products with high power requirements. These rules are combined with numerous application-specific standards that require high power supply efficiency across the entire load range, from full load to as low as 10% load. High efficiency at light load is a challenge for traditional PFC approaches in which fixed MOSFET switching frequencies cause fixed switching losses on each cycle, even at light loads. Besides featuring relatively flat efficiency across the load range, HiperPFS-2 also enables higher power factor at light loads. HiperPFS-2 simplifies compliance with new and emerging energy-efficiency standards over a broad market space in applications such as PCs, LCD TVs, notebooks, appliances, pumps, motors, fans, printers, and LED lighting. HiperPFS-2 advanced power packaging technology and high efficiency simplifies the complexity of mounting the package and thermal management, while providing very high power capabilities in a single compact package; these devices are suitable for PFC applications from 75 W to 425 W. Product Highlights Protected Power Factor Correction Solution

• Incorporates high-voltage power MOSFET, ultra-low reverse recovery loss Qspeed diode, controller, and gate driver
• EN61000-3-2 Class D and Class C compliance
• Integrated protection features reduce external component count
• Accurate built-in brown-in/out protection
• Accurate built-in undervoltage (UV) protection
• Accurate built-in overvoltage (OV) protection
• Hysteretic thermal shutdown (OTP)
• Internal power limiting function for overload protection
• Cycle-by-cycle power switch current limit
• Internal non-linear amplifier for enhanced load transient response
• No external current sense required
• Provides ‘lossless’ internal sensing via sense-FET
• Reduces component count and system losses
• Minimizes high current gate drive loop area
• Minimizes output overshoot and stresses during start-up
• Integrated power limit and frequency soft-start
• Improved dynamic response
• Input line feed-forward gain adjustment for constant loop gain across entire input voltage range
• Eliminates up to 40 discrete components for higher reliability and lower cost Intelligent Solution for High Efficiency and Low EMI
• Continuous conduction mode PFC uses novel constant volt/ amp-second control engine
• High efficiency across load
• High power factor across load
• Low cost EMI filter
• Frequency sliding technique for light load efficiency improvements
• >95% efficiency from 10% load to full load at nominal input voltages
• Variable switching frequency to simplify EMI filter design
• Varies over line input voltage to maximize efficiency and minimize EMI filter requirements
• Varies with input line cycle voltage by >60 kHz to maximize spread spectrum effect Advanced Package for High Power Applications
• Up to 425 W peak output power capability in a highly compact package
• Simple adhesive or clip mounting to heat sink
• No insulation pad required and can be directly connected to heat sink
• Staggered pin arrangement for simple routing of board traces and high-voltage creepage requirements
• Single package solution for PFC converter reduces assembly costs and layout size

bypass any switching noise present on the rectified DC bus. This pin also features brown-in/out detection thresholds. value of 470 pf and 1 nF for the ‘Efficiency’ mode with 49.9 kW. This pin is used for loop compensation and voltage feedback. compensation components comprising of a series RC network. close to the device on the PCB to bypass any switching noise. main voltage divider network at start-up. GOOD THRESHOLD and SIGNAL GROUND pins. POWER GOOD THRESHOLD pin resistor. POWER pin from exceeding 15 VDC. This pin is the source connection of the power switch. This is the drain connection of the internal power switch. This is the cathode connection of the internal Qspeed Diode. Figure 2. Pin Configuration.

Figure 3. Functional Block Diagram. on-time and constant volt-second off-time control algorithm. inductor and thus regulates the output voltage and power.

Figure 9. (a) Frequency Variation Over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation Over Line Half-Cycle as a Function of Load.

180 VAC

135 VAC

115 VAC

90 VAC

Figure 10. VOFF vs. VE and VOFF vs. Input Voltage. valid range. Figure 8 illustrates this sequence.

of the maximum value at low input line conditions. a result of the burst-mode operation. boost converter is designed with a ferrite boost choke. rises to ~95% (VPG(H) threshold) of the set output voltage threshold. signal is in a high-impedance state (internal switch is in ‘off’ state). Figure 11. Power Good Function Description. voltage falls out of regulation. programmed VPG(L) threshold. by the REFERENCE pin resistor fault.

Rev. B 06/13 PFS7323-7329 www.powerint.com Temporarily reducing the brown-out threshold prevents false turn-off at high power start-up when voltage drop across the input bridge rectifier and filter stage may cause the rectified input to sag below the brown-out threshold. Increasing the brown-out timer during soft-start permits a longer time for an in-line AC-side NTC to reduce its resistance and increase the voltage presented to the VOLTAGE MONITOR pin. In the event the converter does not reach regulation at start-up (overload or power limit condition) C UV protection threshold is not activated and both the IUV(SS) and tUV(SS) are not reset. It is expected that while the input voltage peak is below the brown-out threshold (I UV-) during a line cycle drop out or line sag event the internal peak detector will force refresh the line feed-forward gain (mON) to the minimum value at the tREFRESH sample rate. Similar to the original HiperPFS, the controller latches the OCP threshold in the event of an AC line cycle drop-out when the peak sense is for a high input line condition (V IN > 170 VAC). Fast Output Voltage Overvoltage Protection (FB OV) This family features a FEEDBACK pin that is connected directly to the output voltage resistor divider network to permit fast feedback information to the controller for fast load transient response. The COMPENSATION pin which is also connected to the voltage divider network includes a resistor to isolate the slow feedback path and loop compensation network into the controller for steady-state output voltage regulation. Comparators on the FEEBACK and COMPENSATION pins are used to verify that the pins are not open-circuited and that the main voltage divider voltage at start-up is greater than FB OFF and COFF in order to complete the start-up fault detect sequence. After start-up the FBOFF and COFF thresholds remain enabled. Similarly to the original HiperPFS, this controller includes internal FBOV (FEEDBACK pin overvoltage), COV (COMPENSATION pin overvoltage) and CUV (COMPENSATION pin undervoltage) protection thresholds that are detected through the FEEDBACK and COMPENSATION pins. Deglitch filters (tFB(OV) and tC(UV)) are also used to prevent the controller from falsely triggering this protection mode. A FBOV event in excess of the tFB(OV) delay will terminate the switch cycle immediately. The COMPENSATION pin also features an output voltage undervoltage detection threshold to detect an overload or open-loop condition (broken feedback). In the event the falling edge of the voltage on the COMPENSATION pin falls below the CUV threshold, the MOSFET is disabled and the soft-start start-up sequence is initiated. The COMPENSATION pin undervoltage protection (C UV) mode is disabled during start-up and enabled once the COMPENSATION pin voltage exceeds approximately 5.8 V. The brown-out threshold is also reset from IUV(SS) to IUV- under the same conditions as activation of the CUV threshold. VCC Undervoltage Protection (UVLO) The BIAS POWER (VCC) pin has an undervoltage lock-out protection which inhibits the IC from starting unless the applied VCC voltage is above the VCC+ threshold. The IC initiates a soft-start once the VCC pin voltage exceeds the VCC+ threshold. After start-up the IC will continue to operate until the VCC pin voltage has fallen below VCC- level. The absolute maximum voltage of the VCC pin is 15 V which must be externally limited to prevent damage to the IC. Over-Current Protection The device includes a cycle-by-cycle over-current-protection (OCP) mode which protects the device in the event of a catastrophic fault. The OCP mode in the HiperPFS-2 is input line dependent as shown in Figure 13. The intention of OCP in this device is strictly protection of the internal power MOSFET and is not intended to protect the converter from output short-circuit or overload fault conditions. The HiperPFS-2 latches the high input line OCP for a 1/2 line cycle and updates the OCP status after the expiration of a 5 ms block-out timer. This feature has particular benefit for hard-start after an AC line cycle drop where the peak detector may falsely detect a low input line condition even though the input is at high input line. A leading edge blanking circuit inhibits the current limit comparator for a short time (t LEB) after the power MOSFET is turned on. This leading edge blanking time is set so that current spikes caused by capacitance and rectifier reverse recovery time will not cause premature termination of the MOSFET conduction. Safe Operating Area (SOA) Mode Since the cycle-by-cycle OCP mechanism described above does not prevent the possibility of inductor current ‘stair-casing’, an SOA mode is also featured. Rapid buildup of the device current can occur in the event of inductor saturation or when the input and output voltages are equal (no or very short inductor reset time). The SOA mode is triggered whenever the device reaches current limit (IOCP) and the on-time is less than tSOA. The SOA mode forces an off-time equal to t OCP and pulls the internal error-voltage (VE) down to approximately 1/2 of its set value. Open FEEDBACK Pin Protection The FEEDBACK pin also features a static current of I FB that is continuously sourced out of the pin to protect against a fault related to an open FEEDBACK pin. The internal current source introduces a static offset to the output regulation which must be accounted for in selecting the output feedback regulation components.

90 VAC2

Table 2. Output Power Table.

1. See Key Application considerations.
2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended lower range of maximum continuous power for best light load efficiency; HiperPFS-2 will operate and perform below this level.
4. Internal output power limit.

operation the OTP hysteresis is disabled. OTP event is detected is tREFRESH. again because of insufficient time to cool down the controller. brown-in will have hysteresis enabled.

device from the HiperPFS-2 family of integrated PFC controllers. thermistor after start-up to improve power supply efficiency. that prevents the supply voltage to IC U1 from exceeding 12 V. provides reverse polarity protection. decouples REFERENCE pin of IC U1. voltage overshoot or undershoot resulting from transient loading. C12 by safely shutting down the IC. Figure 14. 350 W PFC using PFS7328H.

250 VAC

275 VAC

320 VAC

Rev. B 06/13 PFS7323-7329 www.powerint.com Design, Assembly, and Layout Considerations Power Table The data sheet power table as shown in Table 2 represents the maximum practical continuous output power based on the following conditions: For the universal input devices (PFS7323L -PFS7329H): 1. An input voltage range of 90 VAC to 264 VAC. 2. Overall efficiency of at least 93% at the lowest operating voltage. 3. 385 V nominal output. 4. Sufficient heat sinking to keep device temperature ≤100 ºC. Operation beyond the limits stated above will require derating. Use of a nominal output voltage higher than 390 V is not recommended for HiperPFS-2 based designs. Operation at voltages higher than 390 V can result in higher than expected drain-source voltage during line and load transients. HiperPFS-2 Selection Selection of the optimum HiperPFS-2 part depends on required maximum output power, PFC efficiency and overall system efficiency (when used with a second stage DC-DC converter), heat sinking constraints, system requirements and cost goals. The HiperPFS-2 part used in a design can be easily replaced with the next higher or lower part in the power table to optimize performance, improve efficiency or for applications where there are thermal design constraints. Minor adjustments to the inductance value and EMI filter components may be necessary in some designs when the next higher or the next lower HiperPFS-2 part is used in an existing design for performance optimization. Every HiperPFS-2 family part has an optimal load level where it offers the most value. Operating frequency of a part will change depending on load level. Change of frequency will result in change in peak-to-peak current ripple in the inductance used. Change in current ripple will affect input PF and total harmonic distortion of input current. Input Fuse and Protection Circuit The input fuse should be rated for a continuous current above the input current at which the PFC turns-off due to input under voltage. This voltage is referred to as the brown-out voltage. The fuse should also have sufficient I 2t rating in order to avoid nuisance failures during start-up. At start a large current is drawn from the input as the output capacitor charges to the peak of the applied voltage. The charging current is only limited by any inrush limiting thermistors, impedance of the EMI filter inductors, ESR of output capacitor and the forward resistance of the input rectifier diodes. A MOV will typically be required to protect the PFC from line surges. Selection of the MOV rating will depend on the energy level (EN1000-4-5 Class level) to which the PFC is required to withstand. A suitable NTC thermistor should be used on the input side to provide inrush current limiting. Choice of this thermistor should be made depending on the inrush current specification for the power supply. NTC thermistors may not be placed in any other location in the circuit as they fail to limit the stress on the part in the event of line transients and also fail to limit the inrush current in a predictable manner. Example shown in Figure 14 shows the circuit configuration that has the inrush limiting NTC thermistor on the input side which is bypassed with a relay after PFC start-up. This arrangement ensures that a consistent inrush limiting performance is achieved by the circuit. Input EMI Filter The variable switching frequency of the HiperPFS-2 effectively modulates the switching frequency and reduces conducted EMI peaks associated with the harmonics of the fundamental switching frequency. This is particularly beneficial for the average detection mode used in EMI measurements. The PFC is a switching converter and will need an EMI filter at the input in order to meet the requirements of most safety agency standards for conducted and radiated EMI. Typically a common mode filter with X capacitors connected across the line will provide the required attenuation of high frequency components of input current to an acceptable level. The leakage reactance of the common mode filter inductor and the X capacitors form a low pass filter. In some designs, additional differential filter inductors may have to be used to supplement the differential inductance of the common mode choke. A filter capacitor with low ESR and high ripple current capability should be connected at the output of the input bridge rectifier. This capacitor reduces the generation of the switching frequency components of the input current ripple and simplifies EMI filter design. Typically, 0.33 mF per 100 W should be used for universal input designs and 0.15 mF per 100 W of output power should be used for 230 VAC only designs. It is often possible to use a higher value of capacitance after the bridge rectifier and reduce the X capacitance in the EMI filter. Regulatory requirements require use of a discharge resistor to be connected across the input (X) capacitance on the AC side of the bridge rectifier. This is to ensure that residual charge is dissipated after the input voltage is removed when the capacitance is higher than 0.1 mF. Use of CAPZero integrated circuits from Power Integrations, helps eliminate the steady- state losses associated with the use of discharge resistors connected permanently across the X capacitors. Inductor Design It is recommended that the inductor be designed with the maximum operating flux density less than 0.3 T and a peak flux density less than 0.39 T at maximum current limit when a ferrite core is used. If a core made from Sendust or MPP is used, the flux density should not exceed 1 T. A powder core inductor will have a significant drop in inductance when the flux density approaches 1 T.

to reduce copper loss due to skin effect and proximity effect. of 0.6 is recommended for an optimal design. would be required to be used. CO PFC output capacitance in F. PO PFC output power in watts. VOUT Lowest nominal output voltage of the PFC in volts. the end of hold-up time in volts. ∆VO Peak-peak output voltage ripple in volts. ηPFC PFC operating efficiency. IO(MAX) Maximum output current in amps. appropriately increased to account for ageing and tolerances. should be placed directly at the IC on the circuit board. will affect the maximum power delivered by the part. be placed directly at the IC on the circuit board. the HiperPFS-2 does not have a separate pin for compensation. voltage resulting from transient loads. values are shown in Figure 15. Figure 15. Recommended Feedback Circuit.

injection can lead to waveform instability or dissymmetry. located away from the drain node of the, or the PFC inductor. Figure 19. PCB Layout Example for System Power Supply Consisting of a PFC and a Second Stage Converter. the switching frequency current loop thereby reducing EMI. traversing through the loop.

Rev. B 06/13 PFS7323-7329 www.powerint.com During placement of components on the board, it is best to place the VOLTAGE MONITOR pin, FEEDBACK pin and VCC pin decoupling capacitors close to the HiperPFS-2 before the other components are placed and routed. Power supply return trace from the GROUND pin should be separate from the trace connecting the feedback circuit components to the GROUND pin. To minimize effect of trace impedance affecting regulation, output feedback should be taken directly from the output capacitor positive terminal. The upper end of the line-sense resistors should be connected to the high frequency filter capacitor connected at the output of the bridge rectifier. Quick Design Checklist As with any power supply design, all HiperPFS-2 designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – verify that peak VDS does not exceed 530 V at lowest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just above the highest rated load or before the power supply output voltage starts falling out of regulation. Additional external snubbers should be used if this voltage is exceeded. In most designs, addition of a ceramic capacitor in the range of 33 pF and 100 pF connected across the PFC output diode will reduce the maximum drain-source voltage to a level below the BVDSS rating. When measuring drain-source voltage of the MOSFET, a high voltage probe should be used. When the probe tip is removed, a silver ring in the vicinity of the probe tip can be seen. This ring is at ground potential and the best ground connection point for making noise free measurements. Wrapping stiff wire around the ground ring and then connecting that ground wire into the circuit with the shortest possible wire length, and connecting the probe tip to the point being measured, ensures error-free measurement. Probe should be compensated according to probe manufacturers guidelines to ensure error-free measurement. 2. Maximum drain current – Drain current can be measured indirectly by monitoring inductor current. A current probe should be inserted between the bridge rectifier and inductor connection. At maximum ambient temperature, minimum input voltage and maximum output load, verify inductor current waveforms at start-up for any signs of inductor saturation. When performing this measurement with Sendust inductor, it is typical to see inductor waveforms that show exponential increase in current due to permeability drop. This should not be confused with hard saturation. 3. Thermal check – at maximum output power, minimum input voltage and maximum ambient temperature; verify that temperature specifications are not exceeded for the HiperPFS-2, PFC inductor, output diodes and output capacitors. Enough thermal margin should be allowed for the part-to-part variation of the RDS(ON) of HiperPFS-2, as specified in the data sheet. A maximum package temperature of 100 °C under worst-case operating conditions is recommended to allow for these variations. 4. Input PF should improve with load, if performance is found to progressively deteriorate with loading then that is a sign of possible noise pickup by the VOLTAGE MONITOR pin circuit or the feedback divider network and the compensation circuit.

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Control Functions Maximum Operating ON-time tON(MAX) 0 °C < TJI < 100 °C 30 40 50 ms Minimum Operating ON-time tON(MIN) 0 °C < TJI < 100 °C See Note A 0.5 1 Maximum Operating OFF-time tOFF(MAX) 0 °C < TJI < 100 °C 30 40 50 Minimum Operating OFF-time tOFF(MIN) 0 °C < TJI < 100 °C 1 3.5 Internal Feedback Voltage Reference VREF TJI = 25 °C See Note A 5.955 6.00 6.045 V COMPENSATION Pin Voltage VC 0 °C < TJI < 100 °C (In Regulation) 5.88 6.00 6.12 V FEEDBACK Pin Current IFB TJI = 25 °C Normal Operation 340 500 640 nA Soft-Start Time tSOFT TJI = 25 ° 12 ms Internal Compensation Frequency fCOMP See Note A Pole (fp) 1 kHz Error-Amplifier Gain Av See Note A 100 V/V Absolute Maximum Ratings(2) Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. 3. Normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. Limited to a duration ≤ 15 ns and at a drain current ≤ I LIM(TYP) . Thermal Resistance Thermal Resistance: H/L Package: Notes: 1. Controller junction temperature (TJI) may be less than the Internal Power MOSFET Junction Temperature (TJ(M)) and Diode Junction Temperature (TJ(D)). Qspeed Diode Peak Repetitive Reverse Voltage (V RRM) 530 V Average Forward Current (I F(AVG)) TJ(D) = 150 °C 3 A Non-Repetitive Peak Surge Current (I FSM) 60 Hz, ½ cycle, TC(D) = 25 °C 50 A Non-Repetitive Peak Surge Current (I FSM) 500 ms, TC(D) = 25 °C 130 A

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Line-Sense/Peak Detector Brown-In Threshold Current IUV+ 0 °C < TJI < 100 °C 27.50 28.88 mA Brown-Out Threshold Current IUV- 0 °C < TJI < 100 °C 22.52 24.50 mA Brown-In/Out Hysteresis IUV(HYST) 0 °C < TJI < 100 °C 2.5 5.5 mA Soft-Start Brown-Out Threshold Current IUV(SS) TJI = 25 °C 20.62 mA Soft-Start Brown-Out Time-Out tUV(SS) TJI = 25 °C 1000 ms VOLTAGE MONITOR Pin Voltage Threshold VV(THR) 0 °C < TJI < 100 °C IV = IUV+ 1.6 2.3 3.1 V VOLTAGE MONITOR Pin Short-Circuit Current IV(SC) 0 °C < TJI < 100 °C VV = 6 V 280 mA VOLTAGE MONITOR Pin Pre-Soft-Start Current IV(SS) 0 °C < TJI < 100 °C VV = 3 V 5 mA Line Sample Refresh Period tREFRESH TJI = 25 °C 16 60 ms Brown-Out Timer tBROWN-OUT TJI = 25 °C 32 60 ms VOLTAGE MONITOR Pin Shutdown Current Threshold IV(OFF) 0 °C < TJI < 100 °C 200 mA VOLTAGE MONITOR Pin Shutdown Delay tV(OFF) TJI = 25 °C 65 110 135 ms

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection Over-Current Protection IOCP PFS7323L di/dt = 250 mA/ms TJI = 25 °C IV < 48 mA 3.8 4.1 4.3 IV > 59 mA 2.5 2.9 3.2 PFS7324L di/dt = 300 mA/ms TJI = 25 °C IV < 48 mA 4.5 4.8 5.1 IV > 59 mA 3.0 3.5 3.8 PFS7325L di/dt = 400 mA/ms TJI = 25 °C IV < 48 mA 5.5 5.9 6.2 IV > 59 mA 3.7 4.2 4.7 PFS7326H di/dt = 500 mA/ms TJI = 25 °C IV < 48 mA 6.8 7.2 7.5 IV > 59 mA 4.6 5.2 5.7 PFS7327H di/dt = 650 mA/ms TJI = 25 °C IV < 48 mA 8.0 8.4 8.8 IV > 59 mA 5.4 6.0 6.6 PFS7328H di/dt = 800 mA/ms TJI = 25 °C IV < 48 mA 9.0 9.5 9.9 IV > 59 mA 6.0 6.6 7.3 PFS7329H di/dt = 920 mA/ms TJI = 25 °C IV < 48 mA 10.0 10.5 11.0 IV > 59 mA 6.6 7.4 7.9 SOA Protection Time-Out tOCP TJI = 25 °C 265 315 365 ms SOA On-time tSOA TJI = 25 °C See Note A 1 ms Leading Edge Blanking (LEB) Time tLEB See Note A 220 ns Current Limit Delay (ILD) tIL(D) See Note A 100 ns LEB + ILD + Driver Delay tLEB + tIL(D) + tDRIVER TJI = 25 °C 370 470 570 ns Thermal Shutdown Temperature TSHUT See Note A 110 117 125 °C Thermal Shutdown Hysteresis THYST See Note A 49 °C COMPENSATION Pin Undervoltage Threshold CUV TJI = 25 °C 3 3.5 4 V COMPENSATION Pin Undervoltage Delay tC(UV) TJI = 25 °C 65 100 135 ms Feedback Start-Up Threshold FBOFF 0 °C < TJI < 100 °C 1.15 1.25 1.45 V FEEDBACK Pin Off Delay tFB(OFF) 0 °C < TJI < 100 °C 5 ms

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection (cont.) COMPENSATION Pin Start-Up Threshold COFF 0 °C < TJI < 100 °C 0.5 1.2 1.65 V COMPENSATION Pin Off Delay tC(OFF) 0 °C < TJI < 100 °C 5 ms FEEDBACK Pin Overvoltage Threshold FBOV 0 °C < TJI < 100 °C Referenced to VREF VREF +600 mV VREF +700 mV VREF +850 mV V COMPENSATION Pin Overvoltage Threshold COV 0 °C < TJI < 100 °C Referenced to VREF VREF +25 mV VREF +90 mV VREF +160 mV V 0 °C < TJI < 100 °C Hysterisis 50 mV FEEDBACK Pin/ COMPENSATION Pin Overvoltage Delay tFB(OV) tC(OV) 0 °C < TJI < 100 °C 1 2 3 ms FEEDBACK Pin Overvoltage Hysteresis FBOV(HYST) 0 °C < TJI < 100 °C +300 mV V FEEDBACK Pin Overvoltage Offset Threshold FBCOV 0 °C < TJI < 100 °C Referenced to VC (COMPENSATION Pin) VC +225 mV VC +250 mV VC +275 mV V FEEDBACK Pin Undervoltage Offset Threshold FBCUV 0 °C < TJI < 100 °C Referenced to VC (COMPENSATION Pin) VC -275 mV VC -250 mV VC -215 mV V FEEDBACK Pin Charge Current IFBC 0 °C < TJI < 100 °C |VFB-VC| > 215 mV 2 mA Start-Up VCC (Rising Edge) VCC+ TJI = 25 °C 9.5 10.2 V VCC Operating Range VCC TJI = 25 °C, See Note A 10.2 12 13.2 V Shutdown VCC (Falling Edge) VCC- TJI = 25 °C 9.0 9.5 V VCC Hysteresis VCC(HYST) 0 °C < TJI < 100 °C 0.2 0.5 0.8 V Supply Current Characteristics ICD1 0 °C < TJI < 100 °C Switching 3.5 mA ICD2 0 °C < TJI < 100 °C Not Switching 2.5 VCC Power-Up Reset Threshold VCC(POR) TJI = 25 °C 2.85 3.6 4.25 V VCC Power-Up Reset Current IVCC(POR) TJI = 25 °C 2.5 mA REFERENCE Pin Voltage VR 0 °C < TJI < 100 °C RREF = 24.9 kW 1.240 1.265 1.300 V REFERENCE Pin Threshold IR 0 °C < TJI < 100 °C Full Power Mode (24.9 kW) 48.50 51.00 53.50 mA Efficiency Power Mode (49.9 kW) 24.00 25.50 27.00

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection (cont.) REFERENCE Pin Off-State Current Threshold IR(OFF) TJI = 25 °C See Figure 12 Short REFERENCE Pin to G/S 60 mA Open REFERENCE Pin 20 Power Good Power Good Threshold Set Reference Current IPGT 0 °C < TJI < 100 °C 48.5 51.0 53.5 mA Power Good Delay Time tPG TJI = 25 °C 100 ms Power Good Internal Reference Threshold (Start-Up Threshold) VPG(H) 0 °C < TJI < 100 °C Reference to VREF VREF -600 mV VREF -300 mV VREF -0 mV V POWER GOOD Pin Leakage Current in Off-State IPG(OFF) TJI = 25 °C VPGT < VREF – 0.3 V 500 nA Power Good On-State Voltage VPG(ON) TJI = 25 °C IPG = 2 mA 2 V Power Good Comparator Input Offset Voltage VPG(OS) 0 °C < TJI < 100 °C -50 +50 mV Power Good Threshold Operating Voltage VPGT 0 °C < TJI < 100 °C See Note A 0 13.2 V Power Good Operating Voltage VPG 0 °C < TJI < 100 °C See Note A 0 13.2 V Power MOSFET ON-State Resistance RDS(ON) ID = IOCP × 0.5 and IV < 48 mA PFS7323 W PFS7324 PFS7325 PFS7326 PFS7327 PFS7328 PFS7329

Rev. B 06/13 PFS7323-7329 www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Power MOSFET (cont.) Effective Output Capacitance COSS TJ(M) = 25 °C VGS = 0 V, VDS = 0 to 80% VDSS (See Note A) PFS7323 176 pF PFS7324 210 PFS7325 265 PFS7326 312 PFS7327 320 PFS7328 420 PFS7329 487 Breakdown Voltage BVDSS TJ(M) = 25 °C, VCC = 12 V ID = 250 mA, VFB = VV = VC = 0 V 530 V Breakdown Voltage Temperature Coefficient BVDSS(TC) 0.048 %/°C Off-State Drain Current Leakage IDSS TJ(M) = 100 °C VDS = 80% BVDSS VCC = 12 V VFB=VV=VC=0 PFS7323 TJ(M) = 100 °C 80 mA PFS7324 TJ(M) = 100 °C 100 PFS7325 TJ(M) = 100 °C 120 PFS7326 TJ(M) = 100 °C 150 PFS7327 TJ(M) = 100 °C 170 PFS7328 TJ(M) = 100 °C 200 PFS7329 TJ(M) = 100 °C 235 Turn-Off Voltage Rise Time tR See Notes A, B, C ns Turn-On Voltage Fall Time tF 100 Start-Up Time Delay tSTART-DELAY 0 °C < TJI < 100 °C See Note A, B 2 6 10 ms

Rev. B 06/13 PFS7323-7329 www.powerint.com NOTES: A. Not tested parameter. Guaranteed by design. B. Tested in typical Boost PFC application circuit with 22 nF capacitor between VOLTAGE MONITOR and SIGNAL GROUND pins, and 4 MW resistor from rectified line to the VOLTAGE MONITOR pin. C. Normally limited by internal circuitry. Parameter Symbol Conditions SOURCE = 0 V; VCC = 12 V, TJI = -40 °C to 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Qspeed Diode DC Characteristics Reverse Current IR(D) VR = 530 V, TJ(D) = 25 °C 0.4 mA VR = 530 V, TJ(D) = 100 °C 0.07 mA Forward Voltage VF IF = 3 A, TJ(D) = 25 °C 1.55 V IF = 3 A, Junction Capacitance CJ VR = 10 V, 1 MHz 18 pF Dynamic Characteristics Reverse Recovery Time tRR di/dt = 200 A/ms, VR = 400 V IF = 3 A TJ(D) = 25 °C 25 ns TJ(D) = 100 °C 31 Reverse Recovery Charge QRR di/dt = 200 A/ms, VR = 400 V IF = 3 A TJ(D) = 25 °C 33.5 nC TJ(D) = 100 °C 57 Maximum Reverse Recovery Current IRRM di/dt = 200 A/ms, VR = 400 V IF = 3 A TJ(D) = 25 °C 1.9 A TJ(D) = 100 °C 2.5 Softness Factor = tB/tA S di/dt = 200 A/ms, VR = 400 V IF = 3 A TJ(D) = 25 °C 1

0 PFS7323 PFS7324 PFS7325 PFS7326 PFS7327 PFS7328 PFS7329

Thermal Resistance of Internal Qspeed Diode is = 5.2 °C/W for all devices. Thermal Resistance of Internal Power MOSFET shown below. Figure 20. Thermal Resistance (qJC ).

Rev. B 06/13 PFS7323-7329 www.powerint.com PI-6972-022713 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.038 (0.97) 0.076 (1.93) 0.118 (3.00)

0.029 Dia Hole

0.062 Dia Pad

0.020 (0.50) 0.016 (0.41) Ref. Detail A 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.290 (7.37) Ref. 0.047 (1.19) C 1 3 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.076 (1.93) 0.012 (0.30) Ref. 0.207 (5.26) 0.187 (4.75) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.519 (13.18) Ref. FRONT VIEW SIDE VIEW BACK VIEW PCB FOOT PRINT END VIEW eSIP-16D (H Package) Dimensions in inches, (mm). All dimensions are for reference. 0.524 (13.31) Ref. 0.208 (5.27) Ref.

Rev. B 06/13 PFS7323-7329 www.powerint.com PI-6791-022713 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). 0.038 (0.97) 0.076 (1.93) 0.094 (2.40) FRONT VIEW SIDE VIEW BACK VIEW PCB FOOT PRINT END VIEW eSIP-16G (L Package) 0.628 (15.95) Ref. 0.019 (0.48) Ref. 0.060 (1.52) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) Dimensions in inches, (mm). All dimensions are for reference. 0.653 (16.59) 0.647 (16.43) 0.325 (8.25) 0.320 (8.13) A B Pin 1 I.D. 0.038 (0.97) Typ. 9 Places 0.056 (1.42) Ref. 468101316 5791114 C 0.128 (3.26) 0.122 (3.10) 0.081 (2.06) 0.077 (1.96) Detail A 0.094 (2.40) 0.047 (1.19) Ref. 0.050 (1.26) Ref. 0.144 (3.66) Ref. 0.290 (7.37) Ref. 13×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.076 (1.93) Typ. 3 Pieces 0.173 (4.39) 0.163 (4.14) 0.079 (1.99) 0.069 (1.74) 13×0.024 (0.61) 0.019 (0.48) 0.010 M 0.25 M C A B 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) R0.012 (0.30) Typ., Ref. 0.524 (13.31) Ref. 0.208 (5.27) Ref.

Rev. B 06/13 PFS7323-7329 www.powerint.com Part Marking Information

• HiperPFS-2 Product Family
• PFS-2 Series Number
• Package Identifier L Plastic eSIP , L Bend H Plastic eSIP Part Ordering Information Part Number Option Quantity PFS7323L Tube 30 PFS7324L Tube 30 PFS7325L Tube 30 PFS7326H Tube 30 PFS7327H Tube 30 PFS7328H Tube 30 PFS7329H Tube 30 PFS 7323 L

A Initial Release. 06/03/13 B Updated tBROWN-OUT. Updated Minimum IOCP for PFS7329H. 06/10/13 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2013, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters

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