Power Management

PF5300

NXP Semiconductors

12 A / 8 A / 15 A core supply regulators with AVP and watchdog Rev. 2 - 5 June 2023

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12 A / 8 A / 15 A core supply regulators with AVP and watchdog

Document overview

Manufacturer or author: NXP B.V.
PDF pages: 175

Technical content

Datasheet sections

12 A / 8 A / 15 A core supply regulators with AVP and watchdog
1 Overview
2 Features
3 Simplified application diagram
4 Ordering information
5 Applications
6 Internal block diagram
7 Pinning information
7.1 Pinout
7.2 Pin descriptions
8 Absolute maximum ratings
9 Characteristics
9.1 ESD ratings
9.2 Thermal characteristics
9.3 Recommended operating conditions
10 General description
10.1 Functional block diagram
11 State machine
11.1 State descriptions
11.1.1 ULP_Off state
11.1.2 Load fuses
11.1.3 LP_Off state
11.1.4 Self-test routine (PF5300 ASIL B and ASIL
11.1.4.1 ABIST test on all voltage monitors
11.1.5 Power-up sequence
11.1.6 IO_Release state
11.1.7 INIT state
11.1.8 System ON state
11.1.9 Power-down state
11.1.10 Fail-safe state
12 General device operation
12.1 UVDET
12.2 VIN OVLO condition
12.3 Power up
12.3.1 Power-up events
12.3.2 Power-up sequencing
12.4 Power down
12.4.1 Turn-off events
12.4.2 Power-down sequencing
12.5 Fault management
12.6 Interrupt management
12.7 I/O interface pins
12.7.1 PWRON
12.7.2 STANDBY/SYNCIN
12.7.3 PGOOD
12.7.4 XFAILB
12.7.5 SDA and SCL (I²C bus)
12.7.5.1 I²C CRC verification
12.7.5.2 I²C secure write
13 Functional blocks
13.1 SW1: DC-DC regulator
13.1.1 SW1 architecture
13.1.2 SW1 output voltage selection
13.1.3 SW1 adaptive-voltage positioning (AVP)
13.1.4 Calculating output accuracy with AVP
13.1.4.1 Accuracy of the current sense circuit and
13.1.4.2 Calculating total output voltage tolerance
13.1.5 Compensating the SW1 loop
13.1.5.1 SW1 PLL
13.1.5.2 SW1 TON dominant operation
13.1.5.3 SW1 GM, RCOMP, and CCOMP
13.1.5.4 OTP_SW1_AVP_FILT[1:0] and OTP_SW1_
13.1.6 SW1 operation mode selection
13.1.7 SW1 soft-start and DVS selection
13.2 Voltage monitoring
13.3 ABIST verification
13.4 Clock management
13.4.1 Low-frequency clock
13.4.2 High-frequency clock and SW1 switching
13.4.3 Manual frequency tuning
13.4.4 Spread spectrum
13.4.5 Clock synchronization
13.5 Thermal monitoring
13.6 Watchdog timer
13.6.1 Simple watchdog (OTP_WD_SEL = 0)
13.6.2 Challenger watchdog (OTP_WD_SEL = 1)
14 I²C register map
14.1 PF5300 OTP mirror register map
14.1.1 OTP address 0x2A
14.1.2 OTP address 0x2B
14.1.3 OTP address 0x2C
14.1.4 OTP address 0x2D
14.1.5 OTP address 0x2E
14.1.6 OTP address 0x2F
14.1.7 OTP address 0x20
14.1.8 OTP address 0x21
14.1.9 OTP address 0x22
14.1.10 OTP address 0x23
14.1.11 OTP address 0x24
14.1.12 OTP address 0x25
14.1.13 OTP address 0x26
14.1.14 OTP address 0x27
14.1.15 OTP address 0x28
14.1.16 OTP address 0x29
14.1.17 OTP address 0x30
14.1.18 OTP address 0x31
14.1.19 OTP address 0x32
14.1.20 OTP address 0x33
14.1.21 OTP address 0x34
14.1.22 OTP address 0x35
14.1.23 OTP address 0x36
14.1.24 OTP address 0x37
14.2 PF5300 functional register map
14.2.1 DEVICE_ID register
14.2.2 REV register
14.2.3 CONFIG1 register
14.2.4 INT_STATUS1 register

PF5300; PF5301; PF5302

12 A / 8 A / 15 A core supply regulators with AVP and watchdog

Rev. 7.0 — 27 July 2026 Product data sheet

1 Overview

The PF5300, PF5301, and PF5302 integrate high-performance buck converters, 12 A, 8 A, and 15 A, respectively, to power high-end automotive and industrial processors. With adaptive-voltage positioning and a high-bandwidth loop, they offer transient regulation to minimize capacitor requirements. Clock synchronization and spread-spectrum features reduce EMC issues in the system. The PF5300/PF5301/ PF5302 can operate as standalone point-of-load regulator ICs or as companion chips to a larger PMIC. Built-in one-time programmable (OTP) memory stores key startup configurations, drastically reducing external components. Regulator parameters are adjustable through high-speed I2C after startup, offering flexibility for different system states. PF5300/PF5301/PF5302 have been developed to comply with the ISO 26262 automotive safety specification. They include configurable feature sets to fit in or support applications with safety levels up to ASIL D. To simplify, PF5300 is used in this document to refer to PF5300, PF5301, and PF5302. Unless explicitly mentioned, references to PF5300 include PF5301 and PF5302.

NXP Semiconductors PF5300; PF5301; PF5302

2 Features

The PF5300/PF5301/PF5302 integrate a high-performance 12 A / 8 A /15 A buck converter to power high-end automotive and industrial processors.

High-performance core buck regulator – 12 A, 5 VIN buck regulator - internal FETs (PF5300) – 8 A, 5 VIN buck regulator - internal FETs (PF5301) – 15 A, 5 VIN buck regulator - internal FETs (PF5302) – 2.7 V to 5.5 V input range – 0.5 V to 1.2 V output range – High efficiency – ±1 % output accuracy – 2 MHz to 3 MHz switching frequency – Dynamic voltage scaling – Programmable adaptive-voltage positioning (AVP) (droop)
1.5 μA quiescent current in OFF mode
PFM mode in STBY for PF530xB version
Fast startup time (< 500 µs)
OTP memory for device configuration
Overtemperature protection
Safety features – Available in ASIL D, ASIL B, and QM variations – Watchdog timer – 1 % OV/UV monitoring – PGOOD output – Analog built-in self-test
Automotive AEC-Q100 qualified and extended industrial versions available
Rated from -40 ℃ to 150 ℃ Tj
3.5 mm x 4.5 mm WF-QFN package PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

3 Simplified application diagram

4 Ordering information

Table 1. Ordering information...continued [1] PF530xB version is recommended for new designs. [2] To order parts in tape and reel, add the R2 suffix to the part number. [4] Recommended for new designs. NXP’s latest graphical user interface and socketed evaluation board. third party are allowed to program the device for production purposes. Table 2. Feature comparison PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302

5 Applications

Automotive – infotainment, gateway, domain controllers
High-end consumer and industrial PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

6 Internal block diagram

20 MHz

20 MHz clock

100 MHz

7 Pinning information

7.1 Pinout

Figure 3. PF5300 pinout (bottom view)

7.2 Pin descriptions

distance between corresponding PGND pins.

7 STANDBY/

12 FB+

PCB to reduce differential noise.

13 VDDOTP/

8 Absolute maximum ratings

Table 4. Absolute maximum ratings reliability impact, system must not operate above 6.0 V for more than 1800 seconds over the lifetime of the device. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

9 Characteristics

9.1 ESD ratings

All ESD specifications are compliant with AEC-Q100 specification. Table 5. ESD ratings

9.2 Thermal characteristics

Table 6. Thermal characteristics Table 7. QFN24 thermal resistance and package dissipation ratings [1] Thermal test board meets JEDEC specification for this package (JESD51-9). application-specific environment. [3] Junction-to-Case thermal resistance determined using an isothermal cold plate. Case is defined as the bottom of the packages (exposed pad). by the customer to optimize thermal design of the system. IcePAK, Flotherm, and 3D PF5300 simulation models are available on NXP.com. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

9.3 Recommended operating conditions

specified at 25 °C, unless otherwise noted. Table 8. Operating Conditions PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

10 General description

10.1 Functional block diagram

11 State machine

Section 11.1 for descriptions of the states.

20 MHz Off

State transitions are indicated by an alphabetic character.

Refer to the state transition table for details. Figure 5. State machine diagram PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302

11.1 State descriptions

11.1.1 ULP_Off state

The ULP_Off state is an Ultra-low Power-off mode with very low quiescent current. When VIN is applied, the device moves to this state and waits for a power-on event. In this state, the internal bias circuits are off to maintain the low Iq requirement, and only the PWRON detection circuits are enabled. During power down, the ULP_OFF_CTRL bit determines the transition to the ULP_Off state. If power down is because of PWRON going low, if the ULP_OFF_CTRL = 0, the state machine moves to LP_Off directly. If ULP_OFF_CTRL = 1, the state machine transitions to the ULP_Off state, where the internal regulators are off to reduce the supply current consumption. While powering off into the ULP_Off state results in lower quiescent current, powering off into the LP_Off state results in faster power up. The initial value of the ULP_OFF_CTRL bit is loaded from the OTP_ULP_OFF_CTRL bit.

11.1.2 Load fuses

During a power up from the ULP_Off state, the fuses (for trim and OTP) are loaded into the mirror registers and the functional I2C registers. The fuse circuits have a CRC error check routine, which reports and protects against register loading errors on the mirror registers. If a register loading error is detected, the corresponding TRIM_NOK or OTP_NOK flag is set and the device does not power up further.

11.1.3 LP_Off state

The LP_Off state is a Low Power-off mode with current consumption higher than the ULP_Off mode. All the internal circuits are ON in this state, and the device transitions to the power-up sequence state depending on the PWRON pin status. During this state, if PWRON goes high, the device moves to start the power-up sequence as defined in the OTP settings. See Section 15.1 for details on Debug entry while in LP_Off. When ULP_OFF_CTRL = 0, the device enters the LP_Off state from IO_Release, INIT, or System ON states when turned off.

11.1.4 Self-test routine (PF5300 ASIL B and ASIL D only)

When the device transitions from the LP_Off state, it moves into the self-test routine and performs tests to verify the integrity of the internal circuits. During the self-test routine, the following blocks are verified: 1. The high-speed clock circuit operates within a maximum 15 % tolerance. 2. The outputs of both the voltage generation band gap and the monitoring band gap are not more than 120 mV apart from each other. 3. A CRC is performed on the OTP mirror registers to ensure the integrity of the registers before powering up. 4. ABIST of SW1 OV and UV monitors The self-test routine takes about eleven 100 kHz clock cycles (approximately 110 µs). To allow for varying settling times for the internal band gap and clocks, the self-test block is executed up to three times (with 2.0 ms between each test) in case of a failure. If a failure is encountered, the state machine PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 proceeds to the fail-safe state. Failure of 1, 2, or 3 above is considered a self-test failure. Failure of ABIST is not considered a self-test failure.

11.1.4.1 ABIST test on all voltage monitors

The SW1 OV and UV monitors are checked for functional operation during the self-test routine. This check of the voltage monitors is referred to as ABIST in this document. A failure in the ABIST test is not interpreted as a self-test failure; it only sets the corresponding ABIST flag for system information. The processor is responsible for reading the information and deciding whether it can continue with a safe operation. Upon a successful self-test, the state machine proceeds to the power-up sequence state.

11.1.5 Power-up sequence

During the power-up sequence, the PF5300 starts up per OTP programmed power-up sequence/timing. If SW1 has an OV or UV fault at the end of the power-up sequence (if OTP_PGOOD_SW1_OV or OTP_PGOOD_SW1_UV = 1), the PF5300 waits for up to 2 ms to allow the output voltage to settle and continue the boot up after OV and/or UV pass. If OV/UV persists after 2 ms, it is considered a power-up failure. After a power-up failure, the state machine proceeds to the Fail-safe state via Transition Q and increments the fault counter. During the power-up sequence, PGOOD is checked for a stuck at high fault (internally asserted low, but externally high) and Transition Q is taken if PGOOD is stuck high for more than 10 μs. See Table 9 for full The PGOOD pin can also be programmed, as part of the power-up sequence, to allow controls of its release timing. See Section 12.3.2 for details. When PGOOD is internally released high, but externally pulled low, the FAULT_CNT[3:0] is incremented. If it is expected that the PGOOD is externally asserted low while the PF5300 may have released it, set OTP_FAULT_MAX_CNT[2:0] to > 3b'000. This is to ensure that FAULT_CNT does not reach its maximum limit because of a systematic event.

11.1.6 IO_Release state

If the Power Up state is successfully completed, the state machine transitions to the IO_Release state. PGOOD_sns = 1 is a condition to exit the IO_Release state. A 100 ms timer becomes active in the IO_Release state if PGOOD is internally released. This timer is to check whether the PGOOD pin is shorted to ground (internally released, but externally low). If a short to GND is detected for more than 100 ms, device fault shutdown is initiated. The 100 ms timer is disabled in Debug mode. Figure 6 and Figure 7 show some examples of the IO_Release behavior. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

Figure 6. IO_Release state behavior - SW1 and PGOOD release during power-up sequence Figure 7. IO_Release state behavior - SW1 and PGOOD release during power-up sequence - PGOOD held low PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 8. IO_Release state behavior - SW1 up during power-up sequence - PGOOD_SEQ = 0 (software release) Figure 9. IO_Release state behavior - SW1 up during power-up sequence; PGOOD_SEQ = 0 (software release) but

11.1.7 INIT state

this state, the processor is expected to boot up and set up specific registers of the PMIC. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302 The INIT window must be closed within 2 seconds of entering the INIT state with a good watchdog refresh. Expiration of this timer (absence of good watchdog refresh) is considered to be a watchdog event and the state machine will transition to the IO_Release state, assert PGOOD, and increment the fault counter. If the watchdog is disabled, the INIT state is bypassed automatically without waiting for a refresh. Upon state transition, the state machine exits into the System ON state.

11.1.8 System ON state

The System ON state is a virtual state composed of two modes of operations: the RUN state and the STANDBY state. RUN state In this state, regulator-specific registers to control SW1's output voltage, operation mode and/or enable/disable state can be modified. By default, the SW1_VOLT[7:0] registers are loaded with the data stored in the OTP_SW1_VOLT[7:0] register. In the RUN state, SW1 regulates to the voltage set by SW1_VOLT[7:0] register. The user can change the SW1 voltage dynamically by changing the SW1_VOLT[7:0] register value. STANDBY state SW1 regulates the voltage set by SW1_STBY_VOLT[7:0] register. If the STANDBY/SYNCIN pin is configured as STANDBY pin by setting OTP_SYNCIN_EN = 0, the STANDBY pin can be toggled to change SW1’s regulation voltage. This presents a way to dynamically change SW1’s voltage that is faster than using I2C to change SW1_VOLT[7:0] while in the RUN state. OTP_SW1_DVS_MAX[7:0] and OTP_SW1_DVS_MIN[7:0] set the maximum and minimum values of the SW1_VOLT[7:0] and SW1_STBY_VOLT[7:0] registers that are accepted. This is useful to prevent unintended values at the regulator output that may potentially cause harm. If the user attempts to write a value to SW1_VOLT[7:0] or SW1_STBY_VOLT[7:0] beyond the OTP_SW1_DVS_MAX[7:0] and OTP_SW1_DVS_MIN[7:0] values, the PF5300 rejects the write attempt, and the DVS_ERR_I flag is set. Once a STANDBY exit or entry event is recognized and initiated, the STANDBY pin is masked until the transition is complete. OTP_STBY_DLY[5:0] bits can be used to add a delay at the start of the transition when entering or exiting the STANDBY state. The delay value is (OTP_STBY_DELAY[5:0] * SEQ_TBASE[1:0]). If OTP_STBY_DELAY[5:0] = 0x00, no delay is added.

11.1.9 Power-down state

During the Power-down state, SW1 is disabled and PGOOD is asserted low per the configured power-down sequence. The power-down sequence is programmable as defined in Section 12.4.2. Two types of events may lead to the power-down sequence: 1. Non-faulty turn-off events: Depending on the ULP_OFF_CTRL bit, move directly into LP_Off state or ULP_OFF state as soon as the power-down sequence is finalized. 2. Turn-off events because of a PMIC fault: move to the Fail-safe transition as soon as the power-down sequence is finalized.

11.1.10 Fail-safe state

The Fail-safe state is a fault state where the PMIC turns off the regulator and either remains in the Fail-safe state or can be programmed to restart the power-up sequence. The transition to this state is because of any of the following PMIC faults being TRUE: 1. Power-up fault (PU_FAIL) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302

PGOOD sense fault (PG_FAIL) 3. PGOOD short to high 4. FAULT_CNT = FAULT_MAX_CNT (REG_FAIL) 5. Junction temperature > the thermal shutdown threshold (TSD_FAIL) 6. Register CRC error The Fail-safe state provides the following status bits:

PU_FAIL will be set to 1 when the state machine powered down because of a power-up failure.
PG_FAIL will be set to 1 when the state machine powered down because of PGOOD failure.
REG_FAIL will be set to 1 when the state machine powered down because of a regulator failure (fault counter maxed out).
TSD_FAIL will be set to 1 when the state machine powered down because of a thermal shutdown. The xxx_FAIL bits will be reset to 0 when VIN crosses the UVDET threshold. The processor can read the FAIL bits during the System ON states (RUN and STANDBY) or the INIT state, in order to obtain information about the previous failure, provided the state machine is able to power up successfully after such failure. The processor should clear the FAIL bits by writing a 1 to them during the System ON states (RUN and STANDBY) and INIT state, provided the state machine is able to power up successfully after such failure. The Fail-safe state works as a safety transition during a fault or as a lock-down upon a critical device/system failure. Upon entering the Fail-safe state, the OTP_FS_BYPASS bit configures whether the state machine will be able to exit the state back in to the System ON states through LP_Off, or stay in the Fail-safe state. When the OTP_FS_BYPASS bit = 0, the fail-safe bypass feature is disabled, and the state machine will remain in the Fail-safe state indefinitely until a power cycle takes place. When the OTP_FS_BYPASS bit = 1, the fail-safe bypass feature is enabled, and the state machine will be allowed to transition from the Fail-safe state to the LP_Off state, depending on the OTP_FS_BYPASS_CNT bit. The state machine will provide a fail-safe bypass counter configured by OTP_FS_BYPASS_CNT bit to count the number of bypass transitions. The fail-safe bypass counter is incremented every time the transition from the Fail-safe state to the LP_Off state happens. When OTP_FS_BYPASS_CNT bit = 0, the number of transitions allowed will be configured to 15. When OTP_FS_BYPASS_CNT bit = 1, the number of transitions allowed will be infinite. When OTP_FS_BYPASS_CNT bit = 0, and if the fail-safe bypass counter reaches the maximum count value of 15, the state machine will stay in the Fail-safe state. In the Fail-safe state, the SW_1 regulator will be disabled. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

12 General device operation

12.1 UVDET

whereas PVIN falling below PVIN_UVDET_F does not cause a shutdown. specified at 25 °C, unless otherwise noted. Table 10. UVDET thresholds

12.2 VIN OVLO condition

The VIN_OVLO circuit monitors the VIN pin for an overvoltage. VIN_OVLO_EN = 1 enables this monitoring.

When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an VIN_OVLO_I interrupt, but does not turn off the device
When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power-down sequence The default configuration of the VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power up. Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs, or 1.0 ms, by the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by the OTP_VIN_OVLO_DBNC[1:0] bits upon power up. All parameters are specified at Ta = -40 °C to 125 °C, PVIN = VIN = 3.3 V, PWRON = 1.8 V, no load on regulator, Fsw = 2.2 MHz, typical external component values, unless otherwise noted. Typical values are specified at 25 °C, unless otherwise noted. VIN_OVLO_DBNC[1:0] VIN OVLO debounce value (µs) 00 10 01 100 10 1000

11 Reserved

Table 11. VIN_OVLO debounce configuration specified at 25 °C, unless otherwise noted. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 12. VIN_OVLO specifications [1] Operating the device above the maximum VIN = 5.5 V for an extended period of time may degrade and cause permanent damage to the device.

12.3 Power up

12.3.1 Power-up events

proceeds to Power-up based on the conditions listed in Table 9.

12.3.2 Power-up sequencing

the LP_Off to the RUN state. The OTP_SEQ_TBASE[1:0] bits set the default timebase for the power-up and power-down sequencer. Table 13. Power-up timebase register present, the device waits in the IO_Release state for software instructions to turn on SW1 and release PGOOD. sequence. There is a TBASE time between SLOT0 and SLOT1, and so on. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 14. Power-up sequence registers release this bit after turning on any one or all of the regulators. assigned to the PGOOD monitor block.

12.4 Power down

12.4.1 Turn-off events

the PMIC (Hard Fault condition).

Hardware turn off: PWRON pin is pulled low

When bit PMIC_OFF bit is set to 1, the 500 μs shutdown timer is started and the SDWN_I bit is set
If the 500 μs timer expires, the state machine starts a turn off event.
If the SDWN_I bit is cleared before the 500 μs shutdown timer is expired, the shutdown request is cleared and the shutdown event is canceled. The PMIC_OFF bit self-clears if the SDWN_I flag is cleared. 3. XFAILB event 4. VIN goes below VIN_UVDET_F (no power down sequence) For fault conditions resulting in a turn off, see Table 9. The device shuts down immediately (no power-down sequence) when Tj crosses the thermal shutdown threshold rising. After a power-down sequence is started, the PWRON pin is masked until the sequence is finished and transition to the Off/Fail-safe states is completed.

12.4.2 Power-down sequencing

devices in the system, or to allow sufficient time for output capacitors to discharge. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 15. OTP_PD_SEQ_DLY[2:0] configuration PGOOD assertion (low). The delay value is (OTP_TURN_OFF_DELAY[5:0] * OTP_SEQ_TBASE[1:0]). Figure 10. SW1/PGOOD sequence example 1 PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 11. SW1/PGOOD sequence example 2

12.5 Fault management

sequence (after soft-start complete), IO_Release, INIT, and System ON state (RUN and STANDBY) states. OV/UV faults are debounced for a programmable filter time before they are detected as a fault condition. ILIM faults are debounced for 40 μs before they can be detected as a fault condition. using the OTP_FAULT_MAX_CNT[2:0] bits. If the FAULT_MAX_CNT[2:0] is changed during System ON states, the FAULT_CNT[3:0] is reset to 0x00. For each type of fault on SW1, an option is available to increment the FAULT_CNT[3:0] value. Table 16. Fault counter limit configuration PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 16. Fault counter limit configuration...continued off after a FAULT_CNT[3:0] is maxed out, the device moves to the LP_off transition if FS_BYPASS = 1. change during a state change between RUN and STANDBY. Even if a specific fault is bypassed, the corresponding interrupt bit is still set. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20 MHz and

Table 17. Fault types and the corresponding PGOOD pin responses...continued [2] Startup fault. PGOOD is asserted by default as device doesn't progress to Power-up state. Not valid during Debug mode.

12.6 Interrupt management

The interrupt latch XXXX_I: This bit is set when the corresponding interrupt event occurs. It can be read at any time, and is cleared by writing a 1 to the bit.
The sense bit XXXX_S: If available, the sense bit provides the actual status of the signal triggering the interrupt. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

Table 18. Interrupt Registers

12.7 I/O interface pins

Figure 12. Multi-PMIC interface diagram specified at 25 °C, unless otherwise noted. Table 19. I/O Electrical Characteristics PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 19. I/O Electrical Characteristics...continued

12.7.1 PWRON

PWRON is an input signal to the IC that acts as a power-up event signal in the PF5300. PWRON pin is pulled low. Pulling the PWRON pin high is a necessary condition to generate a power-on event. The PWRON pin has a 10 μs debounce timer on the falling edge. automatically with application of VIN.

12.7.2 STANDBY/SYNCIN

STANDBY input (OTP_SYNCIN_EN = 1).

0 STANDBY/SYNCIN pin configured as STANDBY

1 STANDBY/SYNCIN pin configured as Syncin

Table 21. STANDBY pin polarity control

12.7.3 PGOOD

pulled up to 1.8 V, 3.3 V, or VIN with a pullup resistor. state. The PGOOD pin is asserted low in the Fail-safe, ULP_Off, and LP_Off states. path if PVIN is present, but VIN is not. is cleared immediately upon PGOOD assertion (low), PGOOD remains asserted low for 1 ms from there on. a PGOOD stuck at fault is detected, the state machine increments the fault counter FAULT_CNT. PGOOD_S bit can be used to read the real-time status of the pin. the States and State machine for transition conditions. a difference in the thresholds to add "diversity" in the safety path. specified at 25 °C, unless otherwise noted. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 22. PGOOD monitoring electrical parameters

12.7.4 XFAILB

0, the XFAILB feature is disabled. References to XFAILB in the document assume that OTP_XFAILB_EN = 1. power-up sequence across multiple devices. See Table 9 for transition conditions involving XFAILB. is asserted low internally, and the device starts a power-down sequence. See Table 9 conditions. Figure 13. XFAILB during power up PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 14. XFAILB during power down

12.7.5 SDA and SCL (I²C bus)

operation up to the fast mode. To use the High-speed Operation mode, a suitable pullup resistor must be used in the range of 500 Ω to 1 kΩ. address is set by the OTP_I2C_ADD[2:0]. Table 23. I2C address configuration provide an ACK bit to the MCU. 1.1 V because of noise in the bus. To prevent a wrong I2C configuration, various protective mechanisms are implemented. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

12.7.5.1 I²C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I2C transaction.

When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.
When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled. After each I2C transaction, the device calculates the corresponding CRC byte to ensure the configuration command has not been corrupted. When a CRC fault is detected, the PF5300 ignores the erroneous configuration command and sets the CRC_I bit. The PF5300 implements a CRC-8-SAE, per the SAE J1850 specification.
Polynomial = 0x1D
Initial value = 0xFF aaa-048815 MSB Data 6 5 4 1 03 I2C CRS Polynominal Seed: 1 1 1 1 1 1 1 1

Figure 15. 8 bit SAE J1850 CRC polynomial

12.7.5.2 I²C secure write

A secure write mechanism is implemented for specific registers critical to the functional safety of the device.

When OTP_I2C_SECURE_EN = 0, the secure write is disabled.
When OTP_I2C_SECURE_EN = 1, the secure write is enabled. When the secure write is enabled, a specific sequence must be followed in order to grant writing access on the corresponding secure register. The secure write sequence is as follows:
Processor sends command to modify the secure registers
PMIC generates a random code in the RANDOM_GEN register
Processor reads the random code from the RANDOM_GEN register and writes it back on the RANDOM_CHK register The PMIC compares the RANDOM_CHK against the RANDOM_GEN register:
If RANDOM_CHK [7:0] = RANDOM_GEN[7:0], the device applies the configuration on the corresponding secure register and self-clears both the RANDOM_GEN and RANDOM_CHK registers.
If RANDOM_CHK[7:0] is different from RANDOM_GEN[7:0], the device ignores the configuration command and self-clears both the RANDOM_GEN and RANDOM_CHK registers. In the event the processor sends any other command instead of providing a value for the RANDOM_CHK register, the state machine cancels the ongoing secure write transaction and performs the new I2C command. In the event the processor does not provide a value for the RANDOM_CHK register, the I2C transaction will time out 10 ms after the RANDOM_GEN code is generated, and the device is then ready for a new transaction. The following bits are protected by secure write if enabled: AB_RUN, VIN_OVLO_EN, VIN_OVLO_SDWN, FAULT_MAX_CNT, WD_EN, WD_STBY_EN, WD_ERROR_CNT, WD_DURATION, WD_MAX_ERROR, FLT_CNT_CLR, SW1_VOLT, SW1_STBY_VOLT, PGOOD_RLS, ULP_OFF_CTRL, TMP_MON_EN, PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 TMP_MON_AON, SW1_RUN_MODE, SW1_STBY_MODE, SW1_DVS, SW1_FLT_REN, SW1_ILIM_BYPASS, SW1_OV_BYPASS, SW1_UV_BYPASS. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

13 Functional blocks

13.1 SW1: DC-DC regulator

large number of programmable options to optimize the regulator for a wide range of applications. can maintain an AC tolerance of < 2 % for a 7.5 A load step.

13.1.1 SW1 architecture

Figure 16. SW1 DC-DC Architecture response (from a fast TON controller) and fixed frequency operation at steady state.

13.1.2 SW1 output voltage selection

fly by changing SW1_VOLT[7:0] in the I2C space. SW1_VOLT[7:0]’s initial value is loaded from OTP. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 24. SW1 voltage selection (Also applicable to SW1_STBY_VOLT[7:0]) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 24. SW1 voltage selection (Also applicable to SW1_STBY_VOLT[7:0])...continued

13.1.3 SW1 adaptive-voltage positioning (AVP)

resulting in a reduced output capacitor requirement. Figure 17. Adaptive-voltage positioning illustration Table 25. AVP settings PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 25. AVP settings...continued

13.1.4 Calculating output accuracy with AVP

13.1.4.1 Accuracy of the current sense circuit and the AVP loop

The current sense circuit and the AVP loop in the PF5300 have an accuracy shown in Table 26. specified at 25 °C, unless otherwise noted. Table 26. SW1 Current Sense and AVP Accuracy

13.1.4.2 Calculating total output voltage tolerance with AVP

regulation voltage, and the curve formed by points F and G give the minimum regulation voltage. This section describes the procedure to calculate this spread for a given set of operating conditions. Figure 18. Vout tolerance calculation Using the minimum and maximum ripple currents, we can calculate the minimum and maximum sensed current. These need to be calculated at 0 A and the maximum load current in the system (assumed to be X amperes). current sense circuit is ± 7 %. The maximum offset of the current sense circuit is ± 1.62 A. offset in the output voltage. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302 Now, the AVP gain works only for positive currents. Therefore, there is no AVP injection when the sensed current is lower than 0 A. This information allows us to plot the different points on the curves shown in Figure 18. Point A: Point B: Point C: Point D: Point E: Point F: Where, is the nominal output voltage as set using the SW1_VOLT[7:0]/ SW1_STBY_VOLT[7:0] register. is the minimum AVP for the chosen setting as given in Table 26. is the maximum AVP for the chosen setting as given in Table 26. For example, for an output voltage of 0.76 V set using the SW1_VOLT[7:0] register and a nominal AVP of 1.5 mV/A set using the OTP_SW1_AVP[3:0] register: = 0.76 V = 1.425 mV/A = 1.575 mV/A

13.1.5 Compensating the SW1 loop

There are a number of programmable options in the SW1 regulator that can be used to adjust the loop performance. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

13.1.5.1 SW1 PLL

OTP_SW1_PLL_EN = 0, the steady state switching frequency will increase as the load current is increased.

13.1.5.2 SW1 TON dominant operation

performance benefit in disabling this feature. Figure 19. TON extension for faster response

13.1.5.3 SW1 GM, RCOMP, and CCOMP

amplifier gain and the RC filter at the output of the error amplifier as shown in Table 27, Table 28, and Table 29. model considering all the parameters. Table 27. OTP_SW1_GM[3:0] selection PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 27. OTP_SW1_GM[3:0] selection...continued Table 28. OTP_SW1_ RCOMP[3:0] selection Table 29. OTP_SW1_ COMP_C[3:0] selection PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 29. OTP_SW1_ COMP_C[3:0] selection...continued

13.1.5.4 OTP_SW1_AVP_FILT[1:0] and OTP_SW1_LSEL[1:0]

OTP_SW1_AVP_FILT[1:0] controls the speed of response of the AVP loop. Set it to 0b11. OTP_SW1_LSEL[1:0] should be set to 0x00.

13.1.6 SW1 operation mode selection

Table 30. SW1 Mode Selection command for the new mode to take effect. Table 31. VMON OV/UV settings

13.1.7 SW1 soft-start and DVS selection

in the I2C space, which can be changed to control the ramp rate for on-the-fly changes on SW1 output voltage. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 32. SW1 slew rate selection

Change the mode back to PFM

relies on the external load and/or the internal RDIS discharge resistor. specified at 25 °C, unless otherwise noted.

PFM mode
0.5 V ≤ VSWxFB ≤ 1.2 V
Load 0 A to 200 mA
AVP = 0 mΩ Acc_PFM -3 — 3 %

Table 33. SW1 electrical parameters...continued

13.2 Voltage monitoring

The PF5300 provides OV and UV monitoring capability for the SW1 regulator. behavior taken into account, to avoid false tripping of the monitor. the debounce time on the undervoltage monitor. MHz. The value will vary depending on the CLK_FREQ[3:0] settings being selected. faults. The interrupts are for notification only and do not directly take an action to enable/disable the regulator. Enabling/disabling of the regulators under fault conditions is handled by the state machine. Table 34. SW1 UV threshold selection PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 34. SW1 UV threshold selection...continued Table 35. SW1 OV threshold selection PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 35. SW1 OV threshold selection...continued Table 36. SW1 UV monitor debounce selection Table 37. SW1 OV monitor debounce selection

13.3 ABIST verification

monitors during the self-test routine and on-demand ABIST (AB_RUN) sequence. AB_SW1_OV = 1 indicates that the VMON's overvoltage monitor is not operating correctly. AB_SW1_UV = 1 indicates that the VMON's undervoltage monitor is not operating correctly. AB_SW1_OV and AB_SW1_UV bits are overwritten every time the ABIST check is performed. A bit AB_RUN is provided to perform ABIST on demand, which is available in the RUN state. When the AB_RUN bit is set to 1, the control logic performs an ABIST verification on the voltage monitors. When the ABIST verification is finished, the AB_RUN bit self-clears to 0. write to be cleared if this feature is enabled. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302 When the PF5300 performs an ABIST verification on demand, the OV/UV fault monitoring is blanked for a maximum period of 200 µs. During this time, the system must ensure it is in a safe state, or it is safe to perform this action without violating the safety goals of the system. If a failure on the OV/UV monitor is detected during the ABIST on-demand request, the PMIC will assert the corresponding ABIST flags. It is the responsibility of the system to perform a diagnostic check after each ABIST verification and take action at the system level.

13.4 Clock management

Clock management provides a top-level management control scheme of internal clock and external synchronization, intended to be primarily used for the switching regulators. Clock management incorporates various subblocks:

Low power 100 kHz clock
Internal high-frequency clock with programmable frequency
Phase-locked loop (PLL) A digital clock management interface is in charge of supporting interaction among these blocks. Clock management provides clocking signals for the internal state machine, the switching frequencies for the buck converters, as well as the multiples of those switching frequencies in order to enable phase shifting for multiple-phase operation.

13.4.1 Low-frequency clock

A low-power 100 kHz clock is provided for overall logic and digital control. Internal logic and debounce timers are based on this 100 kHz clock.

13.4.2 High-frequency clock and SW1 switching frequency

The PF5300 features a high frequency clock with nominal frequency of 20 MHz. Clock frequency is programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits. The initial value of CLK_FREQ[3:0] is loaded from the OTP_CLK_FREQ[3:0] bits. SW1 uses the high-frequency clock divided by 8 as its frequency. For example, when CLK_FREQ[3:0] = 0b0000, the high-frequency oscillator runs at 20 MHz and SW1 runs at 2.5 MHz. Since SW1 is a constant on-time regulator with the outer loop PLL that modulates the TON to maintain the switching frequency, the resulting SW1 frequency will be maintained only under steady state load conditions. Under transient load conditions, the switching frequency will vary (since the switcher PLL is much lower than the DC-DC bandwidth) as the switcher loop responds to the transient load. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302

13.4.3 Manual frequency tuning

PF5300 provides manual frequency tuning of the high-speed oscillator to modulate the switching frequency. The CLK_FREQ [3:0] bits select manual frequency tuning of the high-speed oscillator from 18 MHz to 22 MHz. If a frequency change of two or more steps is requested by a single I2C command, the device performs a gradual frequency change, passing through all steps in between. Manual tuning is not supported when frequency spread spectrum or external clock synchronization are used. CLK_FREQ[3:0] High-speed clock frequency (MHz) 0000 20 0001 21 0010 22

0011 Not used

0100 Not used

0101 Not used

0110 Not used

0111 Not used

1000 Not used

1001 Not used

1010 Not used

1101 Not used

1110 Not used

1111 Not used

Table 38. Manual frequency tuning configuration

13.4.4 Spread spectrum

wide spread to help manage EMC in sensitive applications.

When the FSS_EN = 1, the frequency spread-spectrum is enabled.
When the FSS_EN = 0, the frequency spread-spectrum is disabled. The default state of the FSS_EN bit upon a power up can be configured via the OTP_FSS_EN bit. The OTP_FSS_SEL bit is used to select the spread spectrum type. OTP_FSS_SEL FSS_SEL

Description

0 Triangular modulation

1 Pseudo-random modulation

Table 39. Spread spectrum configuration deviation of ±10 % with a step of 0.5 % around the CLK_FREQ frequency setting. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

When the external clock synchronization is enabled, spread-spectrum is to be disabled. Figure 20. Triangular spread-spectrum modulation to -10 %, through three random steps in between, and 0 % to +10 % through three random steps in between. clock synchronization at all times. Figure 21. Pseudo-random spread-spectrum modulation

13.4.5 Clock synchronization

OTP_FSYNC_RANGE = 1 the input frequency range at SYNCIN pin is valid between 333 kHz and 500 kHz. When used as a SYNCIN input, it is not possible to enter the STANDBY state in the PF5300. external clock. FSYNC_I is set when switching from internal to external or external to internal clock sources. used. FSYNC_S = 0 indicates that the internal clock is being used. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

maintained low until the external clock is applied. SYNC pin outside the range defined by the FSYNC_RANGE bit is detected as invalid. Table 40. Clock management specifications

13.5 Thermal monitoring

Figure 22. Thermal monitoring architecture Table 41. Thermal monitor specifications As the temperature crosses the thermal thresholds, the corresponding interrupts are set to notify the system. shutdown until the 15 ºC thermal shutdown hysteresis is crossed as the device cools down. The temperature monitor can be enabled or disabled via I2C with the TMP_MON_EN bit. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

When TMP_MON_EN = 0, the temperature monitor circuit is disabled.
When TMP_MON_EN = 1, the temperature monitor circuit is enabled. Bit or bits Description THERM_110_I, THERM_110_S Interrupt and sense bits for 110 ºC threshold THERM_125_I, THERM_125_S Interrupt and sense bits for 125 ºC threshold THERM_140_I, THERM_140_S Interrupt and sense bits for 140 ºC threshold THERM_155_I, THERM_155_S Interrupt and sense bits for 155 ºC threshold TMP_MON_EN Disables temperature monitoring circuits when cleared

Table 42. Thermal monitor bit description

13.6 Watchdog timer

watchdog is active in STANDBY state, with initial value loaded from OTP_WD_STBY_EN. first refresh in the INIT state, the period of the watchdog is based on WD_DURATION[3:0]. Table 43. Watchdog window duration configuration PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Deassert PGOOD (high) after 8 ms (provided other faults controlling PGOOD do not exist)
Move to INIT (Transition L) to try again
If FAULT_CNT reaches max value, Transition H occurs to power down and enter the Fail-safe state

immediately (without waiting for the period to be completed). new one with updated WD_DURATION[3:0]). A watchdog error counter is provided to keep track of erroneous refreshes of the watchdog. by 1 (floored at 0). An incorrect watchdog refresh (either data and/or temporal) is considered a watchdog error. The WD_ERROR_CNT[3:0] counter is then incremented by 2, and the next period started. WD_MAX_ERROR[1:0] is loaded from OTP_ WD_MAX_ERROR[1:0]. Table 44. Watchdog error count configuration

If FAULT_CNT >= FAULT_MAX_CNT, proceed via Transition Z
If FAULT_CNT < FAULT_MAX_CNT:

Figure 23. Watchdog timer and error counter

13.6.1 Simple watchdog (OTP_WD_SEL = 0)

0x5B to the WD_ANSWER register within the correct window duration.

13.6.2 Challenger watchdog (OTP_WD_SEL = 1)

NXP Semiconductors PF5300; PF5301; PF5302

14 I²C register map

The PF5300 provides a complete set of registers for control and diagnostics of the PMIC operation. The configuration of the device is done at two different levels. At the first level, the OTP mirror registers provide the default hardware and software configuration for the PMIC upon power up. At the second level, the PF5300 provides a set of functional registers intended for system configuration and diagnostics during the system operation. These registers are accessible after power up and can be modified at any time by the system control unit. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

14.1 PF5300 OTP mirror register map

monitoring using continuous CRC. The mirror registers can be read and written by the user when in Debug mode.

22 OTP_SW1_RDIS — — OTP_XFAILB_EN OTP_VIN_

24 OTP_SYNCIN_EN OTP_SW1_PLL_EN OTP_FSYNC_

26 OTP_WD_DURATION[3:0] OTP_WD_EN OTP_WD_

28 OTP_PGOOD_SEQ[5:0] OTP_SEQ_TBASE[1:0]

29 OTP_SW1_SEQ[5:0] OTP_SW1_SS[1:0]

30 RESERVED — OTP_SW1_

32 OTP_STBY_DELAY[5:0] RESERVED OTP_ULP_

33 OTP_TURN_OFF_DELAY[5:0] OTP_FS_

34 OTP_VMON_UV[3:0] OTP_VMON_OV[3:0]

37 OTP_PROG_ID1[7:0]

38 OTP_S2_CRC_LSB[7:0]

39 OTP_S2_CRC_MSB[7:0]

Table 45. PF5300 OTP map...continued

14.1.1 OTP address 0x2A

Table 46. OTP address 0x2A bit allocation Maximum SW1 voltage setting allowed. Table 47. OTP address 0x2A bit description

14.1.2 OTP address 0x2B

Minimum SW1 voltage setting allowed. Table 49. OTP address 0x2B bit description

14.1.3 OTP address 0x2C

Table 50. OTP address 0x2C bit allocation Table 51. OTP address 0x2C bit description

14.1.4 OTP address 0x2D

Table 53. OTP address 0x2D bit description

14.1.5 OTP address 0x2E

Table 54. OTP address 0x2E bit allocation Error amplifier transconductance setting. Table 55. OTP address 0x2E bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.1.6 OTP address 0x2F

Table 56. OTP address 0x2F bit allocation Table 57. OTP address 0x2F bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.1.7 OTP address 0x20

Table 58. OTP address 0x20 bit allocation

4 OTP_I2C_SECURE_EN

3 OTP_I2C_CRC_EN

14.1.8 OTP address 0x21

Table 60. OTP address 0x21 bit allocation

2 OTP_STANDBYINV

Table 61. OTP address 0x21 bit description

14.1.9 OTP address 0x22

7 OTP_SW1_RDIS

4 OTP_XFAILB_EN

3 OTP_VIN_OVLO_SDWN

2 OTP_VIN_OVLO_EN

14.1.10 OTP address 0x23

Table 64. OTP address 0x23 bit allocation Table 65. OTP address 0x23 bit description

14.1.11 OTP address 0x24

6 OTP_SYNCIN_EN

5 OTP_SW1_PLL_EN

4 OTP_FSYNC_RANGE

Table 67. OTP address 0x24 bit description...continued

14.1.12 OTP address 0x25

7 OTP_FSS_EN

5 OTP_FSS_SEL

Extended TON configuration for SW1.

3 OTP_SW1_TON_DOM

14.1.13 OTP address 0x26

Table 70. OTP address 0x26 bit allocation

3 OTP_WD_EN

2 OTP_WD_STBY_EN

1 OTP_WD_SEL

0 OTP_WDWINDOW

Table 71. OTP address 0x26 bit description...continued

14.1.14 OTP address 0x27

Table 72. OTP address 0x27 bit allocation Table 73. OTP address 0x27 bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 73. OTP address 0x27 bit description...continued

14.1.15 OTP address 0x28

Table 74. OTP address 0x28 bit allocation Table 75. OTP address 0x28 bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 75. OTP address 0x28 bit description...continued

14.1.16 OTP address 0x29

Table 76. OTP address 0x29 bit allocation Table 77. OTP address 0x29 bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.1.17 OTP address 0x30

Table 78. OTP address 0x30 bit allocation

2 OTP_SW1_HIZ_OFF

Table 79. OTP address 0x30 bit description

14.1.18 OTP address 0x31

Configures if respective fault increments the fault counter.

4 OTP_SW1_ILIM_BYPASS

2 OTP_SW1_OV_BYPASS

3 OTP_SW1_OV_BYPASS

2b'00 Recommended for PF5300. Table 81. OTP address 0x31 bit description

14.1.19 OTP address 0x32

0 OTP_ULP_OFF_CTRL

Table 83. OTP address 0x32 bit description

14.1.20 OTP address 0x33

Table 84. OTP address 0x33 bit allocation Delay before turning off SW1 and PGOOD assertion.

1 OTP_FS_BYPASS_CNT

0 OTP_FS_BYPASS

Table 85. OTP address 0x33 bit description...continued

14.1.21 OTP address 0x34

Table 86. OTP address 0x34 bit allocation Table 87. OTP address 0x34 bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.1.22 OTP address 0x35

Table 88. OTP address 0x35 bit allocation

6 OTP_PGOOD_BG

5 OTP_PGOOD_SW1_UV

4 OTP_PGOOD_SW1_OV

Table 89. OTP address 0x35 bit description...continued

14.1.23 OTP address 0x36

Table 90. OTP address 0x36 bit allocation Table 91. OTP address 0x36 bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.1.24 OTP address 0x37

Table 92. OTP address 0x37 bit allocation Table 93. OTP address 0x37 bit description

14.2 PF5300 functional register map

Table 94 shows the I2C register map for PF5300. The cells highlighted in yellow are monitoring using continuous CRC. Table 94. PF5300 functional register map PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 94. PF5300 functional register map...continued The following bit types are used in the PF5300 register map.

RWOTP: Read/write bit with default value loaded from OTP
RO: Read-only
RW: Read/write capable
FLGWC: Write 1 to clear flag bit
FLGWC_CLR: Write 1 to clear flag bit with ability to be cleared via external signal
EXTRW: Read/write bit with self-set/reset capability PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

14.2.1 DEVICE_ID register

Table 95. DEVICE_ID register, address 0x00 bit allocation Table 96. DEVICE_ID register bit description

14.2.2 REV register

Table 98. REV register bit description...continued

14.2.3 CONFIG1 register

Debug mode exit timer. Only useful in Debug mode.

4 DBG_TMR

3 PGOOD_RLS

2 ULP_OFF_CTRL

1 TMP_MON_AON

0 TMP_MON_EN

14.2.4 INT_STATUS1 register

Table 101. INT_STATUS1 register, address 0x05 bit allocation

7 SDWN_I

6 BG_ERR_I

5 CRC_I

4 SW1_DVS_DONE

3 SW1_ILIM_I

2 VMON_UV_I

1 VMON_OV_I

0 VIN_OVLO_I

Table 102. INT_STATUS1 register bit description...continued

14.2.5 INT_SENSE1 register

6 BG_ERR_S

3 SW1_ILIM_S

2 VMON_UV_S

1 VMON_OV_S

0 VIN_OVLO_S

14.2.6 INT_STATUS2 register

Table 105. INT_STATUS2 register, address 0x07 bit allocation

7 PGOOD_STUCK_AT_0

6 PGOOD_STUCK_AT_1

5 DVS_ERR_I

4 FSYNC_I

3 THERM_155_I

2 THERM_140_I

1 THERM_125_I

0 THERM_110_I

Table 106. INT_STATUS2 register bit description...continued

14.2.7 EMREV and PROGID registers

Table 108. EMREV register bit description Table 109. PROGID register, address 0x03 bit allocation PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 110. PROGID register bit description...continued

14.2.8 INT_SENSE2 register

Table 111. INT_SENSE2 register, address 0x08 bit allocation

6 PGOOD_S

4 FSYNC_S

3 THERM_155_S

2 THERM_140_S

1 THERM_125_S

0 THERM_110_S

14.2.9 BIST_STAT1 register

Table 113. BIST_STAT1 register bit allocation

7 STEST_NOK

6 OTP_NOK

5 TRIM_NOK

4 REGMAP_CRC_I

2 AB_SW1_UV

1 AB_SW1_OV

0 OSC_ERR

Table 114. BIST_STAT1 register bit description...continued

14.2.10 BIST_CTRL register

0 AB_RUN

Table 116. BIST_CTRL register bit description

14.2.11 STATE register

5 DBG_EXIT

4 IN_DBG_MODE

14.2.12 STATE_CTRL register

Table 119. STATE_CTRL register, address 0x0C bit allocation

7 PMIC_OFF

6 TSD_FAIL

5 REG_FAIL

safe state because of PGOOD stuck at 0 or 1.

4 PG_FAIL

3 PU_FAIL

0 STANDBYINV

Table 120. STATE_CTRL register bit description...continued

14.2.13 SW1_VOLT register

Table 121. SW1_VOLT register, address 0x0D bit allocation Table 122. SW1_VOLT register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.2.14 SW1_STBY_VOLT register

Table 123. SW1_STBY_VOLT register, address 0x0E bit allocation Table 124. SW1_STBY_VOLT register bit description

14.2.15 SW1_CTRL1 register

Table 125. SW1_CTRL1 register bit allocation table Table 126. SW1_CTRL1 register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 126. SW1_CTRL1 register bit description...continued

14.2.16 SW1_CTRL2 register

Table 127. SW1_CTRL2 register, address 0x10 bit allocation

7 SW1_FLT_REN

Not supported. Automatically set to 1 via OTP.

5 SW1_ILIM_STATE

Not supported. Automatically set to 1 via OTP.

4 SW1_UV_STATE

Not supported. Automatically set to 1 via OTP.

3 SW1_OV_STATE

2 SW1_ILIM_BYPASS

1 SW1_UV_BYPASS

0 SW1_OV_BYPASS

Table 128. SW1_CTRL2 register bit description...continued

14.2.17 CLK_CTRL register

6 FSS_SEL

4 FSS_EN

20 MHz oscillator frequency selection

14.2.18 SEQ_CTRL1 register

Table 129. SEQ_CTRL1 register, address 0x12 bit allocation Table 130. SEQ_CTRL1 register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.2.19 SEQ_CTRL2 register

Table 131. SEQ_CTRL2 register, address 0x13 bit allocation Table 132. SEQ_CTRL2 register bit description

14.2.20 RANDOM_CHK register

Table 133. RANDOM_CHK register, address 0x14 bit allocation Table 134. RANDOM_CHK register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.2.21 RANDOM_GEN register

Table 135. RANDOM_GEN register, address 0x15 bit allocation Table 136. RANDOM_GEN register bit description

14.2.22 WD_CTRL1 register

Table 137. WD_CTRL1 register, address 0x16 bit allocation Table 138. WD_CTRL1 register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

1 WD_STBY_EN

0 WD_EN

Table 138. WD_CTRL1 register bit description...continued

14.2.23 WD_SEED register

Table 139. WD_SEED register, address 0x17 bit allocation Table 140. WD_SEED register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

14.2.24 WD_ANSWER register

Table 141. WD_ANSWER register, address 0x18 bit allocation Table 142. WD_ANSWER register bit description

14.2.25 FLT_CNT1 register

Table 143. FLT_CNT1 register, address 0x19 bit allocation Table 144. FLT_CNT1 register bit description PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Table 144. FLT_CNT1 register bit description...continued

14.2.26 FLT_CNT2 register

Table 145. FLT_CNT2 register, address 0x1A bit allocation

7 FLT_CNT_CLR

4 VIN_OVLO_SDWN

3 VIN_OVLO_EN

NXP Semiconductors PF5300; PF5301; PF5302

15 OTP programming Debug mode

The PF5300 supports OTP fuse bank configuration and debug mode through the VDDOTP/XFAILB pin. Debug mode allows the user to modify OTP mirror registers before and after powering up. This facilitates exercising different features of the PF5300 while deciding on the best configuration for a given application. This is especially useful when optimizing the SW1 compensation for the desired transient response. When powered up in Debug mode, the following restrictions are in place:

The PF5300 ignores TRIM_NOK and OTP_NOK flags and proceeds with power up even if they are set.
I2C uses standard communication with no CRC
I2C address is set to 0x28
Secure write is disabled
Watchdog timer set to Infinite period if enabled
100 ms stuck-at-low timer in IO_Releaseis disabled (infinite time for PGOOD release) If the DBG_EXIT bit is set in IO_Release, INIT, RUN or STANDBY states, Debug mode is exited and restrictions arising from debug operation are removed.

15.1 Debug operation

Follow the procedure below to power up the PF5300 in Debug mode. 1. In the ULP_OFF Mode, Connect PWRON > 7.5 V. This signal is used to deactivate the XFAILB pulldown device and move the PF5300 into the LP_Off State. 2. Apply 8 V at VDDOTP pin. This step sets the I2C address to 0x28 and disables I2C CRC (irrespective of OTP setting). 3. Submit I2C keys 0xAB, 0xCD, 0xEF to the TM_ENTRY[7:0] register. 4. Configure mirror registers as needed. Optionally set DBG_TMR = 1. 5. Remove 8 V supply from VDDOTP pin (connect to XFAILB pullup source). 6. Bring PWRON to between 1.4 V and 5 V and clear DBG_TMR = 0 (if set) to exit LP_Off and power up in Debug mode. Steps 1-2 and 5-6 can occur simultaneously to enable using a single high-voltage supply for debug entry. Note: The user can set the DBG_TMR bit to stay in the LP_Off state to allow time for system reconfiguration from Debug-->Normal operation. This is useful if the system has analog switches to isolate XFAILB and VDDOTP nets and the switches need time to change position. The user should clear the DBG_TMR bit as described in Step 6 to exit LP_Off.

15.2 OTP fuse programming

A permanent OTP configuration is possible by burning the OTP fuses. OTP fuse burning is performed in the LP_Off state. Contact an NXP representative for detailed information on OTP fuse programming. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302

16 Functional safety

16.1 System safety strategy

The PF5300 is defined in a context of safety, and provides a set of features to achieve the safety goals in this context. It provides a flexible yet complete safety architecture to comply with safety classifications up to ASIL D, providing full programmability to enable or disable features to address the safety goals. This architecture includes protective mechanisms to avoid unwanted modification on the respective safety features, as required by the system. The following features are considered to be critical for the functional safety strategy:

Internal watchdog timer and watchdog monitor (simple and challenger type)
Output voltage monitoring with dedicated band gap reference
CRC protection for I2C protocol and select I2C, OTP registers
Input voltage monitoring with dedicated band gap reference
Clock monitoring at startup and during normal operation
Analog built-in self-test (ABIST) on voltage monitors Refer to the PF5300 safety manual for complete details of the safety operation. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

17 IC level current and timing specifications

specified at 25 °C, unless otherwise noted. Table 147. Iq and timing specifications PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

18 Typical performance curves

VIN = PVIN = 3.3 V
VOUT = 0.8 V
Switching frequency = 2200 kHz
Hardware: KITPF5300FRDMEVM
Temperature = 25 ℃
Inductor =100 nH HPL505028FR10MRD3P
Output capacitor = 8 x 22 μF

Figure 25. SW1 output ripple (MPF53BDAMMA1ES) ~ 3 mV Figure 26. SW1 load transient response with AVP PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 27. SW1 load transient response without AVP Figure 28. PWM efficiency, Vout = 1.0 V PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 29. PWM efficiency, Vout = 0.9 V Figure 30. PWM efficiency, Vout = 0.8 V PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 31. PWM efficiency, Vout = 0.7 V Figure 32. PFM Mode 3.3 Vin 0.65 Vout PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 33. PFM Mode 5 Vin 0.65 Vout Figure 34. PFM Mode 3.3 Vin 0.80 Vout PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 35. PFM Mode 5 Vin 0.80 Vout Figure 36. SW1 load regulation at different AVP settings PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 37. SW1 current limit entry and exit: Vout drops and recovers smoothly Figure 38. SW1 turn-off with OTP_SW1_RDIS = 1 and OTP_SW1_HIZOFF = 1 PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

19 Schematic and layout guidelines

19.1 Schematic example

Figure 39. Typical application schematic pullup supply, typically the VDIG bus of other PF PMICs in the system. to their two-terminal equivalent. The FB+ and FB- nets can be routed from near the processor to compensate for voltage drop in the PCB. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

19.2 Layout guidelines

shows the top layout of KITPF5300FRDMEVM. Figure 40. KITPF5300FRDMEVM top layout loop between the PVIN-PGND pins and the bypass capacitors must be as short as possible. capacitor is used in KITPF5300FRDMEVM. noise from affecting the VIN rail, which supplies critical internal reference circuits. functionality. The LX node trace should be kept as small as possible. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 41. Boot capacitor placed at the bottom layer path. An optional 10 pF capacitor may be placed close to the pins if desired. The AGND pin must be connected to the ground place using a via as shown in Figure 40. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.1 Automotive package, A

20.1.1 Package outline, A

20.1.2 Soldering, A

Figure 45. Reflow soldering footprint part1 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 46. Reflow soldering footprint part2 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 47. Reflow soldering footprint part3 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 48. Reflow soldering footprint part4 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 49. Reflow soldering footprint part5 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 50. Reflow soldering footprint part6 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.2 Industrial package, A

20.2.1 Package outline, A

Figure 52. Package outline detail E and G of H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.2.2 Soldering, A

Figure 54. Reflow soldering footprint part1 H-FC-PQFN24 (SOT2090-1)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 55. Reflow soldering footprint part2 H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 56. Reflow soldering footprint part3 H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 57. Reflow soldering footprint part4 H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 58. Reflow soldering footprint part5 H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 59. Reflow soldering footprint part6 H-FC-PQFN24 (SOT2090-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.3 Automotive package, B

20.3.1 Package outline, B

20.3.2 Soldering, B

Figure 63. Reflow soldering footprint part1 for HVQFN24 (SOT2090-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 64. Reflow soldering footprint part2 for HVQFN24 (SOT2283-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 65. Reflow soldering footprint part3 for HVQFN24 (SOT2283-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 66. Reflow soldering footprint part4 for HVQFN24 (SOT2283-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 67. Reflow soldering footprint part5 for HVQFN24 (SOT2283-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 68. Reflow soldering footprint part6 for HVQFN24 (SOT2283-1(SC)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.4 Industrial package, B

20.4.1 Package outline, B

Figure 70. Package outline detail E and G of H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

20.4.2 Soldering, B

Figure 72. Reflow soldering footprint part1 H-FC-PQFN24 (SOT2283-1)) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 73. Reflow soldering footprint part2 H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 74. Reflow soldering footprint part3 H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 75. Reflow soldering footprint part4 H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 76. Reflow soldering footprint part5 H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

Figure 77. Reflow soldering footprint part6 H-FC-PQFN24 (SOT2283-1) PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved.

NXP Semiconductors PF5300; PF5301; PF5302 Document ID Release date Description PF5300_PF5301_ PF5302 v. 7.0

27 July 2026 • CIN 202605013I

Product data sheet
Revised Section 2
Revised Table 1
Added Table 2
Revised Table 30
Revised Figure 4
Revised Section 13.1.6
Added Table 31
Revised Section 13.1.7 to add a note
Revised Table 33 to add PFM mode
Revised Table 97
Revised Table 98
Revised Table 122
Removed footnote from Table 33
Revised Table 147
Revised Section 13.1.4.2
Revised title of Figure 28 (was SW1 efficiency, Vout = 1.0 V)
Revised title of Figure 29 (was SW1 efficiency, Vout = 0.9 V)
Revised title of Figure 30 (was SW1 efficiency, Vout = 0.8 V)
Revised title of Figure 31 (was SW1 efficiency, Vout = 0.7 V)
Added Figure 32
Added Figure 33
Added Figure 34
Added Figure 35
Added Section 20.3
Added Section 20.4 PF5300_PF5301_ PF5302 v6

13 November 2025 • CIN 202510025I

Table Ordering information: updated content PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Document ID Release date Description PF5300_PF5301_ PF5302 v5

30 July 2025 • CIN 202506007I

Product data sheet
Changed security level from confidential to public
Features: added information about industrial versions
Ordering information: added OTP programming information, removed table Feature set comparision (formerly Table 2)
Table Ordering information: updated content and format
I2C CRC verification: updated the polynomial to 0x1D
Calculating output accuracy with AVP: updated the first two equations
Removed section SW1 diode emulation (formerly 13.1.5.3) along with its figure and table
Table SW1 electrical parameters: updated maximum peak current limit for PF5301
PF5300 OTP mirror register map: removed bit fields OTP_SW1_ DIODE_EM_TH[3:0] and OTP_SW1_DIODE_EM_EN
OTP address 0x30: removed bit field OTP_SW1_DIODE_EM_TH[3:0]
OTP address 0x32: removed bit field OTP_SW1_DIODE_EM_EN
Table REV register, address 0x01 bit allocation: changed reset value to 0010 0011
Added Table EMREV register, address 0x02 bit allocation
Added Table EMREV register bit description
Added Table PROGID register, address 0x03 bit allocation
Added Table PROGID register bit description
Debug operation: updated procedure
Layout guidelines: added recommendations regarding PVIN/VIN, boot capacitor, and LX trace node
Added Industrial package
Added v2 changes that were inadvertently removed in the v4 release back into revision history
Updated legal information PF5300 v4 20 February 2024 • CIN 202402010I
Ordering information: added statement about OTP emulation and programming
Updated legal information PF5300 v3 29 November 2023 • Table SW1 electrical parameters: Changed Parameter name from "Switching frequency range" to "SW frequency range under steady state"
Table ESD ratings: Updated all "Min" and "Max values."
Voltage monitoring – Added paragraph beginning "… The debounce timer ..." – Added description text beginning "All parameters are specified ..." to Table SW1 UV threshold selection, Table SW1 OV threshold selection, Table SW1 UV monitor debounce selection, and Table SW1 OV monitor debounce selection
Table OTP Address 0x30 bit description: Changed Description of Bit 2 for "1b'0" from "DVS ramp down during power up" to "DVS ramp down during power down"
Updated Table REV register bit description
Updated Package outline and Soldering: Corrected typo in figures from PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Document ID Release date Description PF5300 v2 26 May 2023 Table Ordering information: changed package dimensions for all parts to

Added Soldering
Added disclaimer regarding suitability for use in industrial applications (functional safety) PF5300 v1 27 April 2023 Initial version PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 HTML publications — An HTML version, if available, of this document is provided as a courtesy. Definitive information is contained in the applicable document in PDF format. If there is a discrepancy between the HTML document and the PDF document, the PDF document has priority. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Suitability for use in automotive applications (functional safety) — This NXP product has been qualified for use in automotive applications. It has been developed in accordance with ISO 26262, and has been ASIL classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Suitability for use in industrial applications (functional safety) — This NXP product has been qualified for use in industrial applications. It has been developed in accordance with IEC 61508, and has been SIL-classified accordingly. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Tab. 7. QFN24 thermal resistance and package Tab. 17. Fault types and the corresponding PGOOD Tab. 24. SW1 voltage selection (Also applicable to Tab. 95. DEVICE_ID register, address 0x00 bit Tab. 99. CONFIG1 register, address 0x04 bit Tab. 101. INT_STATUS1 register, address 0x05 bit Tab. 103. INT_SENSE1 register, Address 0x06 bit PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Tab. 105. INT_STATUS2 register, address 0x07 bit Tab. 107. EMREV register, address 0x02 bit Tab. 109. PROGID register, address 0x03 bit Tab. 111. INT_SENSE2 register, address 0x08 bit Tab. 115. BIST_CTRL register, address 0x0A bit Tab. 117. STATE register, address 0x0B bit allocation ..101 Tab. 119. STATE_CTRL register, address 0x0C bit Tab. 121. SW1_VOLT register, address 0x0D bit Tab. 123. SW1_STBY_VOLT register, address 0x0E Tab. 127. SW1_CTRL2 register, address 0x10 bit Tab. 129. SEQ_CTRL1 register, address 0x12 bit Tab. 131. SEQ_CTRL2 register, address 0x13 bit Tab. 133. RANDOM_CHK register, address 0x14 bit Tab. 135. RANDOM_GEN register, address 0x15 bit Tab. 137. WD_CTRL1 register, address 0x16 bit Tab. 139. WD_SEED register, address 0x17 bit Tab. 141. WD_ANSWER register, address 0x18 bit Tab. 143. FLT_CNT1 register, address 0x19 bit Tab. 145. FLT_CNT2 register, address 0x1A bit PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Fig. 6. IO_Release state behavior - SW1 and PGOOD release during power-up Fig. 7. IO_Release state behavior - SW1 and PGOOD release during power-up Fig. 8. IO_Release state behavior - SW1 up during power-up sequence - PGOOD_SEQ Fig. 9. IO_Release state behavior - SW1 up during power-up sequence; PGOOD_SEQ = 0 (software release) but externally Fig. 21. Pseudo-random spread-spectrum Fig. 24. SW1 soft-start (MPF53BDAMMA1ES); 100 Fig. 25. SW1 output ripple (MPF53BDAMMA1ES) ~ Fig. 36. SW1 load regulation at different AVP Fig. 37. SW1 current limit entry and exit: Vout drops Fig. 38. SW1 turn-off with OTP_SW1_RDIS = 1 and Fig. 45. Reflow soldering footprint part1 for Fig. 46. Reflow soldering footprint part2 for Fig. 47. Reflow soldering footprint part3 for Fig. 48. Reflow soldering footprint part4 for Fig. 49. Reflow soldering footprint part5 for Fig. 50. Reflow soldering footprint part6 for Fig. 51. Package outline H-FC-PQFN24 Fig. 52. Package outline detail E and G of H-FC- Fig. 53. Package outline notes H-FC-PQFN24 Fig. 54. Reflow soldering footprint part1 H-FC- Fig. 55. Reflow soldering footprint part2 H-FC- Fig. 56. Reflow soldering footprint part3 H-FC- Fig. 57. Reflow soldering footprint part4 H-FC- Fig. 58. Reflow soldering footprint part5 H-FC- Fig. 59. Reflow soldering footprint part6 H-FC- Fig. 63. Reflow soldering footprint part1 for Fig. 64. Reflow soldering footprint part2 for Fig. 65. Reflow soldering footprint part3 for Fig. 66. Reflow soldering footprint part4 for Fig. 67. Reflow soldering footprint part5 for Fig. 68. Reflow soldering footprint part6 for Fig. 69. Package outline H-FC-PQFN24 Fig. 70. Package outline detail E and G of H-FC- Fig. 71. Package outline notes H-FC-PQFN24 Fig. 72. Reflow soldering footprint part1 H-FC- PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302 Fig. 73. Reflow soldering footprint part2 H-FC- Fig. 74. Reflow soldering footprint part3 H-FC- Fig. 75. Reflow soldering footprint part4 H-FC- Fig. 76. Reflow soldering footprint part5 H-FC- Fig. 77. Reflow soldering footprint part6 H-FC- PF5300_PF5301_PF5302 All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 27 July 2026 Document feedback

NXP Semiconductors PF5300; PF5301; PF5302

17 IC level current and timing

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2026 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 27 July 2026 Document identifier: PF5300_PF5301_PF5302

Selected Specification

NXP Semiconductors PF5300 overview.

Summary

12 A / 8 A / 15 A core supply regulators with AVP and watchdog Rev. 2 - 5 June 2023

Description

12 A / 8 A / 15 A core supply regulators with AVP and watchdog Rev. 2 - 5 June 2023

Source title PF5300 Datasheet(PDF) - NXP Semiconductors

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