18CV8 ETC
Document overview
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Technical content
Features
■■■■ Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available ■■■■ CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs ■■■■ Development / Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer - PLD-to-PEEL JEDEC file translator Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell configurations - Asynchronous clear - Independent output enables -- 20 Pin DIP/SOIC/TSSOP and PLCC ■■■■ Application Versatility - Replaces random logic - Super sets PLDs (PAL, GAL, EPLD) - Enhanced Architecture fits more logic than ordinary PLDs
Figure 3 PEEL18CV8 Logic Array Diagram
The PEEL18CV8 implements logic functions as sum-of- products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by program- ming the connections of input signals into the array. User- configurable output structures in the form of I/O macrocells further increase logic flexibility. Architecture Overview The PEEL18CV8 architecture is illustrated in the block dia- gram of Figure 2. Ten dedicated inputs and 8 I/Os provide up to 18 inputs and 8 outputs for creation of logic functions. At the core of the device is a programmable electrically- erasable AND array which drives a fixed OR array. With this structure, the PEEL18CV8 can implement up to 8 sum- of-products logic expressions. Associated with each of the 8 OR functions is an I/O mac- rocell which can be independently programmed to one of 12 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions of active-high or active-low polarity, while provid- ing three different feedback paths into the AND array. AND/OR LOGIC ARRAY The programmable AND array of the PEEL18CV8 (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as fol- lows: ■■■■ 36 Input Lines: - 20 input lines carry the true and complement of the signals applied to the 10 input pins - 16 additional lines carry the true and complement val- ues of feedback or input signals from the 8 I/Os ■■■■ 74 product terms: - 64 product terms (arranged in groups of 8) are used to form sum of product functions - 8 output enable terms (one for each I/O) - 1 global synchronous preset term - 1 global asynchronous clear term At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each prod- uct term is essentially a 36-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a “don’t care” state exists and that term will always be TRUE. When programming the PEEL18CV8, the device program- mer first performs a bulk erase to remove the previous pat- tern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function). Programmable I/O Macrocell The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configuration of the PEEL18CV8 to the precise requirements of their designs. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a D- type flip-flop and two signal-select multiplexers. The config- uration of each macrocell is determined by the four EEPROM bits controlling these multiplexers. These bits determine output polarity, output type (registered or non- registered) and input-feedback path (bidirectional I/O, com- binatorial feedback). Refer to Table 1 for details. Equivalent circuits for the twelve macrocell configurations are illustrated in Figure 5. In addition to emulating the four PAL-type output structures (configurations 3,4,9, and 10), the macrocell provides eight additional configurations. When creating a PEEL device design, the desired macro- cell configuration generally is specified explicitly in the design file. When the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the JEDEC programming file. Output Type The signal from the OR array can be fed directly to the out- put pin (combinatorial function) or latched in the D-type flip- flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or dis- abled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is switched into the high-impedance state. Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi- directional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically false and the I/O will function as a dedicated input. Input/Feedback Select The PEEL18CV8 macrocell also provides control over the feedback path. The input/feedback signal associated with each I/O macrocell may be obtained from three different locations; from the I/O input pin, from the Q output of the flip-flop (registered feedback), or directly from the OR gate (combinatorial feedback). Bi-directional I/O The input/feedback signal is taken from the I/O pin when using the pin as a dedicated input or as a bi-directional I/O. (Note that it is possible to create a registered output func- tion with a bi-directional I/O.) Combinatorial Feedback The signal-select multiplexer gives the macrocell the ability to feedback the output of the OR gate, bypassing the out- put buffer, regardless of whether the output function is reg- istered or combinatorial. This feature allows the creation of asynchronous latches, even when the output must be dis- abled. (Refer to configurations 5,6,7 and 8 in Figure 5.) Figure 4 Block Diagram of the PEEL18CV8 I/O Macrocell Registered Feedback Feedback also can be taken from the register, regardless of whether the output function is to be combinatorial or regis- tered. When implementing a combinatorial output function, registered feedback allows for the internal latching of states without giving up the use of the external output. Design Security The PEEL18CV8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the program- ming cycle or as a separate step, after the device has been programmed. Once the security bit is set it is impossible to verify (read) or program the PEEL until the entire device has first been erased with the bulk-erase function. Programming Support ICT’s JEDEC file translator allows easy conversion of exist- ing 20 pin PLD designs to the PEEL18CV8, without the need for redesign. ICT supports a broad range of popular third party design entry systems, including Data I/O Synario and Abel, Logical Devices CUPL and others. ICT also offers (for free) its proprietary PLACE software, an easy-to- use entry level PC-based software development system. Programming support includes all the popular third party programmers; Data I/O, Logical Devices, and numerous others. ICT also provides a low cost development program- mer system, the PDS-3.
Symbol Parameter Conditions Rating Unit VCC Supply Voltage Relative to Ground -0.5 to + 6.0 V VI, VO Voltage Applied to Any Pin2 Relative to Ground1 -0.5 to VCC + 0.6 V IO Output Current Per Pin (I OL , IOH )± 2 5 m A TST Storage Temperature -65 to +150 °C TLT Lead Temperature Soldering 10 Seconds +300 °C Symbol Parameter Conditions Min Max Unit Vcc Supply Voltage Commercial 4.75 5.25 V Industrial 4.5 5.5 V TA Ambient Temperature Commercial 0 +70 °C Industrial -40 +85 °C TR Clock Rise Time See Note 3. 20 ns TF Clock Fall TIme See Note 3. 20 ns TRVCC VCC Rise Time See Note 3. 250 ms Symbol Parameter Conditions Min Max Unit VOH Output HIGH Voltage - TTL V CC = Min, IOH = -4.0 mA 2.4 V V OHC Output HIGH Voltage - CMOS12 VCC = Min, IOH = -10 µA VCC - 0.3 V V OL Output LOW Voltage - TTL VCC = Min, IOL = 16mA/24mA13 0.5 V VOLC Output LOW Voltage - CMOS12 VCC = Min, IOL = 10 µA 0.15 V VIH Input HIGH level 2.0 V CC + 0.3 V VIL Input LOW Voltage -0.3 0.8 V IIL Input, I/O Leakage Current LOW Input and I/O pull-ups disabled VCC = Max, VIN = GND, I/O = High Z -10 µA IIP Input, I/O Leakage Current LOW Input and I/O pull-ups enabled VCC = Max, VIN = GND, I/O = High Z -100 µA IIH Input, I/O Leakage Current HIGH VCC = Max, VIN = V CC , I/O = High Z 0 (Typical) 40 µA ISC 9 Output Short Circuit Current V CC = 5V, VO = 0.5V, TA = 25°C -30 -135 mA ICC 10 VCC Current, f=1MHz VIN = 0V or VCC , f = 25 MHz All Outputs disabled4 -5 90 mA -7 90 -10 110/115 -15 45/55 -25 37/50 C IN7 Input Capacitance TA = 25°C, VCC = 5.0V @ f = 1 MHz 6p F C OUT 7 Output Capacitance 12 pF D.C. Electrical Characteristics Over the operating range (Unless otherwise specified) This device has been designed and tested for the specified operating ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.
- Test conditions assume: signal transition times of 3ns or less from the 10% and 90% points, timing reference levels of 1.5V (Unless otherwise specified). 9. Test one output at a time for a duration of less than 1 second. 10. I CC for a typical application: This parameter is tested with the device programmed as an 8-bit Counter. 11. Parameters are not 100% tested. Specifications are based on initial characterization and are tested after any design process modification that might affect operational frequency. 12. Available only for 18CV8 -15/I-15/-25/I-25 grades 13. 24mA available for 18CV8-5/-7. All other speeds are 16mA. A.C. Electrical Characteristics Over the operating range 8 Switching Waveforms Notes: 1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than 20 ns. 2. VI and VO are not specified for program/verify operation. 3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels. 4. I/O pins are 0V and VCC . 5. “Input” refers to an input pin signal. 6. tOE is measured from input transition to VREF ±0.1V, TOD is measured from input transition to VOH -0.1V or VOL +0.1V; VREF =V L. 7. Capacitances are tested on a sample basis. Symbol Parameter -5 -7 -10/I-10 -15/I-15 -25/I-25 UnitsMin Max Min Max Min Max Min Max Min Max tPD Input5 to non-registered output 5 7.5 10 15 25 ns tOE Input5 to output enable6 5 7.5 10 15 25 ns tOD Input5 to output disable6 5 7.5 10 15 25 ns tCO1 Clock to Output 4 7 7 12 15 ns tCO2 Clock to comb. output delay via internal registered feedback 7.5 10 12 25 35 ns tCF Clock to Feedback 2.5 3.5 4 8 15 ns tSC Input5 or feedback setup to clock 3 . 5 5 51 22 0 n s tHC Input5 hold after clock 0000 0 n s tCL , tCH Clock low time, clock high time8 3 3 . 5 51 01 5 n s tCP Min clock period Ext (tSC + tCO1 ) 7 12 12 24 35 ns fMAX1 Internal feedback (1/tSC +tCF )11 166.7 117.6 111 50 28.5 MHz fMAX2 External Feedback (1/tCP )11 133 83.3 83.3 41.6 28.5 MHz fMAX3 No Feedback (1/tCL +tCH )11 166.7 142.8 100 50 33.3 MHz tAW Asynchronous Reset Pulse Width 5 7.5 10 15 25 ns tAP Input5 to Asynchronous Reset 5 7.5 10 15 25 ns tAR Asynchronous Reset recovery time 5 7.5 10 15 25 ns tRESET Power-on reset time for registers in clear state 5555 5 µ s Inputs, I/O, Registered Feedback, Synchronous Preset Clock Asynchronous Reset Registered Outputs Combinatorial Outputs
PEEL Device and Array Test Loads
Ordering Information
Technology R1 R2 R L VL C L CMOS 12 480kΩ 480kΩ 228kΩ 2.375V 33 pF TTL -10/-15/-25 235 Ω 159Ω 95Ω 2.02V 33 pF TTL -5/-7 159 Ω 118Ω 68Ω 2.129V 33 pF Part Number Speed Temperature Package PEEL18CV8J-5 5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) PEEL18CV8P-7 7.5 ns Commercial 20-pin Plastic 300 mil DIP PEEL18CV8J-7 7.5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) PEEL18CV8S-7 7.5 ns Commercial 20-pin SOIC PEEL18CV8P-10 10 ns Commercial 20-pin Plastic 300 mil DIP PEEL18CV8PI-10 Industrial PEEL18CV8J-10 10 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) PEEL18CV8JI-10 Industrial PEEL18CV8S-10 10 ns Commercial 20-pin SOIC PEEL18CV8SI-10 Industrial PEEL18CV8T-10 10 ns Commercial 20-pin TSSOP 170 mil PEEL18CV8TI-10 Industrial PEEL18CV8P-15 15 ns Commercial 20-pin Plastic 300 mil DIP PEEL18CV8PI-15 Industrial PEEL18CV8J-15 15 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) PEEL18CV8JI-15 Industrial PEEL18CV8S-15 15 ns Commercial 20-pin SOIC PEEL18CV8SI-15 Industrial PEEL18CV8T-15 15 ns Commercial 20-pin TSSOP 170 mil PEEL18CV8TI-15 Industrial PEEL18CV8P-25 25 ns Commercial 20-pin Plastic 300 mil DIP PEEL18CV8PI-25 Industrial PEEL18CV8J-25 25 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC) PEEL18CV8JI-25 Industrial PEEL18CV8S-25 25 ns Commercial 20-pin SOIC PEEL18CV8SI-25 Industrial PEEL18CV8T-25 25 ns Commercial 20-pin TSSOP 170 mil PEEL18CV8TI-25 Industrial Output C L R2
5 VStandard
P = 20-pin Plastic 300mil DIP J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC) S = 20-pin SOIC 300 mil Gullwing T = 20-pin TSSOP 170 mil Speed –5 = 5ns tPD –7 = 7.5ns tPD –10 = 10ns tPD –15 = 15ns tPD –25 = 25ns tPD Temperature Range (Blank) = Commercial 0 to +70°C I = Industrial -40 to +85 °C