PC740A

MPC750A MOTOROLA

Document overview

• PDF pages: 44

Technical content

Page 1

Order Number: MPC750EC/D

Rev. 2.3, 9/2001

Semiconductor Products Sector

Technical Data

MPC750A RISC Microprocessor

Hardware Specifications

This document is primarily concerned with the MPC750, however, unless otherwise noted, all information here applies also to the MPC740. The MPC750 and MPC740 are implementations of the PowerPC™ family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent physical characteristics of the MPC750. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor User’s Manual. The MPC750 (and MPC740) is implemented in several semiconductor fabrication processes. Different processes may require different supply voltages and may have other electrical differences but will have the same functionality. As a designator to distinguish between MPC750 implementations in various processes,

a suffix is added to the MPC750 part number as shown below:

Table 1. MPC750 Microprocessors from Motorola

This document will describe only the MPC750A implementation. The XPC750P is described in a separate document.

This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2001. All rights reserved.

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This document contains the following topics: Topic

Page

Section 1.1, “Overview”

3

Section 1.2, “Features”

4

Section 1.3, “General Parameters”

6

Section 1.4, “Electrical and Thermal Characteristics”

6

Section 1.4.1, “DC Electrical Characteristics”

6

Section 1.4.2, “AC Electrical Characteristics”

10

Section 1.4.2.1, “Clock AC Specifications”

10

Section 1.4.2.2, “60x Bus Input AC Specifications”

12

Section 1.4.2.3, “60x Bus Output AC Specifications”

14

Section 1.4.2.4, “L2 Clock AC Specifications”

15

Section 1.4.2.5, “L2 Bus Input AC Specifications”

18

Section 1.4.2.6, “L2 Bus Output AC Specifications”

19

Section 1.5, “Pin Assignments”

23

Section 1.6, “Pinout Listings”

25

Section 1.7, “Package Description”

29

Section 1.8, “System Design Information”

31

Section 1.9, “Document Revision History

42

To locate any published errata or updates for this document, refer to the website at http://www.mot.com/PowerPC/.

Page 3

Overview

1.1 Overview

The MPC750 is targeted for low-cost, low-power systems and supports the following power management

features—doze, nap, sleep, and dynamic power management. The MPC750 consists of a processor core

and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.

Figure 1 shows a block diagram of the MPC750.

Figure 1. MPC750 Block Diagram

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Features

1.2 Features

This section summarizes features of the MPC750’s implementation of the PowerPC architecture. Major features of the MPC750 are as follows:

• Branch processing unit — Four instructions fetched per clock — One branch processed per cycle (plus resolving 2 speculations) — Up to 1 speculative stream in execution, 1 additional speculative stream in fetch — 512-entry branch history table (BHT) for dynamic prediction — 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots
• Dispatch unit — Full hardware detection of dependencies (resolved in the execution units) — Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, or floating-point)

— Serialization control (predispatch, postdispatch, execution serialization)

• Decode — Register file access — Forwarding control — Partial instruction decode
• Load/store unit — One cycle load or store cache access (byte, half-word, word, double-word) — Effective address generation — Hits under misses (one outstanding miss) — Single-cycle misaligned access within double word boundary — Alignment, zero padding, sign extend for integer register file — Floating-point internal format conversion (alignment, normalization) — Sequencing for load/store multiples and string operations — Store gathering — Cache and TLB instructions — Big- and little-endian byte addressing supported — Misaligned little-endian support in hardware
• Fixed-point units — Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical — Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical — Single-cycle arithmetic, shift, rotate, logical — Multiply and divide support (multi-cycle) — Early out multiply
• Floating-point unit — Support for IEEE-754 standard single- and double-precision floating-point arithmetic — 3 cycle latency, 1 cycle throughput, single-precision multiply-add

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Features

— 3 cycle latency, 1 cycle throughput, double-precision add — 4 cycle latency, 2 cycle throughput, double-precision multiply-add — Hardware support for divide — Hardware support for denormalized numbers — Time deterministic non-IEEE mode

• System unit — Executes CR logical instructions and miscellaneous system instructions — Special register transfer instructions
• Cache structure — 32K, 32-byte line, 8-way set associative instruction cache — 32K, 32-byte line, 8-way set associative data cache — Single-cycle cache access — Pseudo-LRU replacement — Copy-back or write-through data cache (on a page per page basis) — Supports all PowerPC memory coherency modes — Non-blocking instruction and data cache (one outstanding miss under hits) — No snooping of instruction cache
• Memory management unit — 128 entry, 2-way set associative instruction TLB — 128 entry, 2-way set associative data TLB — Hardware reload for TLBs — 4 instruction BATs and 4 data BATs

52

— Virtual memory support for up to 4 exabytes (2

) of virtual memory 32

— Real memory support for up to 4 gigabytes (2

) of physical memory

• Level 2 (L2) cache interface (not implemented on MPC740) — Internal L2 cache controller and 4K-entry tags; external data SRAMs — 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support — Copy-back or write-through data cache (on a page basis, or for all L2) — 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size — Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs

— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported

• Bus interface — Compatible with 60x processor interface — 32-bit address bus — 64-bit data bus — Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x supported
• Integrated power management — Low-power 2.6/3.3-volt design — Three static power saving modes: doze, nap, and sleep

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General Parameters

— Automatic dynamic power reduction when internal functional units are idle

• Integrated Thermal Management Assist Unit — On-chip thermal sensor and control logic — Thermal Management Interrupt for software regulation of junction temperature.
• Testability — LSSD scan design — JTAG interface
• Reliability and serviceability—Parity checking on 60x and L2 cache buses

1.3 General Parameters

The following list provides a summary of the general parameters of the MPC750:

0.29 µm CMOS, five-layer metal

Technology:

2

7.56 mm x 8.79 mm (67 mm

Die size:

)

Transistor count

6.35 million

Logic design

Fully-static MPC740: Surface mount 255 ceramic ball grid array (CBGA) without L2

Packages

interface MPC750: Surface mount 360 ceramic ball grid array (CBGA) with L2 interface

Core power supply:

2.6V ± 100 mV

I/O power supply

3.3V ± 5% V dc

1.4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC750.

1.4.1 DC Electrical Characteristics

The tables in this section describe the MPC750 DC electrical characteristics. Table 2 provides the absolute maximum ratings.

Table 2. Absolute Maximum Ratings

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Electrical and Thermal Characteristics

Table 2. Absolute Maximum Ratings (Continued)

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Electrical and Thermal Characteristics

Table 3. Recommended Operating Conditions (Continued)

Note:These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 1. For extended temperature parts marked MPC750ARXnnnTH or MPC740ARXnnnTH only (where nnn is the operating frequency from Table 8.

Table 4 provides the package thermal characteristics for the MPC750.

Table 4. Package Thermal Characteristics

Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see Motorola Application Note AN1800/D, “Programming the Thermal Assist Unit in the MPC750 Microprocessor”. 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. Guaranteed by design and characterization.

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Electrical and Thermal Characteristics

Table 6 provides the DC electrical characteristics for the MPC750.

Table 6. DC Electrical Specifications

At recommended operating conditions (See Table 3)

Notes: 1. Nominal voltages; See Table 3 for recommended operating conditions. 2. For 60x bus signals, the reference is OVdd while L2OVdd is the reference for the L2 bus signals. 3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. 4. Applicable to L2 bus interface only 5. Capacitance is periodically sampled rather than 100% tested. 6. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both OVdd and Vdd vary by either +5% or -5%).

Table 7 provides the power consumption for the MPC750.

Table 7. Power Consumption for MPC750

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Electrical and Thermal Characteristics

Table 7. Power Consumption for MPC750 (Continued)

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Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (Continued)

At recommended operating conditions (See Table 3)

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8.1, “PLL Configuration,” for valid PLL_CFG[0–3] settings 2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V. 3. Timing is guaranteed by design and characterization. 4. The total input jitter (short term and long term combined) must be under ±150 ps. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time

required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 3 provides the SYSCLK input timing diagram.

SYSCLK

VM = Midpoint Voltage (1.4V)

Figure 3. SYSCLK Input Timing Diagram

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Electrical and Thermal Characteristics

1.4.2.2 60x Bus Input AC Specifications

Table 9 provides the 60x bus input AC timing specifications for the MPC750 as defined in Figure 4 and

Figure 5. Input timing specifications for the L2 bus are provided in Section 1.4.2.5, “L2 Bus Input AC

Specifications.

Table 9. 60x Bus Input AC Timing Specifications1

At recommended operating conditions (See Table 3)

Notes: 1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/Data/Transfer Attribute inputs are composed of the following—A[0–31], AP[0–3], TT[0–4], TBST, TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7]. 3. All other signal inputs are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table

must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Guaranteed by design and characterization. 7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.

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Electrical and Thermal Characteristics

Figure 4 provides the input timing diagram for the MPC750.

SYSCLK

ALL INPUTS

HRESET

MODE PINS

VIH = 2.0V

Figure 5. Mode Select Input Timing Diagram

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Electrical and Thermal Characteristics

1.4.2.3 60x Bus Output AC Specifications

Table 10 provides the 60x bus output AC timing specifications for the MPC750 as defined in Figure 6.

Output timing specifications for the L2 bus are provided in Section 1.4.2.6, “L2 Bus Output AC

Specifications.”

Table 10. 60x Bus Output AC Timing Specifications1

At recommended operating conditions (See Table 3), CL = 50 pF2

Notes: 1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timing are measured at the pin. 2. All maximum timing specifications assume CL = 50 pF. 3. This minimum parameter assumes CL = 0 pF. 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question. 5. Output signal transitions from GND to 2.0V or OVdd to 0.8V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk.

1. Guaranteed by design and characterization.

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Electrical and Thermal Characteristics

Figure 6 provides the output timing diagram for the MPC750.

SYSCLK

ALL OUTPUTS (Except TS, ABB, ARTRY, DBB)

TS

ABB, DBB

ARTRY

VM = Midpoint Voltage (1.4V)

Figure 6. Output Timing Diagram

1.4.2.4 L2 Clock AC Specifications

Table 11 provides the L2CLK output AC timing specifications as defined in Figure 7.

Table 11. L2CLK Output AC Timing Specifications

At recommended operating conditions (See Table 3)

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Electrical and Thermal Characteristics

Table 11. L2CLK Output AC Timing Specifications (Continued)

At recommended operating conditions (See Table 3)

Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB and L2SYNC_OUT pins. The L2 cache interface supports higher frequencies when appropriate load conditions have been considered. The L2 I/O drivers have been designed to support a 133 MHz L2 bus loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond 133 MHz requires tightly coupled customized SRAMs or a multi-chip module (MCM) implementation. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. L2CLK_OUTA and L2CLK_OUTB must have equal loading.

1. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz 5. Guaranteed by design and not tested.

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Electrical and Thermal Characteristics

The L2CLK_OUT timing diagram is shown in Figure 7.

L2 Single-Ended Clock Mode

L2CLK_OUTA

L2CLK_OUTB

L2SYNC_OUT

L2 Differential Clock Mode

L2CLK_OUTB

L2CLK_OUTA

L2SYNC_OUT

VM = Midpoint Voltage (L2OVdd/2)

Figure 7. L2CLK_OUT Output Timing Diagram

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Electrical and Thermal Characteristics

1.4.2.5 L2 Bus Input AC Specifications

The L2 bus input interface AC timing specifications are found in Table 12.

Table 12. L2 Bus Input Interface AC Timing Specifications1

At recommended operating conditions (See Table 3)

Notes: 1. All input specifications are measured from the TTL level (0.8V or 2.0V) of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN. Input timings are measured at the pins (see Figure 8). 2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.

Figure 8 shows the L2 bus input timing diagrams for the MPC750.

L2SYNC_IN

ALL INPUTS

VM = Midpoint Voltage (1.4V)

Figure 8. L2 Bus Input Timing Diagrams

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Electrical and Thermal Characteristics

1.4.2.6 L2 Bus Output AC Specifications

Table 13 provides the L2 bus output interface AC timing specifications for the MPC750 as defined in

Figure 9.

Table 13. L2 Bus Output Interface AC Timing Specifications1

At recommended operating conditions (See Table 3), CL = 20 pF3

Figure 9 shows the L2 bus output timing diagrams for the MPC750.

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Electrical and Thermal Characteristics

L2SYNC_IN

ALL OUTPUTS

L2DATA BUS

VM = Midpoint Voltage (1.4V)

Figure 9. L2 Bus Output Timing Diagrams

1.4.3 IEEE 1149.1 AC Timing Specifications

Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 10, Figure 11,

Figure 12, and Figure 13.

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (See Table 3), CL = 50 pF

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Electrical and Thermal Characteristics

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) At recommended operating conditions (See Table 3), CL = 50 pF

Notes: 1. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 2. Non-JTAG signal input timing with respect to TCK. 3. Non-JTAG signal output timing with respect to TCK. 4. Guaranteed by design and characterization.

Figure 10 provides the JTAG clock input timing diagram.

TCK

VM = Midpoint Voltage

Figure 10. JTAG Clock Input Timing Diagram

Figure 11 provides the TRST timing diagram.

TRST

5

Figure 11. TRST Timing Diagram

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Electrical and Thermal Characteristics

Figure 12 provides the boundary-scan timing diagram.

TCK

DATA INPUTS

DATA OUTPUTS

DATA OUTPUTS

DATA OUTPUTS

Figure 13 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

TDO

TDO

Figure 13. Test Access Port Timing Diagram

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Pin Assignments

1.5 Pin Assignments

Figure 14 (in part A) shows the pinout of the MPC740, 255 CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view.

Part A

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

A B C D E F G H J K L M

N P R T

Not to Scale

Part B

View

Figure 14. Pinout of the MPC740, 255 CBGA Package as Viewed from the Top Surface

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Pin Assignments

Figure 15 (in part A) shows the pinout of the MPC750, 360 CBGA package as viewed from the top

surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface

view.

Part A

10 11 12 13 14 15 16 17 18 19

1 2 3 4 5 6 7 8 9

A B C D E F G H J K L M

N P R T

U V W

Not to Scale

Part B

View

Figure 15. Pinout of the MPC750, 360 CBGA Package as Viewed from the Top Surface

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Pinout Listings

1.6 Pinout Listings

Table 15 provides the pinout listing for the MPC740, 255 CBGA package.

Table 15. Pinout Listing for the MPC740, 255 CBGA Package

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Pinout Listings

Table 15. Pinout Listing for the MPC740, 255 CBGA Package (Continued)

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Pinout Listings

Table 16. Pinout Listing for the MPC750, 360 CBGA Package (Continued)

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Pinout Listings

Table 16. Pinout Listing for the MPC750, 360 CBGA Package (Continued)

Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 3. Internally tied to L2OVDD in the MPC750 CBGA package to indicate the power present at the L2 cache interface. This signal is not a power supply input. Caution: This is different from the MPC740 CBGA package. 4. These pins are reserved for potential future use as additional L2 address pins.

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Package Description

1.7 Package Description

The following sections provide the package parameters and mechanical dimensions for the MPC740, 255 CBGA packages.

1.7.1 Parameters for the MPC740

The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline

21 x 21 mm 255 (16 x 16 ball array - 1)

Interconnects Pitch

1.27 mm (50 mil)

Minimum module height 2.45 mm Maximum module height 3.00 mm Ball diameter

0.89 mm (35 mil)

1.7.2 Mechanical Dimensions of the MPC740

Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the MPC740, 255 CBGA package.

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Package Description

2X

Dimensioning and tolerancing per ASME Y14.5M, 1994. Dimensions in millimeters. Top side A1 corner index is a metalized feature with various shapes. bottom side A1 corner is designated with a ball

Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC740

1.7.3 Parameters for the MPC750

The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA). Package outline

25 x 25 mm

Interconnects

360 (19 x 19 ball array - 1)

Pitch

1.27 mm (50 mil)

Minimum module height 2.65 mm Maximum module height 3.20 mm Ball diameter

0.89 mm (35 mil)

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System Design Information

1.7.4 Mechanical Dimensions of the MPC750

Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC750, 360

CBGA package.

DIMENSIONS AND TOLERANCING PER ASME

E2

DIMENSIONS IN MILLIMETERS. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE AND UNDERFILL. ACTUAL SIZE OF THIS AREA MAY BE SMALLER THAN SHOWN. D3 AND E3 ARE THE MINIMUM CLEARANCE FROM THE PACKAGE EDGE TO THE CHIP CAPACITORS. CAPACITORS MAY NOT BE PRESENT ON ALL

CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON

2X

MILLIMETERS

DIM MIN MAX

A 2.72 3.20 A1 0.80 1.00 A2 1.10 1.30 --- 0.60 A3 A4 0.82 0.90 b 0.82 0.93 25.00 BSC D D1 22.86 BSC --- 12.50 D2 D3 2.75 --- D4 6.00 9.00 1.27 BSC e 25.00 BSC E E1 22.86 BSC --- 14.30 E2 E3 3.00 --- E4 8.00 11.00

Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC750

1.8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC750.

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System Design Information

1.8.1 PLL Configuration

The MPC750’s PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency,

the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL

configuration for the MPC750 is shown in Table 17 for nominal frequencies.

Table 17. MPC750 Microprocessor PLL Configuration

Notes: 1. PLL_CFG[0–3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC750; see Section 1.4.2.1, “Clock AC Specifications,” for valid SYSCLK and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the MPC750 regardless of the SYSCLK input.

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System Design Information

Table 18 provides sample core-to-L2 frequencies.

Table 18. Sample Core-to-L2 Frequencies

Note: The core and L2 frequencies are for reference only. Some configurations may select core or L2 frequencies which are not useful, not supported, or not tested for by the MPC750; see Section 1.4.2.4, “L2 Clock AC Specifications,” for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz.

1.8.2 PLL Power Supply Filtering

The AVdd and L2AVdd power signals are provided on the MPC750 to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 18. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. An identical but separate circuit should be placed as close as possible to the L2AVdd pin.

10 Ω Vdd

AVdd (or L2AVdd)

0.1 µF

10 µF

GND

Figure 18. PLL Power Supply Filter Circuit

1.8.3 Decoupling Recommendations

Due to the MPC750’s dynamic power management feature, large address and data buses, and high operating frequencies, the MPC750 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC750 system, and the MPC750 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin (and L2OVdd for the 360 CBGA) of the MPC750. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the

PCB, utilizing short traces to minimize inductance.

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System Design Information

These capacitors should vary in value from 220 pF to 10 µF to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pins. Suggested values for the Vdd pins—220 pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the OVdd pins—0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk

capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100 µF (AVX TPS tantalum) or 330 µF (AVX TPS tantalum).

1.8.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the MPC750. External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all SRAMs and at the L2SYNC_IN input of the MPC750. The L2CLKOUTA network could be used only, or the L2CLKOUTB network could also be used depending on the loading, frequency, and number of

SRAMs.

1.8.5 Output Buffer DC Impedance

The MPC750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected to the chip pad, either to OVdd or OGND. Then, the value of such resistor is varied until the pad voltage is OVdd/2; see Figure 19. The output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVdd/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open), and RP is trimmed until Pad = OVdd/2. RP then becomes the resistance of the

pull-up devices. With a properly designed driver RP and RN are close to each other in value. Then Z0 = (RP + RN)/2.

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System Design Information

OVdd

RP

OGND

Figure 19. Driver Impedance Measurement

Table 19 summarizes the signal impedance results. The driver impedance values were derived by simulation at 65 °C. As the process varies, the output impedance will be reduced by several ohms.

Table 19. Impedance Characteristics

Vdd = 2.6V, OVdd = 3.3V, Tj = 65 °C

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System Design Information

1.8.6 Pull-up Resistor Requirements

The MPC750 requires high-resistive (weak: 10 KΩ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC750 or other bus masters. These signals are TS, ABB, DBB, and ARTRY. In addition, the MPC750 has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7 KΩ–10 KΩ) if it is used by the system. This signal is CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the MPC750

must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC750 or by other receivers in the system. It is recommended that these signals be pulled up through weak (10 KΩ) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are A[0–31], AP[0–3], TT[0–4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the system during inactive periods. The data bus

signals are DH[0–31], DL[0–31], DP[0–7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. No pull-up resistors are normally required for the L2 interface.

1.8.7 Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design—the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods—adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see Figure 20. This spring force should not exceed 5.5 pounds of force.

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System Design Information

CBGA Package

Heat Sink

Heat Sink

Adhesive or Thermal Interface Material

Option

Figure 20. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the MPC750. There are several commercially-available heat sinks for the MPC750 provided by the following vendors: Chip Coolers Inc.

800-227-0254 (USA/Canada)

333 Strawberry Field Rd.

401-739-7600

Warwick, RI 02887-6979 International Electronic Research Corporation (IERC)

818-842-7277

135 W. Magnolia Blvd. Burbank, CA 91502 Thermalloy

214-243-4321

2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731 Wakefield Engineering

617-245-5900

60 Audubon Rd. Wakefield, MA 01880 Aavid Engineering

603-528-3400

One Kool Path Laconia, NH 03247-0440 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

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System Design Information

1.8.7.1 Internal Package Conduction Resistance

For the exposed-die packaging technology, shown in Table 4, the intrinsic conduction thermal resistance paths are as follows:

• The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
• The die junction-to-ball thermal resistance

Figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

External Resistance

Radiation

Convection

External Resistance

(Note the internal versus external package resistance)

Figure 21. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms.

1.8.7.2 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 22 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 20). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.

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System Design Information

1.5

0.5

0 10 20 30 40 50 60 70 80

Contact Pressure (psi)

Figure 22. Thermal Performance of Select Thermal Interface Material

The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: Dow-Corning Corporation

517-496-4000

Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Chomerics, Inc.

617-935-4850

77 Dragon Court Woburn, MA 01888-4850 Thermagon Inc.

216-741-7659

3256 West 25th Street Cleveland, OH 44109-1668 Loctite Corporation

860-571-5100

1001 Trout Brook Crossing Rocky Hill, CT 06067 AI Technology (e.g. EG7655)

609-882-2332

1425 Lower Ferry Rd. Trent, NJ 08618

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System Design Information

The following section provides a heat sink selection example using one of the commercially available heat sinks.

1.8.7.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (θjc + θint + θsa) \* Pd Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet θjc is the junction-to-case thermal resistance θint is the adhesive or interface material thermal resistance θsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air

temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40 °C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 °C. The thermal resistance of the thermal interface material (θint) is typically about 1 °C/W. Assuming a Ta of 30 °C, a Tr of 5 °C, a CQFP package θjc = 2.2, and a power consumption (Pd) of 4.5 watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30 °C + 5 °C + (2.2 °C/W + 1.0 °C/W + θsa) \* 4.5 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus airflow velocity is shown in Figure 23.

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System Design Information

0 0.5 1 1.5 2 2.5 3 3.5

Approach Air Velocity (m/s)

Figure 23. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity

Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 °C/W, thus Tj = 30 °C + 5 °C + (2.2 °C/W +1.0 °C/W + 7 °C/W) \* 4.5 W, resulting in a die-junction temperature of approximately 81 °C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several “compact” thermal-package models are available within FLOTHERM®. These are available upon request.

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Document Revision History

1.9 Document Revision History

Table 20. Document Revision History

1.10 Ordering Information

This section provides the part numbering nomenclature for the MPC750. Note that the individual part

numbers correspond to a maximum processor core frequency. For available frequencies, contact your local

Motorola sales office.

Figure 24 provides the Motorola part numbering nomenclature for the MPC750. In addition to the

processor frequency, the part numbering scheme also consists of a part modifier and application modifier.

The part modifier indicates any enhancement(s) in the part from the original production design. The bus

divider may specify special bus frequencies or application conditions. Each part number also contains a

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Ordering Information

revision code. This refers to the die mask revision number and is specified in the part numbering scheme

for identification purposes only.

MPC 750 A RX XXX X X

Revision Level

Product Code

Part Identifier (740 or 750)

Part Modifier

Package (RX = BGA)

Figure 24. Motorola Part Number Key

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DigitalDNA is a trademark of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.