PA502FMG ETC2

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P-Channel Logic Level Enhancement Mode Field Effect Transistor PA502FMG SOT -23 Lead-Free NIKO-SEM Nov-03-2004 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -20 V Gate-Source Voltage VGS ±12 V TC = 25 °C -3 Continuous Drain Current TC = 70 °C ID -1.4 Pulsed Drain Current1 IDM -10 A TC = 25 °C 1.25 Power Dissipation TC = 70 °C PD 0.8 W Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Ambient Rθ JA 166 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -20 Gate Threshold Voltage VGS(th) VDS = VGS, ID = -250µA -0.5 -0.9 -1.2 V Gate-Body Leakage IGSS VDS = 0V, V GS = ±12V ±100 nA VDS = -16V, VGS = 0V -1 Zero Gate Voltage Drain Current IDSS VDS = -16V, VGS = 0V, TJ = 125 °C -10 µA On-State Drain Current1 ID(ON) VDS = -5V, VGS = -4.5V -6 A VGS = -4.5V, ID =-2A 100 150 Drain-Source On-State Resistance1 RDS(ON) VGS = -2.5V, ID = -1A 180 250 mΩ 1 :GATE 2 :DRAIN 3 :SOURCE PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -20 150mΩ -3A G S D

P-Channel Logic Level Enhancement Mode Field Effect Transistor PA502FMG SOT -23 Lead-Free NIKO-SEM Nov-03-2004 Forward Transconductance1 gfs VDS = -5V, ID = -2A 16 S DYNAMIC Input Capacitance Ciss 410 Output Capacitance Coss 220 Reverse Transfer Capacitance Crss VGS = 0V, V DS = -6V, f = 1MHz pF Total Gate Charge2 Qg 5.8 10 Gate-Source Charge2 Qgs 0.85 Gate-Drain Charge2 Qgd VDS = 0.5V(BR)DSS, VGS = -4.5V, ID = -2A 1.70 nC Turn-On Delay Time2 td(on) 13 Rise Time2 tr VDD = -10V 36 Turn-Off Delay Time2 td(off) ID ≅ -1A, VGS = -4.5V, RG = 6Ω 42 Fall Time2 tf 34 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -1.6 Pulsed Current3 ISM -3 A Forward Voltage1 VSD IF = -1A, VGS = 0V -1.2 V 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “20YWW”, DATE CODE or LOT # Orders for parts with Lead -Free plating can be placed using the PXXXXXXG parts name.

P-Channel Logic Level Enhancement Mode Field Effect Transistor PA502FMG SOT -23 Lead-Free NIKO-SEM Nov-03-2004 Body Diode Forward Voltage Variation with Source Current and Temperature T = 125° C -V - Body Diode Forward Voltage(V) 0.6 -Is - Reverse Drain Current(A) 0.0001 0.001 0.01 SD 0.2 0.4 25° C V = 0V 0.1 GS A 0.8 1.0 -55° C 1.2

P-Channel Logic Level Enhancement Mode Field Effect Transistor PA502FMG SOT -23 Lead-Free NIKO-SEM Nov-03-2004

P-Channel Logic Level Enhancement Mode Field Effect Transistor PA502FMG SOT -23 Lead-Free NIKO-SEM Nov-03-2004 SOT-23 (M3) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. B 2.4 3 I 0.37 C 1.4 1.6 1.8 J D 2.7 2.9 3.1 K E 1 1.1 1.3 L F 0 0.1 M G 0.35 0.5 N D E G B F C A 1 3 I H