P65630SVCGR

TPSM65630 TI

Document overview

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Technical content

TPSM656x0 High-Density, 3V to 65V Input, 1V to 24V Output, 3A, 2A, 1A, Synchronous, Buck, DC/DC Power Module With Enhanced HotRod™ QFN Package

1 Features

• Versatile synchronous buck DC/DC module – Integrated MOSFETs, inductor, and controller – 3V to 65V wide input voltage range – 40ns (maximum) low minimum on time enables 36V to 3.3V conversion at 2.2MHz – –40°C to 150°C junction temperature range – 5.80mm × 5.20mm × 2.93mm enhanced HotRod™ QFN package with exposed inductor – Frequency adjustable from 300kHz to 2.2MHz
• Ultra-high efficiency across the full load range – > 92% peak efficiency at 24VIN, 5VOUT, 400kHz – 2.5µA PFM no-load input current
• Optimized for ultra-low EMI requirements – Facilitates CISPR 11 Class B compliance – Mode pin configurable ±5% or ±10% dual- random spread spectrum reducing peak emissions – Enhanced HotRod QFN package with symmetrical pinout – Pin-configurable 400kHz and 2.2MHz – Pin-configurable AUTO or FPWM operation
• Output voltage and current options – 3.3V or 5V VOUT fixed output variants – Adjustable output voltage from 1V to 24V – 3A, 2A, 1A output current options
• Inherent protection features for robust design – Precision enable input and open-drain power- good indicator for sequencing, control, and VIN UVLO – Overcurrent and thermal shutdown protections

2 Applications

• Industrial transport systems
• Factory automation and control systems
• Medical imaging systems
• Test and measurement systems
• Aerospace and defense
• Building automation
• Power delivery
• Robotics

3 Description

The TPSM656x0 is a family of 3A, 2A, 1A , 65V (70V tolerant) input synchronous step-down DC/DC power module that combines power MOSFETs, integrated inductor, and passives in a compact and easy-to- use 5.8mm × 5.2mm × 2.93mm, 19-pin enhanced HotRod QFN package. With the pin-selectable fixed- output voltages of 3.3V and 5V and adjustable output voltage from 1V to 24V, the TPSM656x0 is designed to quickly and easily implement a low- EMI design in a small PCB footprint. The module only requires the input and output filter capacitors to finish the design and eliminates the magnetics and compensation part selection from the design process. A pin-selectable ±5% or ±10% dual-random spread spectrum (DRSS) significantly reduces peak emissions through a combination of triangular and pseudo-random modulation while keeping output voltage ripple very low. Device Information PART NUMBER(3) PACKAGE (1) PACKAGE SIZE(2) TPSM65630, TPSM65620(4), TPSM65610(4) VCG (QFN-FCMOD, 19) 5.2mm × 5.8mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) See the Device Comparison Table. (4) Product preview (not Advance Information). VIN1 VIN2 EN/ UVLO VCC MODE/ SYNC RT VOUT FB PG BIAS NC1 NC2 PGND PGND 3V to 65VIN 5VOUT VOUT FSW = 2.2MHz VCC Simplified Schematic ADVANCE INFORMATION TPSM65630 SNVSCU1 – JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice.

Although designed for small size and simplicity in space-constrained applications, the TPSM656x0 module offers many features for robust performance. The current-mode control architecture with a 30ns typical minimum on- time allows high conversion ratios at high frequencies coupled with a fast transient response and excellent load and line regulation. The precision EN feature allows precise control of the device during start-up and shutdown. An open-drain PGOOD output provides a true indication of the output voltage status. The TPSM656x0 includes accurate overcurrent and temperature protections, making the TPSM656x0 an excellent device for powering a wide range of industrial applications. The MODE/ SYNC pin enables seamless transition between FPWM and AUTO mode with a no-load standby quiescent current of less than 2.5 μA (typical), ensuring high efficiency and remarkable transient response for the entire load-current range. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable

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4 Device Comparison Table

ORDERABLE PART NUMBER CURRENT SPREAD SPECTRUM TPSM65630SVCGR 3A Yes TPSM65630VCGR(1) 3A No TPSM65620SVCGR(1) 2A Yes TPSM65610SVCGR(1) 1A Yes (1) Product preview (not Advance Information) TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. 19-Pin VCG, QFN-FCMOD Package (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. FB 1 A Feedback configuration pin. Connect to GND to configure 3.3V fixed output voltage. Connect to VCC to configure 5V fixed output voltage. Connect this pin to a feedback divider for adjustable output options. The regulation threshold is 0.8V. VOUT 2 O Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external output capacitors between the pin and PGND. MODE / SYNC 3 I/O Mode and synchronization input pin. Connect to GND, or drive the pin low to operate in AUTO mode. Connect to VCC, or drive the pin high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency. RT 4 I/O Switching frequency programming pin. Connect this pin to VCC for 400kHz operation, or to GND for 2.2MHz operation. Connect this pin to ground through a resistor to set the switching frequency between 300kHz and 2200kHz. Do not float. EN / UVLO 5 P Precision enable pin. High = ON, Low = OFF. This pin can be directly connected to VIN. The precision threshold on this input enables use as an adjustable UVLO. Do not float. NC 6 — No connect pin. Leave floating. NC 7 — No connect pin. Leave floating. PGND1 8 G Power ground to low-side MOSFET. Connect to system ground. Connect a high-quality bypass capacitor or capacitors between this pin and VIN1. VIN1 9 P Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND1. Provide a low-impedance connection to VIN2. SW 10 P Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI. VIN2 11 P Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND2. Provide a low-impedance connection to VIN1. PGND2 12 G Power ground to internal low-side MOSFET. Connect to system ground. Connect high- quality bypass capacitors between this pin and VIN2. BIAS 13 P Input to internal voltage regulator. If configured for fixed VOUT, connect this pin to the VOUT node to close the control loop. If configured for an adjustable VOUT, connect this pin to the VOUT node or an external bias supply from 3.3V to 30V. If output voltage is above 30V and no external supply is used, tie the pin to GND. www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM65630 ADVANCE INFORMATION

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. VCC 14 P Internal LDO output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Can be used for logic pull-up to control or flag pins. A 2.2μF capacitor internally connects from VCC to AGND. NC 15 — NNo connect pin. Leave floating. PG 16 O Power Good flag output. Open drain output that goes low if VOUT is outside of the specified regulation window. GND 17, 18 G Exposed ground pad. Connect to system GND on the PCB. This pin is a major heat dissipation path for the die. The pad must be used for heat sinking by soldering to the GND copper on a PCB. Implementing as many thermal vias as suggested in the example board layout makes sure of the lowest package thermal resistance and best possible thermal performance. BOOT 19 P Bootstrap pin for internal high-side driver circuitry. A 100nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. (1) I = input, O = output, A = Analog, P = Power, G = Ground TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range –40°C to +150°C (unless otherwise noted) (1) MIN MAX UNIT Input voltage VIN to PGND –0.3 70 V Input voltage EN/UVLO TO PGND –0.3 70 V Input voltage RT to PGND –0.3 70 V Input voltage BIAS TO PGND –0.3 40 V Input voltage MODE/CLKIN to PGND –0.3 5.5 V Input voltage FB to PGND –0.3 5.5 V Output voltage SW to PGND –0.6 VIN+0.3 V Output voltage PG to PGND –0.3 40 V Output voltage BST to SW –0.3 5.5 V Output voltage VCC to PGND –0.3 5.5 V Operating junction temperature TJ –40 150 °C Storage temperature Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V V(ESD) Electrostatic discharge Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range –40°C to +150°C (unless otherwise noted) MIN MAX UNIT Input voltage VIN 3 65 V Input voltage EN 0 65 V Input voltage BIAS, PG 0 30 V Input voltage FB 0 5.5 V Input voltage MODE/SYNC, RT 0 5.5 V Pullup Resistance RPU(PG) 4 kΩ Pullup Refernce Voltage VPU(PG) 0.8 30 V Output Voltage VOUT 1 V Operating junction temperature TJ –40 150 °C www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM65630 ADVANCE INFORMATION

6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNITVCG (QFN-FCMOD)

19 PINs

RθJA Junction-to-ambient thermal resistance(3) 24.2 °C/W RθJA Junction-to-ambient thermal resistance (JESD 51-7)(2) 35.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 24.5 °C/W RθJB Junction-to-board thermal resistance 14 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W ΨJB Junction-to-board characterization parameter 13.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note (2) The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. The thermal parameters do not represent the performance obtained in an actual application. For example, the EVM RΘJA = 24.2 °C/W. For design information please see the Maximum Ambient Temperature section. (3) Refer to the TPSM65630EVM user's guide for board layout and additional information. For thermal design information please see the Maximum Ambient Temperature section.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, fSW = 2.2MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY (VIN PIN) VINUVLO_R VIN UVLO rising threshold VIN rising (Needed to start up), IVCC = 0A 3.5 V VINUVLO_H VIN UVLO hysteresis 0.9 V IVIN VIN pin input current, no switching VBIAS = 3.3V + 2% 0.83 µA IBIAS(FIX-3.3V) BIAS pin input current, fixed 3.3V output, no switching VBIAS = 3.3V + 2%, auto mode enabled 8.0 µA IQ(FIX-3.3V) Total VIN quiescent current, fixed 3.3V output, no switching VIN = 24V, VBIAS = 3.3V + 2%, TJ = 25℃, Auto Mode enabled 2.1 µA IBIAS(ADJ-3.3V) BIAS pin input current, adjustable 3.3V output, no switching VFB = 0.8V + 2%, Auto Mode 6.5 µA IQ(ADJ-3.3V) Total VIN quiescent current, adjustable 3.3V output, no switching VIN = 24.0V, VFB = 0.8V + 2%, Auto Mode 2.5 µA ENABLE (EN PIN) VEN_TH_R Enable voltage rising threshold VEN rising 1.25 V VEN_TH_F Enable input low threshold VEN falling 1 V VEN_HYS Enable voltage hysteresis 250 mV IEN_LKG Enable input leakage current VEN = VIN 0.2 µA INTERNAL LDO (VCC PIN) VVCC Internal LDO output voltage 3.4V ≤ VIN ≤ 65V, VBIAS = 0V 3.35 V 3.4V ≤ VBIAS ≤ 30V 3.35 V VVCC-UVLO_R VCC UVLO rising threshold VCC rising undervoltage threshold, IVCC = 0A 3.5 V V VCC-UVLO_H VCC UVLO hysteresis Hysteresis below VVCC-UVLO_R 0.9 V VOLTAGE REFERENCE (FB PIN) VFB Internal feedback reference voltage FPWM Mode 0.8 V FIXED OUTPUT VOLTAGE (BIAS PIN) VOUT(3.3V) 3.3V fixed output voltage FB shorted to GND 3.3 V VOUT(5V) 5.0V fixed output voltage FB shorted to VCC 5 V TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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6.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, fSW = 2.2MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STARTUP (SS PIN) tEN_HIGH Enable HIGH to start of switching delay VFB = VRT = VMODE = GND, VBIAS = VOUT 3 ms tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% of set point 5.3 ms CURRENT LIMITS AND HICCUP IHS-LIM High Side Peak Current Limit, 3A version (TPSM65630) Duty-cycle approaches 0%. 4.8 A ILS-LIM Low side valley current limit, 3A version (TPSM65630) Valley current limit on LS FET 3.9 A IL-PEAK-MIN Minimum peak inductor current at minimum duty cycle, 3A version (TPSM65630) VVCC = 3.3V, tpulse ≤ 100ns, Auto Mode 1.2 A IL-PEAK-MAX Minimum peak inductor current at maximum duty cycle, 3A version (TPSM65630) VVCC = 3.3V, tpulse ≥ 1µs, Auto Mode 0.48 A ILS-NEG-LIM Low side negative current limit Sinking current limit on LS FET, FPWM Mode –4.3 A IL-ZC-LIM Zero-cross current limit VVCC = 3.3V, Auto Mode 45 mA VHIC Overcurrent hiccup threshold on FB Pin LS FET On-time > 165ns, Not during Soft- start 0.32 V tHIC_DLY Hiccup mode activation delay 64 cycles tHIC Hiccup mode duration time 45 ms POWER GOOD (PG PIN) VPG-OVP-R PG overvoltage rising threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 105 % VPG-OVP-F PG overvoltage falling threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 104 % VPG-UVP-R PG undervoltage rising threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 96 % VPG-UVP-F PG undervoltage falling threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 95 % tPG-DEGLITCH-F Deglitch filter delay on PG falling edge 120 µs tPG-DEGLITCH-R Deglitch filter delay on PG rising edge 2 ms RON-PG PGOOD ON resistance IPG = 1mA 40 Ω DUAL RANDOM SPREAD SPECTRUM ΔfSS1-LF Low-frequency triangular spread spectrum modulation range - standard 8.5 % ΔfSS2-LF Low-frequency triangular spread spectrum modulation range - extended 17 % fm1-LF Triangular modulation frequency - standard 12 kHz fm2-LF Triangular modulation frequency - extended 6 kHz ΔfSS-HF High-frequency pseudo-random spread spectrum modulation range 2.0 % THERMAL SHUTDOWN TSD Thermal Shutdown(1) Shutdown threshold 155 165 177 ºC Recovery threshold 156 ºC (1) Specified by design. www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM65630 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The TPSM656x0 is an easy-to-use, high-power density, synchronous buck DC-DC power module that operates from a 3V to 65V (70V tolerant) supply voltage. The TPSM656x0 has pin selectable fixed output voltages of 3.3V, 5V, or adjustable output configuration. With an integrated power controller, inductor, MOSFETs, and other necessary components, the TPSM656x0 delivers up to 3A, 2A, 1A DC load current with high efficiency and low input quiescent current in a very small design size. Although designed for simple implementation, this device offers flexibility to optimize the usage according to the target application. The current-mode control architecture, with 30ns minimum on-time, allows high conversion ratios at high frequencies, fast transient response, and excellent load and line regulation. If the minimum on-time or minimum off-time does not support the desired conversion ratio, the switching frequency is automatically reduced. This feature allows regulation to be maintained during wide VIN variations. This device is designed to minimize end-product cost and size while operating in high-performance industrial environments. The TPSM656x0 can be set to operate at fixed 400kHz, fixed 2.2MHz, or in adjustable mode from 300kHz to 2.2MHz by using the RT pin. An integrated compensation network combined with an accurate current limit scheme minimizes bill of material cost and component count. The TPSM656x0 has been designed for low EMI. The device includes the following:

• Mode pin-configurable ±5% or ±10% dual random spread spectrum (DRSS) frequency hopping
• Symmetrical pin out minimizing parasitic package inductance
• Operation over a frequency range above and below AM radio band
• Pin-configurable for AUTO or FPWM mode along with external clock synchronization capabilities These features can eliminate shielding and other expensive EMI mitigation measures. The TPSM656x0 also includes protection features for robust system requirements:
• An open-drain PGOOD indicator for power-rail sequencing and fault reporting
• Precision enable input with hysteresis, providing: – Programmable line undervoltage lockout (UVLO) – Remote ON and OFF capability
• Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
• Thermal shutdown with automatic recovery. To use the device in reliability-conscious environments, the TPSM656x0 has a package with enlarged corner terminals for improved board level reliability and wettable flanks, allowing optical inspection. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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7.2 Functional Block Diagram

Comparators, De-glitch Filters, and Logic FB MODE / SYNC PGND2 PGND1 VOUT VIN1 BOOT HS and LS Current Control Internal EA HS Current Sense SLOPE COMP RAMP VCCBIAS PWM Comparator CLK Frequency Foldback TSD CLK Soft Start System EN LS ILIM EN / UVLO LS Current Comparator LS Current Sense UVP / OVP RT SW PLL and OSCILLATOR MODE / SYNC Detect LDO VIN2 VCC UVLO OVLO HS UVLO SPREAD SPECTRUM CLKOUT Drivers and Logic FB Decoder 3.3V, 5V ADJ BIAS Bandgap System EN VIN UVLO RRT Detect ZX Current Comparator VREF EN UVLO EN Control System EN 4.2µH www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSM65630 ADVANCE INFORMATION

7.3 Feature Descriptions

7.3.1 Output Voltage Selection

The TPSM656x0 features pin-selectable fixed output voltage or adjustable output voltage mode. In fixed output voltage mode, the output voltage is selected by the FB pin. Connect the FB pin to GND to select the fixed 3.3V output, or connect to VCC for a fixed 5V output. When the fixed output voltage mode is selected, the BIAS pin is connected directly to VOUT. In this mode, the BIAS pin closes the feedback loop of the regulator and provides input power to the internal bias regulator. Because of the internal LDO is supplied through this pin, a reliable bode plot cannot be taken in fixed output voltage mode however this measurement can be take in adjustable mode. Connect BIAS to VOUT as shown in Figure 8-1. Table 7-1. Output Voltage Selection FB VOUT Short to GND 3.3V Short to VCC 5V Connect to a feedback resistor divider (Figure 7-1) ADJ In the adjustable output voltage mode, a voltage divider is connected between the regulator output voltage and the FB pin. The resistor values are calculated based on the desired output voltage and the 0.8V reference of the regulator. See Figure 7-1 for detailed connections. RFBT RFBB FB AGND VOUT CFF Figure 7-1. Setting Output Voltage of Adjustable Versions Use Equation 1 to select a value for RFBB, based on a desired value of RFBT. Limiting the value of RFBT to 100kΩ or less is best practice. Larger values of resistance are susceptible to leakage currents on the PCB, caused by environmental contamination, that can shift the desired output voltage. Values up to about 1M Ω can be used to reduce the no-load supply current, in those cases where excessive PCB leakage currents are not present. R FBB = R FBT × 0.8 V O UT − 0.8 (1) In some cases, when using the adjustable mode, a feed forward capacitor can be used to improve the loop phase margin or load transient response. The exact value of C FF is best selected empirically during the initial bench evaluation of the design. Leave a placeholder for this capacitor in the PCB layout if needed at some stage during development.

7.3.2 EN Pin and Use as VIN UVLO

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use of an external voltage divider to provide an adjustable input Undervoltage Lockout (UVLO), if desired. Applying a voltage greater than V EN_TH_R fully enables the device, allowing the device to enter start-up mode and begin the soft-start period. When the EN input is brought below V EN_TH_F, the regulator stops switching and enters shutdown mode, with a VIN input current of less than 0.81 μA (Max). Note that the EN input draws a current of about 0.2μA (typical). The EN input can be connected directly to VIN if this feature is not needed. The enable TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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must not float, as floating the enable pin turns the device off. The values for the various EN thresholds can be found in the Electrical Characteristics table. RENT RENB EN VIN Figure 7-2. VIN UVLO Using the EN Pin In some cases, an input UVLO level different than that provided internal to the device is needed. This feature can be used for special sequencing or to prevent input voltage oscillations caused by excessively long power cables. External UVLO can be accomplished by using the circuit shown in Figure 7-2. The input voltage at which the device turns on is designated as V ON while the turn-off voltage is V OFF. The current in the divider must be greater than the current into the EN input (I EN_LKG), to preserve accuracy. Values for R ENB between 10k Ω and 50kΩ are reasonable. Then, Equation 2 is used to calculate RENT and Equation 3 is used to calculate VOFF. R ENT = R EN B × V O N V EN _ TH _R − 1 (2) V OFF = V O N × V EN _ T H_F V EN _ TH_R (3) where

• VON = VIN turn-on voltage
• VOFF = VIN turn-off voltage

7.3.3 Mode Selection

The MODE / SYNC pin is a multifunction pin that configures the mode of operation, and serves as an input for an external synchronization signal. If the pin is grounded or driven to logic low, the converter operates in auto mode. If the pin is tied to VCC or driven to logic high, or synchronized to an external clock source, the converter operates in FPWM mode. Table 7-2. Mode Selection MODE/SYNC MODE DYNAMIC MODE CHANGE SPREAD SPECTRUM Short to GND or driven low AUTO Enabled Standard ±5% DRSS 49.9kΩ to GND FPWM Disabled Wide ±10% DRSS 149.9kΩ to GND AUTO Disabled Wide ±10% DRSS Short to VCC or driven high FPWM Enabled Standard ±5% DRSS Synchronizing Signal FPWM Enabled Disabled Transitioning the device from auto to FPWM mode requires driving the pin from low to high or sending a synchronization signal. Transitioning the device from FPWM to auto mode requires driving the pin from high to low or stop sending the synchronization signal. Note that a short to ground or a pullup to VCC requires < 200 Ω resistor. www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM65630 ADVANCE INFORMATION

7.3.3.1 MODE/SYNC Pin Uses for Synchronization

The TPSM656x0 MODE/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by coupling a positive edge into the pin. The coupled edge voltage at the pin must exceed the SYNC amplitude threshold of V IH(SYNC) to trip the internal synchronization pulse detector. The minimum SYNC ON pulse and OFF pulse durations must be longer than t SYNC(TON-MIN) and tSYNC(TOFF-MIN) respectively. The TPSM656x0 switching action can be synchronized to an external clock from 300kHz to 2.2MHz. Note, an external SYNC signal can only be applied before or after pin detection. If applied during the pin detection, the SYNC signal can not be detected. MODE/SYNCClock Range Figure 7-3. Typical Implementation Allowing Synchronization Using the MODE/SYNC Pin VIH(MODE/ CLKIN) tCLKIN(TOFF) tCLKIN(TON) t VIL(MODE/ CLKIN) This figure shows the conditions needed for detection of a synchronization signal. Figure 7-4. Typical SYNC Waveform

7.3.3.2 Clock Locking

After a valid synchronization signal is detected, a clock locking procedure is initiated. After approximately 2048 pulses, the clock frequency locks to the frequency of the synchronization signal. While the switching frequency adjusts, phase is maintained so that the clock cycle lying between the operation at the default and synchronization frequencies is of intermediate length. There are no very long or very short pulses. After frequency is adjusted, phase is adjusted over a few tens of cycles so that the rising synchronization edges correspond with the rising SW node pulses. See the following figure. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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VIH(SYNC) VIL(SYNC) Pulse 1 Pulse 2 Pulse 3 Pulse 4 Phase lock achieved, Rising edges align to within approximately 45ns, no spread spectrum VIN GND Pulse 2048 Pulse 2049 Pulse 2050 Pulse 2051 SW Node Synchronization signal Spread Spectrum is on between pulse 1 and pulse 2048, there is no change to the operating frequency. At pulse 4, the device transitions from Auto to FPWM mode. At approximately pulse 2048, spread spectrum turns off Also clock frequency matches the synchronization signal and phase locking begins On the fourth pulse, the synchronization signal is detected. After approximately 2048 pulses, the synchronization signal is ready to synchronize, and the frequency is adjusted using a glitch-free technique, then the phase is locked. Figure 7-5. Synchronization Process

7.3.4 Adjustable Switching Frequency

The RT pin is configurable. This pin can be tied to VCC for 400kHz operation, grounded for 2.2MHz operation, or a resistor to GND can be used to set an adjustable operating frequency; see Table 7-3. Note that if a resistor value falls outside of the recommended range, the TPSM656x0 reverts to 400kHz or 2.2MHz. Do not apply a pulsed signal to this pin to force synchronization. If synchronization is needed, see the SYNC/MODE pin in Section 7.3.3.1. The switching frequency can be programmed in the range of 300kHz to 2200kHz by placing a resistor from the RT pin to GND. See Equation 4 and Figure 7-6. R T k Ω = 16.4 F SW MHz − 0.633 (4) For example, for fSW = 400kHz, RT = 40.37kΩ so a 40.2kΩ resistor can be selected as the closest value. Switching Frequency (MHz) RT (kΩ) Figure 7-6. Switching Frequency vs RT Table 7-3. Switching Frequency Settings RT SWITCHING FREQUENCY VCC 400kHz GND 2200kHz RT resistor to GND 300kHz to 2200kHz Float Do not float Note that a short to ground or a pullup to VCC requires < 200Ω resistor.

7.3.5 Dual Random Spread Spectrum (DRSS)

The TPSM656x0 provides a Dual Random Spread Spectrum (DRSS) function, which reduces the EMI of the power supply over a wide-frequency range. The DRSS function combines a low-frequency triangular modulation profile (standard or wide) with a high-frequency cycle-by-cycle pseudo-random modulation profile. The low www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM65630 ADVANCE INFORMATION

frequency triangular modulation improves performance in the lower radio frequency bands, while the high frequency random modulation improves performance in the higher radio frequency bands. The low frequency triangular modulation profiles are pin-selectable. The standard low-frequency modulation profile spreads the switching frequency by ±5% with a 12kHz modulation frequency while the wide low frequency modulation profile spreads the switching frequency by ±10% with a 6kHz modulation frequency. Spread spectrum works by converting a narrowband signal into a wideband signal which spreads the energy over multiple frequencies. Industry standards require different spectrum analyzer resolution bandwidth (RBW) settings for different frequency bands. The RBW has an impact on the spread spectrum performance. For example, the CISPR-25 requires 9kHz RBW for the 150kHz to 30MHz frequency band. For frequencies greater than 30MHz, the required RBW is 120kHz. DRSS is able to simultaneously improve the EMI performance in the high and low RBWs with the low frequency triangular modulation and high-frequency cycle-by-cycle pseudo-random modulation. In the low-frequency band (150kHz – 30MHz), the DRSS function can reduce the conducted emissions by as much as 15dBμV, and in the high-frequency band (30MHz – 108MHz) by as much as 5dBμV. The DRSS function is disabled when an external clock is applied to the MODE / SYNC / pin. Time Clock Frequency DRSS Low RBWHigh RBW Figure 7-7. Dual Random Spread Spectrum Implementation

7.3.6 Internal LDO, VCC UVLO, and BIAS Input

The TPSM656x0 has a dual input for the VCC regulator that is supplied from either VIN or BIAS. After the TPSM656x0 is active, power comes from VIN if BIAS is less than approximately 3.1V. However, power comes from BIAS if BIAS is more than 3.2V (maximum). VCC is typically 3.3V under most conditions, but can be lower if VIN is very low. To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See VCC-UVLO_R and VCC-UVLO_HYST in Electrical Characteristics.

7.3.7 Bootstrap Voltage (BST Pin)

The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The capacitor internally connected between BST and SW works as a charge pump to boost voltage on the BST terminal to (SW + VCC). The boot diode is integrated on the TPSM656x0 die to minimize the physical design size.

7.3.8 Soft Start and Recovery From Dropout

When designing with the TPSM656x0, slower rise in output voltage due to recovery from dropout and soft start must be considered separate phenomena. Soft start is triggered by any of the following conditions:

• EN is used to turn on the device.
• Recovery from a hiccup waiting period; see Section 7.3.9.3.
• Recovery from shutdown due to overtemperature protection.
• Power is applied to the VIN of the IC or the VCC UVLO is released. After soft start is initiated, the IC takes the following actions:
• The reference used by the IC to regulate output voltage is slowly ramping up from zero. The net result is that output voltage, if previously 0V, takes tSS to reach 90% of regulation value. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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• Operating mode is set to auto, activating diode emulation. This allows start-up without pulling the output voltage low if there is a voltage already present on the output.
• Hiccup is disabled for the duration of soft start; see Section 7.3.9.3. All of these actions together provide a controlled start-up with limited inrush current. These actions also allow the use of output capacitors and loading conditions that can cause current limit during start-up without triggering hiccup. In addition, if the output voltage is already present the output voltage does not discharge. Any time the output voltage is more than a few percent low for any reason, the output voltage ramps back up slowly. This is the recovery from dropout condition which differs from soft start in three important ways:
• Hiccup is allowed only if output voltage is less than 40 percent the set point. Note that during dropout
• FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by an external supply, the TPSM656x0 can pull down on the output. Note that all the protections that are present during normal operation are in place, protecting the device if output is shorted to a high voltage or ground.
• The reference voltage is set to approximately 1% above that needed to achieve the current output voltage. The reference voltage is not started from zero. Despite the name, recovery from dropout is active whenever output voltage is more than a few percent lower than the setpoint for long enough that:
• Duty factor is controlled by minimum on-time or
• When the part is operating in current limit. This action primarily occurs under the following conditions:
• Dropout: When there is insufficient input voltage for the desired output voltage to be generated.
• Overcurrent that is not severe enough to trigger hiccup or if the duration is too short to trigger hiccup. See Section 7.3.9.3. Load current VOUT Set Point and max output current Output Voltage and Current Slope the same as during soft start Time t VOUT V Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall below the setpoint is removed, output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, hiccup can, in principal, be triggered during recovery if output voltage is below 0.4 times output the setpoint for more than 128 clock cycles during recovery. Figure 7-8. Recovery From Dropout

7.3.9 Safety Features

The TPSM656x0 includes a set of safety features:

• Power-Good monitor with output undervoltage (UV) and overvoltage (OV) protection
• Overcurrent and short-circuit protection with HICCUP mode
• Thermal shutdown (TSD)

7.3.9.1 Power-Good Monitor

The TPSM656x0 includes a power-good function to simplify supply sequencing and supervision in a system. The power good function can be used to enable downstream circuits that are supplied by the TPSM656x0, control downstream protection circuits such as load switches, or to turn on sequenced supplies. The function monitors www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM65630 ADVANCE INFORMATION

the output voltage with a window comparator through the FB pin for adjustable V OUT configurations and the BIAS pin for fixed V OUT configurations. The power-good output (PG) switches to a high impedance open-drain state when the output voltage is in regulation. When the output voltage is outside of the ±5% range from the set voltage, the PG pin is driven low (< V OL(PG)) warning the system of an output over-voltage or undervoltage condition. A 114µs deglitch filter on the PG falling edge prevents false tripping of the power-good signals during transients. When the output voltage returns within the regulation window, a 2ms filter on the PG rising edge allows extra processing time for the downstream components. TI recommends a100k Ω pullup resistor from the PG pin to the relevant logic rail not greater than 30V. PG is asserted low during soft start and when the TPSM656x0 is disabled.

7.3.9.2 Overcurrent and Short-Circuit Protection

The TPSM656x0 is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side and the low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to the minimum of a fixed current setpoint, or the output of the voltage regulation loop minus slope compensation, every switching cycle. Because the voltage loop has a maximum value and slope compensation increases with duty cycle, the HS current limit decreases with increased duty cycle if duty cycle is above 35%. When the LS switch is turned on, the current going through is also sensed and monitored. Like the high-side MOSFET, the low-side MOSFET turn-off is commanded by the voltage control loop. For a low-side device, turn-off is prevented if the current limit is exceeded, even if the oscillator normally starts a new switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This limit is called the low-side current limit; see the Electrical Characteristics for values. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not turned on. The LS switch is turned off after the LS current falls below the limit. The HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. iL VSW IL-LS Inductor Current t t SW Voltage VIN Typically, tSW > Clock setting tON < tON_MAX IL-HS IOUT Figure 7-9. Current Limit Waveforms The net effect of the operation of high-side and low-side current limit is that the IC operates in hysteretic control. Because the current waveform assumes values between I L-HS and I L-LS, output current is close to the average of these two values unless duty cycle is very high. After operating in current limit, hysteretic control is used and current does not increase as output voltage approaches zero. After the overload condition is removed, the device recovers as though in soft start; see Section 7.3.8. Note that hiccup can be triggered if output voltage drops below approximately 0.4 times the intended output voltage. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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7.3.9.3 Hiccup

The TPSM656x0 employs hiccup overcurrent protection when all of the following conditions are met for 128 consecutive switching cycles:

• A time greater than tSS has passed since soft start has started; see Section 7.3.8.
• Output voltage is below approximately 0.4 times output setpoint.
• The part is not operating in dropout defined as having minimum off-time controlled by duty factor. In hiccup mode, the device shuts down and attempts to soft start after t HIC. Hiccup mode helps reduce the device power dissipation under severe overcurrent and short circuit conditions.

7.3.9.4 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the IC junction temperature exceeds 165°C (typical) and power-good (PG) asserts. Thermal shutdown does not trigger below 155°C. After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 156°C. When the junction temperature falls below 156°C (typical), the TPSM656x0 attempts to soft start.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on and off control of the device. When the EN pin voltage is below 0.9V, both the regulator and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode, the quiescent current drops below 0.81µA.

7.4.2 Active Mode

The TPSM656x0 is in active mode when the following occurs:

• The EN pin is above VEN_TH_R.
• VIN is above VIN_UVLO_R.
• VIN is high enough to satisfy the VIN minimum operating input voltage.
• No other fault conditions are present. See Section 7.3 for protection features. The simplest way to enable the operation is to connect EN to VIN, allowing self-start-up when the applied input voltage exceeds the minimum VIN_OPERATE. In active mode, depending on the load current, input voltage, and output voltage, the TPSM656x0 is in one of six sub-modes:
• Continuous conduction mode (CCM) with fixed switching frequency and peak current mode operation
• Discontinuous conduction mode (DCM) while in auto mode when the load current is lower than half of the inductor current ripple. If current continues to reduce, the device enters Pulse Frequency Modulation (PFM) which reduces the switch frequency to maintain regulation while reducing switching losses to achieve higher efficiency at light load.
• Minimum on-time operation while the on-time of the device needed for full-frequency operation at the requested low-duty cycle is not supported by TON_MIN
• Forced pulse width modulation (FPWM) similar to CCM with fixed-switching frequency, but extends the fixed frequency range of operation from full to no load
• A current limiting condition where the output voltage remains above 0.4 times the output setpoint
• Dropout mode when switching frequency is reduced to minimize dropout
• Recovery from dropout similar to other modes of operation except the output voltage setpoint is gradually moved up until the programmed setpoint is reached.

7.4.2.1 Peak Current Mode Operation

The following operating description of the TPSM656x0 refers to Section 7.2 and the waveforms in Figure 7-10. Both supply a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW terminal voltage, V SW, swings up to approximately VIN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM65630 ADVANCE INFORMATION

control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, forcing V SW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over the switching period: D = TON / (TON + TOFF). In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. iL VSW ILPK IOUT Iripple Inductor Current - IOUT×RDSLS D = t t SW Voltage tON tSWVIN tSW tON tOFF VOUT VIN Figure 7-10. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM) To get accurate DC load regulation, a voltage feedback loop is used. Peak and valley inductor currents are sensed for peak current mode control and current protection. The regulator operates with continuous conduction mode with constant switching frequency when load level is above one half of the minimum peak inductor current. The internally-compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.

7.4.2.2 Auto Mode Operation

The TPSM656x0 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows a seamless transition between normal current mode operation while heavily loaded and in highly-efficient light-load operation. The other behavior, known as FPWM mode, maintains full frequency even when unloaded. Which mode the TPSM656x0 operates in depends on the SYNC/MODE pin. When SYNC/MODE is high, the part is in FPWM. When SYNC/MODE is low, the part is in PFM. In auto mode, light-load operation is employed in the TPSM656x0 at load lower than approximately 1/10th of the rated maximum output current. Light-load operation employs two techniques to improve efficiency:

• Diode emulation, which allows DCM operation
• Frequency foldback Note that while these two features operate together to create excellent light load behavior, these features operate independently of each other.

7.4.2.2.1 Diode Emulation

Diode emulation prevents reverse current though the inductor, which requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. Frequency is reduced when peak inductor current goes below I PEAK-MIN. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN In auto mode, the low-side device is turned off after inductor current is near zero. As a result, after output current is less than half of inductor ripple in CCM, the part operates in DCM. This action is equivalent to saying that diode emulation is active. Figure 7-11. PFM Operation The TPSM656x0 has a minimum peak inductor current setting in auto mode. That being said, when current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting frequency. This mode of operation is called PFM mode regulation.

7.4.2.3 FPWM Mode Operation

Like auto mode operation, FPWM mode operation during light-load operation is selected using the SYNC/MODE pin. In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See the Electrical Characteristics for reverse current limit values. iL VSW ILPK IOUT Iripple Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN FPWM mode Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 7-12. FPWM Mode Operation In FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on-time, even while lightly loaded. This allows good behavior during faults which involves the output being pulled up. www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM65630 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPSM656x0 step-down DC-to-DC module is typically used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 1A, 2A, or 3A. The following design procedure can be used to select components for the TPSM656x0. Note All of the capacitance values given in the following application information refer to effective values unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under DC bias, the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This action can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to make sure that the minimum value of effective capacitance is provided. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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8.2 Typical Application

Figure 8-1 shows a typical application circuit for the TPSM656x0, when using the adjustable output mode or the fixed output mode, respectively. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is designed for a certain range of external inductance and output capacitance. VIN EN VCC SW BOOT FB VOUT COUT CIN CVCC 2 × 4.7µF 1µF RT TPSM656x0CHF RFBT RFBB CFF GND PG MODE BIASConnect as required 2 × 100nF VOUT 0 Ω 0.1µF Figure 8-1. Example Application Circuit for Adjustable Output Voltage Mode With TPSM656x0

8.2.1 Design Requirements

The following example provides a detailed design procedure based on the specifications found in Table 8-1. Table 8-1. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 24V (typical) Output voltage 5V Maximum output current 0A to 3A Switching frequency 400kHz

8.2.2 Detailed Design Procedure

The following design procedure applies to Figure 8-1 and Table 8-1.

8.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall design size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more compact design. For this application example, select a frequency of 400kHz. In this case, the RT pin is connected to the VCC pin. See also Section 7.3.4. www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM65630 ADVANCE INFORMATION

8.2.2.2 FB for Adjustable or Fixed Output Voltage Mode

This example uses the adjustable output voltage mode. An external voltage divider must be connected between the output node and the FB pin, while Equation 5 and Equation 6 are used to determine the divider values. R FBB = R FBT × 0.8 V O UT − 0.8 (5) 100 k Ω ≥ R FBB R F BT ≥ 4 k Ω (6) Note that Equation 6 states that the parallel combination of R FBB and R FBT must be greater than 4k Ω and less than 100kΩ. This limit is required because the regulator must reliably detect the sate of the FB pin during the start-up sequence to set the output voltage mode correctly. Since adjustable output voltage mode was chosen for this example, the values of R FBT = 205k Ω and R FBB = 39kΩ satisfy both Equation 5 and Equation 6. See also Section 7.3.1.

8.2.2.3 Output Capacitor Selection

The current mode control scheme of the TPSM656x0 device allows operation over a wide range of output capacitances. The output capacitor bank is usually limited by the load transient requirements and stability rather than the output voltage ripple. In general, higher output voltages and higher switching frequencies require less output capacitance. In addition, when using the adjustable output voltage mode, the C FF capacitor can be used to optimize the loop performance. In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load transient testing and Bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1nF to 100nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics. The maximum output capacitance must be limited to approximately 10 times the design value, or 1000µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed. This example uses an output capacitance of 70 μF. Keep in mind that this represents the value after applying D.C. bias derating and any other applicable tolerance in the capacitance. This is true for all the values shown in the tables. Any ceramic capacitor, or combination of capacitors, with an X7R or better dielectric, that provides 70μF at 5V bias, can be used. The values shown in the table must be considered as typical to provide a stable design. Maximum and minimum limits on the output capacitance can be found by testing the application, as mentioned above.

8.2.2.4 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2 × 4.7µF is required on the input of the regulator. Place one capacitor on each side of the package and connected directly to the VIN and GND pins of the device. This capacitance must be rated for at least the maximum input voltage that the application requires, preferably twice the maximum input voltage. The value can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. In addition, a high frequency bypass capacitance of 2 × 100nF ceramic capacitor must be used at the input, as close a possible to the regulator. Place one capacitor on each side of the package and connected directly to the VIN and GND pins of the device. This requirement provides a high frequency bypass for the control circuits internal to the device. For this example, 2 × 4.7µF, 100V, X7R (or better) ceramic capacitors are chosen. The 100nF capacitors must also be rated at 100V with an X7R dielectric. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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Using an electrolytic capacitor on the input in parallel with the ceramics is often desirable. This statement is especially true if long leads or traces are used to connect the input supply to the regulator, or an input EMI filter is used. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by any inductance on the input. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

8.2.2.5 CBOOT

The TPSM656x0 has an internal bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor stores energy that is used to supply the high-side gate driver for the power MOSFET, along with other critical control circuits.

8.2.2.6 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This need can be accomplished by using the circuit shown in Figure 8-2. The turn-on voltage is designated as V ON while the turn-off voltage is V OFF. First, a value for R ENB is chosen in the range of 10k Ω to 100k Ω, then use Equation 7 and Equation 8 to calculate RENT and VOFF. EN RENT RENB VIN Figure 8-2. Setup for External UVLO Application R ENT = R ENB × V O N V E N − H − 1 (7) V OFF = V EN − L × V ON V EN − H (8) where

• VON = VIN turn-on voltage
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8.3 Best Design Practices

• Do not exceed the Absolute Maximum Ratings
• Do not exceed the Recommended Operating Conditions.
• Do not exceed the ESD Ratings.
• Do not allow the EN input to float.
• Do not allow the output voltage to exceed the input voltage, nor go below ground.
• Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique design and PCB layout to help make the project a success.

8.4 Power Supply Recommendations

The characteristics of the input supply must be capable of delivering the required input current to the loaded regulator. Estimate the average input current with Equation 9. I IN = V IN V O UT × I O UT η (9) where η is the efficiency. If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can form an underdamped resonant circuit. This action can result in overvoltage transients at the input to the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A value in the range of 20µF to 100µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients. Sometimes, for other system considerations, an input filter is used in front of the regulator. This usage can lead to instability, as well as some of the effects mentioned above, unless designed carefully. The user's guide AN-2162 Simple Success With Conducted EMI From DCDC Converters provides helpful suggestions when designing an input filter for any switching regulator. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). TI does not recommend to use a device with this type of characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device. The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If this scenario is considered likely, then use a Schottky diode between the input supply and the output.

8.5 Layout

8.5.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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ground, as shown inFigure 8-3. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Section 8.5.2 shows a recommended layout for the critical components of the TPSM656x0 .

• Place the input capacitors as close as possible to the VIN pins and connect to ground through a short wide trace.
• Apply the symmetrical input capacitors technique as shown in the TPSM65630SEVM
• Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise sources (such as the SW node) that can capacitively couple into the feedback path of the regulator.
• Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a heat dissipation path.
• Connect the thermal pad to the ground plane. The B1QFN package has a thermal pad (PAD) connection that can be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application.
• Provide wide planes for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
• Provide enough PCB area for proper heat sinking. Enough copper area must be used to keep a low RθJA, commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce. With the B1QFN package, use heat-sinking vias from the thermal pad to the rest of the PCB ground layer to assist in heat dissipation. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes.
• Keep the switch area small. Do not add any connection to the switch pin. The total area of this node must be minimized to help reduce radiated EMI. See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies application note
• Simple Switcher PCB Layout Guidelines application note
• Construction Your Power Supply- Layout Considerations seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application note www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM65630 ADVANCE INFORMATION

Figure 8-3. Current Loops With Fast Edges

8.5.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. A ground plane also provides a quiet reference potential for the control circuitry. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise and must be used for sensitive routes. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2oz / 1oz / 1oz / 2oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and lower thermal resistance. TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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8.5.2 Layout Example

Figure 8-4. Layout Example www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPSM65630 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Thermal Design by Insight not Hindsight application note
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application note
• Texas Instruments, How to Properly Evaluate Junction Temperature with Thermal Metrics application note
• Texas Instruments, Layout Guidelines for Switching Power Supplies application note
• Texas Instruments, Simple Switcher PCB Layout Guidelines application note
• Texas Instruments, Construction Your Power Supply- Layout Considerations seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES July 2025 * Initial Release TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPSM65630SVCG QFN- FCMOD VCG 19 1000 330 100 5.5 6.10 3.3 12 16 4 www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPSM65630 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSM65630SVCG QFN-FCMOD VCG 19 1000 336.6 336.6 31.8 TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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www.ti.com B1QFN - 3.14 mm max heightPLASTIC QUAD FLATPACK-NO LEADVCG0019AA 0.08C B 5.35.1 5.95.7PIN 1 INDEX AREA SEATING PLANEC 1PIN 1 ID 0.1CAB0.05C 2.8±0.1 3 9 1116171811X 0.60.410 0.010 (0.13)DETAIL ATYPICAL DETAIL A 0.1CAB0.05C 2X 0.82X 0.3 3.142.72 www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPSM65630 ADVANCE INFORMATION

www.ti.com B1QFN - 3.14 mm max heightVCG0019APLASTIC QUAD FLATPACK-NO LEAD LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 12X0.05 MAXALL AROUNDMETALSOLDER MASKOPENING 0.05 MINALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKNON- SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINEDEXPOSEDMETALSOLDER MASK DETAILSNOT TO SCALE EXPOSEDMETAL (0.325) TYP 2X (1.4)(Ø0.2) VIATYP(R0.05) TYP(2.8) 3 9 16 11 (2.45)2X (2.8) 5X (2.8)2X (3.1) 2X (3.1) 104X (0.368) 11X (0.25) 3X (0.25) 2X (0.8)2X (0.3) TPSM65630 SNVSCU1 – JULY 2025 www.ti.com

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NOTES: (continued)5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4230382/E 07/2024 www.ti.com B1QFN - 3.14 mm max heightVCG0019APLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCILSCALE: 12X 3X (0.2) 2X (1.3)(R0.05) TYP 2X (1.23) 3 9 16 11 (2.45)2X (2.8) 2X (2.8)2X (3.1) 2X (3.1) 104X (0.368) 11X (0.25) 3X (0.25) 2X (0.8)2X (0.3) www.ti.com TPSM65630 SNVSCU1 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPSM65630 ADVANCE INFORMATION

www.ti.com 4-Sep-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) P65630SVCGR Active Preproduction QFN-FCMOD (VCG) | 19 1500 | LARGE T&R - Call TI Call TI -40 to 150 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4230382/H 09/2025 www.ti.com B1QFN - 3.14 mm max height PLASTIC QUAD FLATPACK-NO LEAD VCG0019A A 0.08 C B 5.3 5.1 5.9 5.7PIN 1 INDEX AREA SEATING PLANE C PIN 1 ID

0.1 C A B

0.05 C 0.95 0.65 0.65 0.95 2X 2.588 2X 2.588

0000 PKG ℄

2X 2.1 2X 1.3 2X 0.7 2X 2.1

0.000 PKG ℄

2X 0.1 2.8±0.1 2X 1.4±0.1 4X 0.55 0.45 (0.15) TYP 11X 0.3 0.2 (0.12) TYP 0.65±0.1 4X 0.42 0.32 2X 1.5±0.1 3 9 1116 0.01 (0.13) DETAIL A TYPICAL DETAIL A 0.05 C 2X 0.8 2X 0.3 3.14 2.72 1.23 1.811 0.25 0.15 0.4 0.3 (0.73) (4) (4.2) (0.5) 11X 0.6 0.4

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4230382/H 09/2025 www.ti.com B1QFN - 3.14 mm max heightVCG0019A PLASTIC QUAD FLATPACK-NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X

0.05 MAX

0.05 MIN

(PREFERRED) SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL (2.75) 2X (2.588) (0.95) 2X (0.65) 2X (0.65) (0.95) 2X (2.588) (2.75) (2.15) 2X (2.1) 2X (1.3) 2X (0.1) 2X (0.2) 2X (0.7) 2X (2.1) 4X (0.825) 8X (0.25) 3X (0.325) (0.975) 2X (1.5) 2X (1.4)(Ø0.2) VIA TYP (R0.05) TYP (2.8) 3 9 5X (2.8) 5X (2.8) 2X (3.1) 2X (3.1) 6X (0.25) 2X (0.8) 2X (0.3) (0.35)2X (0.2) (1.811) (1.23) (2.45)

NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4230382/H 09/2025 www.ti.com B1QFN - 3.14 mm max heightVCG0019A PLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 12X 1(2.75) 2X (2.588) (0.95) (0.65) (0.65) (0.95) 2X (2.588) (2.75) 2X (2.15) 2X (2.1) 2X (1.3) 2X (0.1) 2X (0.2) 2X (0.7) 2X (2.1) 4X (0.825) 8X (0.25) 6X (0.2) 2X (0.635) 2X (1.38) 2X (1.3) (R0.05) TYP 2X (1.23) 3 9 (0.715) (0.715) (2.7) 2X (2.8) 2X (2.8) 2X (3.1) 2X (3.1) 6X (0.25) 2X (0.8) 2X (0.3) (1.811) (1.23) (0.35)(0.2) (2.45)

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