P620-05OC

PLL620-05 ETC1

Document overview

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Technical content

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 1

FEATURES

100MHz to 200MHz Fundamental or 3rd Overtone Crystal. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 700MHz (4x multiplier), or 800MHz-1GHz(PLL620-09 only, 8x multiplier). CMOS (Standard drive PLL620-07 or Selectable Drive PLL620-06), PECL (Enable low PLL620-08 or Enable high PLL620-05) or LVDS output (PLL620-09). Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP.

DESCRIPTION

The PLL620-0x family of XO IC’s is specifically designed to work with high frequency fundamental and third overtone crystals. Their low jitter and low phase noise performance make them well suited for high frequency XO requirements. They achieve very low current into the crystal resulting in better overall stability. BLOCK DIAGRAM PIN CONFIGURATION (Top View) ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. OUTPUT ENABLE LOGICAL LEVELS Part # OE State (Default) Output enabled PLL620-08 Tri-state Tri-state PLL620-05 PLL620-06 PLL620-07 PLL620-09 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/- 07/-09 OE Q Q PLL by-pass SEL PLL (Phase Locked Loop) Oscillator Amplifier PLL 620-0x VDD XIN XOUT SEL3^ SEL2^ OE GND GND SEL0^ SEL1^ GND CLKC VDD CLKT GND GND PLL620-0x GND VDD CLKT CLKC DNC/ DRIVSEL* SEL0^ SEL1^ VDD XOUT XIN SEL2^ OE GND GND GND GND

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 2 PIN DESCRIPTIONS Name TSSOP* Pin number 3x3mm QFN* Pin number Type 1, 12 6,11 P +3.3V power supply. XIN I Crystal input. See Crystal Specification on page 3. XOUT I Crystal output. See Crystal Specification on page 3. OE I Output enable. GND 7,8,9, 10, 14 1,2,3,4,8 P Ground (except pin 12 on PLL620-06: DRIVSEL see below). DRIVSEL** I PLL620-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL620-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. The pin remains ‘Do Not Connect (DNC)’ for CLKT O True output PECL (PLL620-08) or LVDS (PLL620-09) (N/C for PLL620-07) CLKC O Complementary output PECL (PLL620-08) or LVDS (PLL620- 09) (CMOS out for PLL620-07). SEL0 I SEL1 I SEL2 I SEL3 Not available I Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. * Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier Fin x 8(PLL620-09 only) Fin x 4 Fin x 2 No multiplication Note: SEL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 3 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Fundamental or 3rd overtone* 100 200 MHz Crystal Loading Rating CL (xtal) pF Interelectrode Capacitance pF Recommended ESR RE AT cut Ω * Note: 3rd overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating. 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD PECL/LVDS/CMOS 100/80/40 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 4 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS 2.5 Period jitter peak-to-peak At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 ps Accumulated jitter RMS 2.5 Accumulated jitter peak-to-peak At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. ps Random Jitter “RJ” measured on Wavecrest SIA 3000 2.5 ps Integrated jitter RMS at 155MHz Integrated 12 kHz to 20 MHz 0.3 0.4 ps Period jitter RMS Period jitter peak-to-peak At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles ps Accumulated jitter RMS Accumulated jitter peak-to-peak At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. ps Random Jitter “RJ” measured on Wavecrest SIA 3000 ps Integrated jitter RMS at 622MHz Integrated 12 kHz to 20 MHz 1.6 1.8 ps 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz -75 -95 -125 -140 -145 Phase Noise relative to carrier 622.08MHz -75 -95 -110 -125 -120 dBc/Hz 6. CMOS Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V mA Output drive current (High Drive) IOL VOL = 0.4V, VDD = 3.3V mA IOH VOH= VDD-0.4V, VDD=3.3V mA Output drive current (Standard Drive) IOL VOL = 0.4V, VDD = 3.3V mA Output Clock Rise/Fall Time (Standard Drive) 0.3V ~ 3.0V with 15 pF load 2.4 Output Clock Rise/Fall Time (High Drive) 0.3V ~ 3.0V with 15 pF load 1.2 ns * Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12.

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 5 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 uA Output Short Circuit Current IOSD -5.7 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50Ω 50Ω OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 6 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.620 V 19. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns OUT OUT 50Ω 50Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V

Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 7

PACKAGE INFORMATION

C L A E H D e B

16 PIN TSSOP ( mm )

Min. Max. A 1.20 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 4.50 H

6.40 BSC

L 0.45 0.75 e

0.65 BSC

3mm x 3mm, QFN

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