P4H290MDYYTSEP

TLV4H290-SEP TI

Document overview

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Technical content

TLV4H290-SEP and TLV4H390-SEP Radiation-Tolerant High-Precision Quad Comparators in Space Enhanced Plastic

1 Features

• Radiation tolerant – Single Event Latch-up (SEL) immune to 43MeV·cm2 /mg at 125°C – ELDRS free to 30krad (Si) – Total Ionizing Dose (TID) RLAT for every wafer lot up to 30krad(Si) – TID characterized to 30krad (Si)
• Space enhanced plastic – –55°C to 125°C temperature range – Controlled baseline – Gold wire – NiPdAu Lead Finish – One fabrication, assembly, and test site – Extended product life cycle – Extended product change nofication – Product traceability – Enhanced mold compound for low outgassing
• 1.65V to 5.5V supply range
• Precision input offset voltage 300μV
• Power-on Reset (POR) for known start-up
• Rail-to-Rail input with fault-tolerance
• 100ns typical propagation delay
• Low quiescent current 25μA per channel
• 2kV ESD protection
• Open-drain output option (TLV4H290-SEP)
• Push-pull output option (TLV4H390-SEP)

2 Applications

• Support Low Earth Orbit Space Applications
• Satellite Electrical Power Systems
• Flight Control Unit
• Communications Payload

3 Description

The TLV4H290-SEP and TLV4H390-SEP are quad channel comparators which offer low input offset voltage, fault-tolerant inputs with an excellent speed- to-power combination with a propagation delay of 100ns. Operating voltage range of 1.65V to 5.5V with a quiescent supply current of 25μA per channel. This device family also includes a Power-on Reset (POR) feature that makes sure the output is in a known state until the minimum supply voltage has been reached and a small time period passed before the output starts responding to the inputs. This prevents output transients during system power-up and power-down. These comparators also feature no output phase inversion with fault-tolerant inputs that can go up to 6V without damage. The TLV4H290-SEP comparator has an open-drain output stage that can be pulled below or beyond the supply voltage, making it appropriate for level translation. The TLV4H390-SEP comparator has a push-pull output stage capable of both sinking and sourcing current. The TLV4H290-SEP and TLV4H390-SEP are available in a plastic 14-pin SOT-23 package with radiation tolerance up to 43MeV·cm2 /mg. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) (2) TLV4H290-SEP, TLV4H390-SEP SOT-23 (14) 4.2mm x 2.0mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. OUT IN+ IN- Bias Power-On-Reset (POR) SNAPBACK ESD CLAMPS V- V- Output Control Open Drain Output Block Diagram OUT IN+ IN- Bias Power-On-Reset (POR) SNAPBACK ESD CLAMPS V- V- Output Control V+ Push-Pull Output Block Diagram ADVANCE INFORMATION TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

4.1 Pin Functions:TLV4H290-SEP and TLV4H390-

10 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

4.1 Pin Functions:TLV4H290-SEP and TLV4H390-SEP Quad

IN1± IN1+ IN2± IN2+ OUT1 OUT2 IN4± IN3+ IN3± OUT4 OUT3 IN4+ Figure 4-1. DYY Package 14-Pin SOT-23 Top View Table 4-1. Pin Functions: TLV4H290-SEP and TLV4H390-SEP Quad PIN I/O DESCRIPTION NAME NO. OUT2 1 O Output pin of the comparator 2 OUT1 2 O Output pin of the comparator1 V+ 3 — Positive supply IN1– 4 I Negative input pin of the comparator 1 IN1+ 5 I Positive input pin of the comparator 1 IN2– 6 I Negative input pin of the comparator 2 IN2+ 7 I Positive input pin of the comparator 2 IN3– 8 I Negative input pin of the comparator 3 IN3+ 9 I Positive input pin of the comparator 3 IN4– 10 I Negative input pin of the comparator 4 IN4+ 11 I Positive input pin of the comparator 4 V– 12 — Negative supply OUT4 13 O Output pin of the comparator 4 OUT3 14 O Output pin of the comparator 3 www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) –0.3 6 V Input pins (IN+, IN–) from (V–)(2) –0.3 6 V Current into Input pins (IN+, IN–) –10 10 mA Output (OUT) from (V–), open-drain only(3) –0.3 6 V Output (OUT) from (V–), push-pull only –0.3 (V+) + 0.3 V Output short circuit duration(4) 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3V beyond the supply rails must be current-limited to 10mA or less. Additionally, Inputs (IN+, IN–) can be greater than (V+) and OUT as long as it is within the –0.3V to 6V range (3) Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as it is within the –0.3V to 6V range (4) Short-circuit to (V–) or (V+).

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) 1.65 5.5 V Input voltage range (IN+, IN–) from (V–) –0.3 5.5 V Ambient temperature, TA –40 125 °C

5.4 Thermal Information, Quad

THERMAL METRIC(1) TLV4H290- SEP, TLV4H390- SEP UNIT DYY (SOT23)

14 PINS

RqJA Junction-to-ambient thermal resistance 218.1 °C/W RqJC(top) Junction-to-case (top) thermal resistance 127.0 °C/W RqJB Junction-to-board thermal resistance 129.6 °C/W yJT Junction-to-top characterization parameter 24.7 °C/W yJB Junction-to-board characterization parameter 126.8 °C/W RqJC(bot) Junction-to-case (bottom) thermal resistance – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics appnote. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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5.5 Electrical Characteristics, Quad

For VS (Total Supply Voltage) = (V+) – (V–) = 5V, VCM = (V–) at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 1.8V and 5V –2.5 ±0.3 2.5 mV VOS Input offset voltage VS = 1.8V and 5V, TA = –55°C to +125°C –4 4 dVIO/dT Input offset voltage drift VS = 1.8V and 5V, TA = –55°C to +125°C ±0.5 µV/°C POWER SUPPLY IQ Quiescent current per comparator VS = 1.8V and 5V, No Load, Output Low 25 35 µA IQ Quiescent current per comparator VS = 1.8V and 5V, No Load, Output Low, TA = –55°C to +125°C 40 PSRR Power-supply rejection ratio VS = 1.8V to 5V, TA = –55°C to +125°C 95 dB INPUT BIAS CURRENT IB Input bias current VCM = VS/2 5 pA IOS Input offset current VCM = VS/2 1 pA INPUT CAPACITANCE CID Input Capacitance, Differential VCM = VS/2 2 pF CIC Input Capacitance, Common Mode VCM = VS/2 3 pF INPUT VOLTAGE RANGE VCM-Range Common-mode voltage range VS = 1.8V and 5V, TA = –55°C to +125°C (V–) (V+) V CMRR Common-mode rejection ratio VS = 5V, (V–) < VCM < (V+), TA = –55°C to +125°C 70 dB CMRR Common-mode rejection ratio VS = 1.8V, (V–) < VCM < (V+) , TA = –55°C to +125°C 60 dB OPEN-LOOP GAIN AVD Large signal differential voltage amplification For open-drain version only 200 V/mV OUTPUT VOL Voltage swing from (V–) ISINK = 4mA, TA = 25°C 75 125 mV VOL Voltage swing from (V–) ISINK = 4mA, TA = –55°C to +125°C 175 mV VOH Voltage swing from (V+) ISOURCE = 4mA, TA = 25°C (push-pull only) 75 125 mV VOH Voltage swing from (V+) ISOURCE = 4mA, TA = –55°C to +125°C (push-pull only) 175 mV ILKG Open-drain output leakage current VPULLUP = (V+), TA = 25°C (open drain only) 100 pA ISC Short-circuit current VS = 5V, Sinking 90 100 mA ISC Short-circuit current VS = 5V, Sourcing (push-pull only) 90 100 mA www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

5.6 Switching Characteristics, Quad

For VS (Total Supply Voltage) = (V+) – (V–) = 5V, VCM = VS / 2, CL = 15pF at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT TPD-HL Propagation delay time, high- to-low VID = –100mV; Delay from mid-point of input to mid-point of output (RP = 2.5KΩ for open drain only) 100 ns TPD-LH Propagation delay time, low-to- high VID = 100mV; Delay from mid-point of input to mid-point of output (for push-pull only) 115 ns TPD-LH Propagation delay time, low-to- high VID = 100mV; Delay from mid-point of input to mid-point of output (RP = 2.5KΩ for open drain only) 150 ns TFALL 5V Output Fall Time, 80% to 20% VID = –100mV 3 ns TRISE 5V Output Rise Time, 20% to 80% VID = 100mV, for push-pull only 3 ns FTOGGLE 5V, Toggle Frequency VID = 100mV (RP = 2.5KΩ for open drain only) 3 MHz POWER ON TIME PON Power on-time VS = 1.8V and 5V, VCM = (V–), VID = –0.1 V, VPULL-UP = VS / 2, Delay from VS / 2 to VOUT = 0.1 x VS / 2 (RP = 2.5KΩ for open drain only) 30 µs TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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5.7 Typical Characteristics

TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Supply Voltage (V) Supply Current Per Channel (PA) 125°C 85°C 25°C -40°C Figure 5-1. Supply Current vs. Supply Voltage Temperature (°C) Supply Current Per Channel (PA) -40 -25 -10 5 20 35 50 65 80 95 110 125 1.8V 3.3V 5V Figure 5-2. Supply Current vs. Temperature Input Voltage (V) Supply Current Per Channel (PA) VS=1.8V 125°C 85°C 25°C -40°C Figure 5-3. Supply Current vs. Input Voltage, 1.8V Input Voltage (V) Supply Current Per Channel (PA) VS=3.3V 125°C 85°C 25°C -40°C Figure 5-4. Supply Current vs. Input Voltage, 3.3V Input Voltage (V) Supply Current Per Channel (PA) 125°C 85°C 25°C -40°C Figure 5-5. Supply Current vs. Input Voltage, 5V Temperature (°C) Input Bias Current (pA) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.002 0.01 0.1 100 1000 VS = 5V VIN = VS/2 Figure 5-6. Input Bias Current vs. Temperature www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

5.7 Typical Characteristics (continued)

TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Output Sinking Current (A) Output Voltage to V- (V) 100P 1m 10m 100m 10m 100m 100P 1m 10m 100m 10m 100m 125°C 85°C 25°C -40°C Figure 5-7. Output Sinking Current vs. Output Voltage, 1.8V Output Sourcing Current (A) Output Voltage from V+ (V) 100P 1m 10m 100m 10m 100m P-P Output Only 125°C 85°C 25°C -40°C Figure 5-8. Output Sourcing Current vs. Output Voltage, 1.8V Output Sinking Current (A) Output Voltage to V- (V) 100P 1m 10m 100m 10m 100m 100P 1m 10m 100m 10m 100m 125°C 85°C 25°C -40°C Figure 5-9. Output Sinking Current vs. Output Voltage, 3.3V Output Sourcing Current (A) Output Voltage to V+ (V) 100P 1m 10m 100m 10m 100m 100P 1m 10m 100m 10m 100m P-P Output Only 125°C 85°C 25°C -40°C Figure 5-10. Output Sourcing Current vs. Output Voltage, 3.3V Output Sinking Current (A) Output Voltage to V- (V) 100P 1m 10m 100m 10m 100m 100P 1m 10m 100m 10m 100m 125°C 85°C 25°C -40°C Figure 5-11. Output Sinking Current vs. Output Voltage, 5V Output Sourcing Current (A) Output Voltage to V+ (V) 100P 1m 10m 100m 10m 100m 100P 1m 10m 100m 10m 100m P-P Output Only 125°C 85°C 25°C -40°C Figure 5-12. Output Sourcing Current vs. Output Voltage, 5V TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Temperature (°C) Sinking Short Circuit Current (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 100 110 120 130 3.3V 1.8 Figure 5-13. Sinking Short Circuit Current vs. Temperature Temperature (°C) Sourcing Short Circuit Current (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 100 110 120 130 Push-Pull Output Only 5V 3.3V 1.8 Figure 5-14. Sourcing Short Circuit Current vs. Temperature Output Capacittive Load (F) Risetime (ns) 10p 100p 1n 10n 100 VS = 5V 125°C 85°C 25°C -40°C Figure 5-15. Risetime vs. Capacitive Load Output Capacittive Load (F) Falltime (ns) 10p 100p 1n 10n 100 VS = 5V 125°C 85°C 25°C -40°C Figure 5-16. Falltime vs. Capacitive Load www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Input Overdrive (mV) Propagation Delay, High to Low (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 1.8V -40°C 25°C 85°C 125°C Figure 5-17. Propagation Delay, High to Low, 1.8V Input Overdrive (mV) Propagation Delay, Low to High (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 1.8V -40°C 25°C 85°C 125°C Figure 5-18. Propagation Delay, Low to High, 1.8V Input Overdrive (mV) Propagation Delay, High to Low (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 3.3V 125°C 85°C 25°C -40°C Figure 5-19. Propagation Delay, High to Low, 3.3V Input Overdrive (mV) Propagation Delay, Low to High (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 3.3V -40°C 25°C 85°C 125°C Figure 5-20. Propagation Delay, Low to High, 3.3V Input Overdrive (mV) Propagation Delay, High to Low (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 5V -40°C 25°C 85°C 125°C Figure 5-21. Propagation Delay, High to Low, 5V Input Overdrive (mV) Propagation Delay, Low to High (ns) 5 6 78 10 20 30 4050 70 100 200 300 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 VS = 5V -40°C 25°C 85°C 125°C Figure 5-22. Propagation Delay, Low to High, 5V TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 125°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-23. Offset Voltage vs. Input Votlage at 125°C, 1.8V Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 125°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-24. Offset Voltage vs. Input Votlage at 125°C, 5V Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 25°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-25. Offset Voltage vs. Input Votlage at 25°C, 1.8V Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 25°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-26. Offset Voltage vs. Input Votlage at 25°C, 5V Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = -40°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-27. Offset Voltage vs. Input Votlage at -40°C, 1.8V Input Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = -40°C Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-28. Offset Voltage vs. Input Votlage at -40°C, 5V www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

TA = 25°C, VS = 5V, RPULLUP = 2.5k, CL = 15pF, VCM = 0V, VUNDERDRIVE = 100mV, VOVERDRIVE = 100mV unless otherwise noted. Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 125°C Vin = V+ Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-29. Offset Voltage vs. Supply Voltage at 125°C, VIN=V+ Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 125°C Vin = V- Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-30. Offset Voltage vs. Supply Voltage at 125°C, VIN=V- Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = 25°C Vin = V+ Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-31. Offset Voltage vs. Supply Voltage at 25°C, VIN=V+ Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = -40°C Vin = V- Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-32. Offset Voltage vs. Supply Voltage at 25°C, VIN=V- Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = -40°C Vin = V+ Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-33. Offset Voltage vs. Supply Voltage at -40°C, VIN=V+ Supply Voltage (V) Input Offset Voltage (mV) -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 TA = -40°C Vin = V- Unit 1 Unit 2 Unit 3 Unit 4 Figure 5-34. Offset Voltage vs. Supply Voltage at -40°C, VIN=V- TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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6 Detailed Description

6.1 Overview

The TLV4H290-SEP and TLV4H390-SEP devices are quad channel Space Grade Enhanced Products, micro- power comparators with push-pull and open-drain outputs and low input offset voltage. Operating down to 1.65V while only consuming only 25µA per channel. The radiation hardened TLVLV4H290-SEP and TLV4390-SEP are designed for low orbit and space applications. An internal power-on reset circuit makes sure that the output remains in a known state during power-up and power-down while fail-safe inputs can tolerate input transients without damage or false outputs.

6.2 Functional Block Diagram

• * * Push-Pull Version Only Power Clamp

6.3 Feature Description

The TLV4H290-SEP (open-drain output) and TLV4H390-SEP (push-pull output) devices are micro-power comparators that have low input offset voltages and are capable of operating at low voltages. The TLV4H290- SEP and TLV4H390-SEP family feature a rail-to-rail input stage capable of operating up to 200mV beyond the power supply rails. The comparators also feature push-pull and open-drain output stage options and Power-on Reset for known start-up conditions.

6.4 Device Functional Modes

6.4.1 Outputs

6.4.1.1 TLV4H290-SEP Open Drain Output

The TLV4H290-SEP features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0V up to 5.5V, independent of the comparator supply voltage (VS). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower pull-up resistor values help increase the rising edge risetime, but at the expense of increasing V OL and higher power dissipation. The risetime is dependent on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1MΩ) create an exponential rising edge due to the RC time constant and increase the risetime. Unused open drain outputs must be left floating, or can be tied to the V- pin if floating pins are not allowed. While an individual output can typically sink up to 125mA, the total combined current for all channels must be less than 200mA. www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

6.4.1.2 TLV4H390-SEP Push-Pull Output

The TLV4H390-SEP features a push-pull output stage capable of both sinking and sourcing current. This allows driving loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up resistor. The push-pull output must never be connected to another output. Unused push-pull outputs must be left floating, and never tied to a supply, ground, or another output. While an individual output can typically sink and source up to 100mA, the total combined current for all channels must be less than 200mA.

6.4.2 Power-On Reset (POR)

The TLV4H290-SEP and TLV4H390-SEP has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While the power supply (V s) is ramping up or ramping down, the POR circuitry will be activated for up to 30µs after the minimum supply voltage threshold of 1.5V is crossed, or immediately when the supply voltage drops below 1.5V. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential input (VID). The POR circuit will keep the output high impedance (HI-Z) during the POR period (ton). Power On Reset Time (tON) VOH / 2 VOL OUT VS +1.5V Figure 6-1. Power-On Reset Timing Diagram Note that it the nature of an open collector output that the output will rise with the pull-up voltage during the POR period. For the TLV4H390-SEP push-pull output devices, the output is "floating" during the POR period. A light pull-up (to V+) or pull-down (to V-) resistor can be used to pre-bias the output condition to prevent the output from floating. If output high is the desired start-up condition, then use the open collector TLV4H290-SEP, since a pull-up resistor is already required.

6.4.3 Inputs

6.4.3.1 Rail to Rail Input

The TLV4H290-SEP and TLV4H390-SEP input voltage range extends from 200mV below V- to 200mV above V+. The differential input voltage (V ID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when the input pins exceed V+ or V-.

6.4.3.2 Fault Tolerant Inputs

The TLV4H290-SEP and TLV4H390-SEP inputs are fault tolerant up to 5.5V independent of V S. Fault tolerant is defined as maintaining the same high input impedance when V S is unpowered or within the recommended operating ranges. The fault tolerant inputs can be any value between 0V and 5.5V, even while V S is zero or ramping up or down. This feature avoids power sequencing issues as long as the input voltage range and supply voltage are within the specified ranges. This is possible since the inputs are not clamped to V+ and the input current maintains its value even when a higher voltage is applied to the inputs. As long as one of the input pins remains within the valid input range, and the supply voltage is valid and not in POR, the output state will be correct. The following is a summary of input voltage excursions and their outcomes: 1. When both IN- and IN+ are within the specified input voltage range: TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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a. If IN- is higher than IN+ and the offset voltage, the output is low. b. If IN- is lower than IN+ and the offset voltage, the output is high. 2. When IN- is outside the specified input voltage range and IN+ is within the specified voltage range, the output is low. 3. When IN+ is higher than the specified input voltage range and IN- is within the specified input voltage range, the output is high 4. When IN- and IN+ are both outside the specified input voltage range, the output is indeterminate (random). Do not operate in this region. Even with the fault tolerant feature, TI strongly recommends keeping the inputs within the specified input voltage range during normal system operation to maintain datasheet specifications. Operating outside the specified input range can cause changes in specifications such as propagation delay and input bias current, which can lead to unpredictable behavior.

6.4.3.3 Input Protection

The input bias current is typically 5pA for input voltages between V+ and V-. The comparator inputs are protected from reverse voltage by the internal ESD diodes connected to V-. As the input voltage goes under V-, or above the input Absolute Maximum ratings the protection diodes become forward biased and begin to conduct causing the input bias current to increase exponentially. Input bias current typically doubles for each 10°C temperature increase. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents if the clamps conduct. The current must be limited 10mA or less. This series resistance can be part of any resistive input dividers or networks.

6.4.4 ESD Protection

The TLV4H290-SEP and TLV4H390-SEP family incorporates internal ESD protection circuits on all pins. The inputs, and the open-drain output, use a proprietary "snapback" type ESD clamp from each pin to V-, which allows the pins to exceed the supply voltage (V+). While shown as Zener diodes, snapback "short" and go low impedance (like an SCR) when the threshold is exceeded, as opposed to clamping to a defined voltage like a Zener. The TLV4H290-SEP open-drain output protection also consists of a ESD clamp between the output and V- to allow the output to be pulled above V+ to a maximum of 5.5V. The TLV4H390-SEP push-pull output protection consists of a ESD clamp between the output and V-, but also includes a ESD diode clamp to V+, as the output must not exceed the supply rails. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents must the clamps conduct. The current must be limited 10mA or less. This series resistance can be part of any resistive input dividers or networks. TI does not specify the performance of the ESD clamps and external clamping must be added if the inputs or output could exceed the maximum ratings as part of normal operation.

6.4.5 Unused Inputs

If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low offset voltage, tying the inputs directly together can cause high frequency "chatter" as the device triggers on it's own internal wideband noise. Instead, the inputs must be tied to any available voltage that resides within the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input can be grounded and the other input connected to a reference voltage, or even V+ as long as the input is directly connected to the V+ pin (to avoid transients).

6.4.6 Hysteresis

The TLV4H290-SEP and TLV4H390-SEP family does not have internal hysteresis. Due to the wide effective bandwidth and low input offset voltage, it is possible for the output to "chatter" when the absolute differential www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

voltage near zero as the comparator triggers on it's own internal wideband noise. This is normal comparator behavior and is expected. TI recommends that the user add external hysteresis if slow moving signals are expected. See Section 7.1.2 in the following section. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Basic Comparator Definitions

7.1.1.1 Operation

The basic comparator compares the input voltage (V IN) on one input to a reference voltage (V REF) on the other input. In the Figure 7-1 example below, if V IN is less than V REF, the output voltage (V O) is logic low (V OL). If VIN is greater than V REF, the output voltage (V O) is at logic high (V OH). Table 7-1 summarizes the output conditions. The output logic can be inverted by simply swapping the input pins. Table 7-1. Output Conditions Inputs Condition Output IN+ > IN- HIGH (VOH) IN+ = IN- Indeterminate (chatters - see Hysteresis) IN+ < IN- LOW (VOL)

7.1.1.2 Propagation Delay

There is a delay between from when the input crosses the reference voltage and the output responds. This is called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input transitions. This is shown as t pLH and t pHL in Figure 7-1 and is measured from the mid-point of the input to the midpoint of the output. 20% 80% 20% 80% VREF VREF + 100mV VREF 5100mV 50% 50% tpLH tpHL tFtR Input Output ±VREF VIN Output VOL VOH GND VOD (+200mV) VIN VREF + 200mV VREF - 200mV VOD (-200mV) Figure 7-1. Comparator Timing Diagram www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

7.1.1.3 Overdrive Voltage

The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 7-1 example. The overdrive voltage can influence the propagation delay (t p). The smaller the overdrive voltage, the longer the propagation delay, particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest amount of overdrive possible. The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.

7.1.2 Hysteresis

The basic comparator configuration may oscillate or produce a noisy "chatter" output if the applied differential input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very slowly across the switching threshold of the comparator. This problem can be prevented by the addition of hysteresis or positive feedback. The hysteresis transfer curve is shown in Figure 7-2. This curve is a function of three components: V TH, VOS, and VHYST:

• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states.
• VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. VTH + VOS ± (VHYST / 2) VTH + VOS + (VHYST / 2)VTH + VOS Figure 7-2. Hysteresis Transfer Curve For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".

7.1.2.1 Inverting Comparator With Hysteresis

The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator supply voltage (V+), as shown in Figure 7-3. 1 0Ÿ +VCC +5 V VIN 1 0Ÿ 1 0Ÿ VO VA 5 V 0 V VA2 VA1 VO 1.67 V 3.33 V VIN Figure 7-3. TLV4H390-SEP in an Inverting Configuration With Hysteresis The equivalent resistor networks when the output is high and low are shown in Figure 7-3. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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+VCC VA2 VO Low +VCC Figure 7-4. Inverting Configuration Resistor Equivalent Networks When VIN is less than V A, the output voltage is high (for simplicity, assume V O switches as high as V CC). The three network resistors can be represented as R1 || R3 in series with R2, as shown in Figure 7-4. Equation 1 below defines the high-to-low trip voltage (VA1). V = VA1 CC /c180 R2 (R1 || R3) + R2 (1) When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented as R2 || R3 in series with R1, as shown in Equation 2. Use Equation 2 to define the low to high trip voltage (VA2). V = VA2 CC /c180 R2 || R3 R1 + (R2 || R3) (2) Equation 3 defines the total hysteresis provided by the network. /c68 /c45V = V VA A1 A2 (3)

7.1.2.2 Non-Inverting Comparator With Hysteresis

A noninverting comparator with hysteresis requires a two-resistor network and a voltage reference (V REF) at the inverting input, as shown in Figure 7-5, VREF 2.5 V 1 0Ÿ 330 NŸ VOVA 5 V 0 V VIN2 VIN1 VO 1.675 V 3.325 V VIN VIN Figure 7-5. TLV4H390-SEP in a Non-Inverting Configuration With Hysteresis The equivalent resistor networks when the output is high and low are shown in Figure 7-6. www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

VA = VREF VO High +VCC VA = VREF VO Low +VIN1 VIN2 Figure 7-6. Non-Inverting Configuration Resistor Networks When VIN is less than VREF,, the output is low. For the output to switch from low to high, V IN must rise above the VIN1 threshold. Use Equation 4 to calculate VIN1. V = R1IN1 /c180VREF + VREF (4) When VIN is greater than V REF, the output is high. For the comparator to switch back to a low state, V IN must drop below VIN2. Use Equation 5 to calculate VIN2. V =IN2 VREF CC(R1 + R2) V R1/c45 /c180 (5) The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6. /c68V = VIN CC /c180 R1 (6) For more information, please see Application Notes SNOA997 " Inverting comparator with hysteresis circuit " and SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".

7.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output

It is also possible to use an open drain output device, such as the TLV4H390-SEP, but the output pull-up resistor must also be taken into account in the calculations. The pull-up resistor is seen in series with the feedback resistor when the output is high. Thus, the feedback resistor is actually seen as R2 + R PULLUP. TI recommends that the pull-up resistor be at least 10 times less than the feedback resistor value.

7.2 Typical Applications

7.2.1 Window Comparator

Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 7-7 shows a simple window comparator circuit. Window comparators require open drain outputs (TLV4H290-SEP) if the outputs are directly connected together. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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3.3 V Sensor 10 0Ÿ RPU UV_OV Open Drain Output Only! VTH- VTH+ VIN Low when VIN < VTH- Open Drain Output Only! Output high when VIN is within window 10 0Ÿ 10 0Ÿ Low when VIN > VTH+ Figure 7-7. Window Comparator

7.2.1.1 Design Requirements

For this design, follow these design requirements:

• Alert (logic low output) when an input signal is less than 1.1V
• Alert (logic low output) when an input signal is greater than 2.2V
• Alert signal is active low
• Operate from a 3.3V power supply

7.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 7-7. Connect VCC to a 3.3V power supply and V EE to ground. Make R1, R2 and R3 each 10M Ω resistors. These three resistors are used to create the positive and negative thresholds for the window comparator (VTH+ and VTH–). With each resistor being equal, V TH+ is 2.2V and V TH- is 1.1V. Large resistor values such as 10M Ω are used to minimize power consumption. The resistor values can be recalculated to provide the desired trip point values. The sensor output voltage is applied to the inverting and noninverting inputs of the two comparators. Using two open-drain output comparators allows the two comparator outputs to be Wire-OR'ed together. The respective comparator outputs are low when the sensor is less than 1.1V or greater than 2.2V. The respective comparator outputs are high when the sensor is in the range of 1.1V to 2.2V (within the "window"), as shown in Figure 7-8.

7.2.1.3 Application Curve

VTH+ = 2.2 V VTH± = 1.1 V VIN OUT Figure 7-8. Window Comparator Results For more information, please see Application note SBOA221 "Window comparator circuit". www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

7.2.2 Square-Wave Oscillator

Square-wave oscillator can be used as low cost timing reference or system supervisory clock source. A push- pull output (TLV4H390-SEP) is recommended for best symmetry. 100 pF 100 kŸ VCC 100 kŸ OUT VA VC 100 kŸ 100 kŸ Figure 7-9. Square-Wave Oscillator

7.2.2.1 Design Requirements

The square-wave period is determined by the RC time constant of the capacitor C 1 and resistor R 4. The maximum frequency is limited by propagation delay of the device and the capacitance load at the output. The low input bias current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency, which may help to reduce BOM cost and board space. R4 must be over several kilo-ohms to minimize loading the output.

7.2.2.2 Detailed Design Procedure

The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides details of the steps. Figure 7-10. Square-Wave Oscillator Timing Thresholds First consider the output of Figure Figure 7-9 as high, which indicates the inverted input V C is lower than the noninverting input (V A). This causes the C 1 to be charged through R 4, and the voltage V C increases until it is equal to the noninverting input. The value of VA at the point is calculated by Equation 7. CC 2 2 1 3 V R V R R I IR u (7) if R1 = R2= R3, then VA1 = 2VCC/ 3 At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is calculated by Equation 8. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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V ( R I I R )V R + R I I R (8) if R1 = R2 = R3, then VA2 = VCC/3 The C1 now discharges though the R 4, and the voltage V CC decreases until it reaches V A2. At this point, the output switches back to the starting state. The oscillation period equals to the time duration from for C 1 from 2VCC/3 to V CC / 3 then back to 2V CC/3, which is given by R 4C1 × ln 2 for each trip. Therefore, the total time duration is calculated as 2 R4C1 × ln 2. The oscillation frequency can be obtained by Equation 9: f 1/ 2 R4 C1 In2 u u (9)

7.2.2.3 Application Curve

Figure 7-11 shows the simulated results of an oscillator using the following component values:

• R1 = R2 = R3 = R4 = 100kΩ
• C1 = 100pF, CL = 20pF
• V+ = 5V, V– = GND
• Cstray (not shown) from VA TO GND = 10pF Figure 7-11. Square-Wave Oscillator Output Waveform

7.2.3 Adjustable Pulse Width Generator

Figure 7-12 is a variation on the square wave oscillator that allows adjusting the pulse widths. R4 and R5 provide separate charge and discharge paths for the capacitor C depending on the output state. www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

100 kŸ 100 pF 100 kŸ VCC 100 kŸ OUT VA VC

1 MŸ D1

100 kŸ Figure 7-12. Adjustable Pulse Width Generator The charge path is set through R 5 and D2 when the output is high. Similarly, the discharge path for the capacitor is set by R4 and D1 when the output is low. The pulse width t 1 is determined by the RC time constant of R 5 and C. Thus, the time t 2 between the pulses can be changed by varying R 4, and the pulse width can be altered by R 5. The frequency of the output can be changed by varying both R 4 and R 5. At low voltages, the effects of the diode forward drop (0.8V, or 0.15V for Shottky) must be taken into account by altering output high and low voltages in the calculations.

7.2.4 Time Delay Generator

The circuit shown in Figure 7-13 provides output signals at a prescribed time interval from a time reference and automatically resets the output low when the input returns to 0V. This is useful for sequencing a "power on" signal to trigger a controlled start-up of power supplies. 100 NŸ 10 NŸ 51 NŸ 10 0Ÿ 10 NŸ 10 0Ÿ 10 NŸ 10 0Ÿ 51 NŸ 51 NŸ R100 NŸ 100 NŸ VC C Input Gating Signal VIN Open Drain Output t0 t1 t2 t3 t4 VC +VLOGIC2 RPU +VLOGIC3 RPU +VLOGIC1 RPU RPU not required if using push-pull output devices t0 t1 t0 t2 t0 t3 Figure 7-13. Time Delay Generator TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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Consider the case of V IN = 0. The output of comparator 4 is also at ground, "shorting" the capacitor and holding it at 0V. This implies that the outputs of comparators 1, 2, and 3 are also at 0V. When an input signal is applied, the output of open drain comparator 4 goes High-Z and C charges exponentially through R. This is indicated in the graph. The output voltages of comparators 1, 2, and 3 switch to the high state in sequence when V C rises above the reference voltages V 1, V2 and V3. A small amount of hysteresis has been provided by the 10k Ω and 10MΩ resistors to insure fast switching when the RC time constant is chosen to give long delay times. A good starting point is R = 100kΩ and C = 0.01µF to 1µF. All outputs immediately go low when V IN falls to 0V, due to the comparator output going low and immediately discharging the capacitor. Comparator 4 must be a open-drain type output (TLV4H290-SEP), whereas comparators 1 though 3 may be either open drain or push-pull output, depending on system requirements. R PU is not required for push-pull output devices.

7.2.5 Logic Level Shifter

The output of the TLV4H290-SEP is the uncommitted drain of the output transistor. Many open-drain outputs can be tied together to provide an output OR'ing function if desired. VCC Logic OutVLOGIC RPULLUP VLOGIC Logic In 10 kŸ 10 kŸ VCC VCC Open Drain Output Figure 7-14. Universal Logic Level Shifter The two 10 k Ω resistors bias the input to half of the input logic supply level to set the threshold in the mid-point of the input logic levels. Only one shared output pull-up resistor is needed and may be connected to any pull-up voltage between 0V and 5.5V. The pullup voltage must match the driven logic input "high" level.

7.2.6 One-Shot Multivibrator

1 0Ÿ 1 0Ÿ 1N4148 100 pF 1N4148 +VIN t0 t1V2 PW Figure 7-15. One-Shot Multivibrator A monostable multivibrator has one stable state in which it can remain indefinitely. It can be triggered externally to another quasi-stable state. A monostable multivibrator can thus be used to generate a pulse of desired width. The desired pulse width is set by adjusting the values of C 2 and R 4. The resistor divider of R 1 and R 2 can be used to determine the magnitude of the input trigger pulse. The output will change state when V 1 < V 2. Diode www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

D2 provides a rapid discharge path for capacitor C 2 to reset at the end of the pulse. The diode also prevents the non-inverting input from being driven below ground.

7.2.7 Bi-Stable Multivibrator

100 NŸ 100 NŸ SET S R 100 NŸ RESET 50 NŸ Figure 7-16. Bi-Stable Multivibrator A bi-stable multivibrator has two stable states. The reference voltage is set up by the voltage divider of R 2 and R3. A pulse applied to the SET terminal will switch the output of the comparator high. The resistor divider of R 1, R4, and R5 now clamps the non-inverting input to a voltage greater than the reference voltage. A pulse applied to RESET will now toggle the output low.

7.2.8 Zero Crossing Detector

100 NŸ 5 NŸ 5 NŸ VIN 20 0Ÿ 10 NŸ 100 NŸ BAT54 VOUT R1 = R2 = (R5 / 2) Figure 7-17. Zero Crossing Detector A voltage divider of R 4 and R 5 establishes a reference voltage V 1 at the non-inverting input. By making the series resistance of R 1 and R 2 equal to R 5, the comparator switches when V IN = 0. Diode D 1 insures that V 3 clamps near ground. The voltage divider of R 2 and R 3 then prevents V 2 from going below ground. A small amount of hysteresis is setup to ensure rapid output voltage transitions.

7.2.9 Pulse Slicer

A Pulse Slicer is a variation of the Zero Crossing Detector and is used to detect the zero crossings on an input signal with a varying baseline level. This circuit works best with symmetrical waveforms. The RC network of R 1 and C1 establishes an mean reference voltage V REF, which tracks the mean amplitude of the V IN signal. The noninverting input is directly connected to V REF through R2. R2 and R3 are used to produce hysteresis to keep transitions free of spurious toggles. The time constant is a tradeoff between long-term symmetry and response time to changes in amplitude. If the waveform is data, it is recommended that the data be encoded in NRZ (Non-Return to Zero) format to maintain proper average baseline. Asymmetrical inputs may suffer from timing distortions caused by the changing VREF average voltage. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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0.01 F Output R1 R2 R3 VREF VIN Figure 7-18. Pulse Slicer using TLV4H390-SEP For this design, follow these design requirements:

• The RC constant value (R2 and C1) must support the targeted data rate to maintain a valid tripping threshold.
• The hysteresis introduced with R2 and R43 helps to avoid spurious output toggles. The TLV4H290-SEP may also be used, but with the addition of a pull-up resistor on the output (not shown for clarity). Figure 7-19 shows the results of a 9600 baud data signal riding on a varying baseline. VOUT VIN VREF 1.8 V 1.2 V 4.0 V 0.0 V 1.61 V 1.58 V Time Figure 7-19. Pulse Slicer Waveforms

7.3 Power Supply Recommendations

Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1µF ceramic bypass capacitor directly between V CC pin and ground pins. Narrow, peak currents will be drawn during the output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and create an inaccurate comparison or even oscillations. The device can be powered from either "split" supplies (V+, V- & GND), or a "single" supply (V+ and GND), with GND applied to the V- pin. Input signals must stay within the specified input range (between V+ and V-) for either type. Note that on "split" supplies, the output now swings "low" (VOL) to V- potential and not GND.

7.4 Layout

7.4.1 Layout Guidelines

For accurate comparator applications it is important maintain a stable power supply with minimized noise and glitches. Output rise and fall times are in the tens of nanoseconds, and must be treated as high speed logic www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

devices. The bypass capacitor must be as close to the supply pin as possible and connected to a solid ground plane, and preferably directly between the VCC and GND pins. Minimize coupling between outputs and inputs to prevent output oscillations. Do not run output and input traces in parallel unless there is a V CC or GND trace between output to reduce coupling. When series resistance is added to inputs, place resistor close to the device. A low value (<100 ohms) resistor may also be added in series with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge shapes, controlled impedance traces with back-terminations must be used when routing long distances.

7.4.2 Layout Example

1IN– 1IN+

3 GND

2IN– 52IN+ 0.1 Fμ Ground Bypass Capacitor Negative Supply or GroundPositive Supply 0.1 Fμ Ground Only needed for dual power supplies 3IN+ 3IN– 4IN+ 4IN– 3OUT 4OUT Figure 7-20. Layout Example TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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8 Device and Documentation Support

8.1 Documentation Support

8.1.1 Related Documentation

Analog Engineers Circuit Cookbook: Amplifiers (See Comparators section) - SLYY137 Precision Design, Comparator with Hysteresis Reference Design— TIDU020 Window comparator circuit - SBOA221 Reference Design, Window Comparator Reference Design— TIPD178 Comparator with and without hysteresis circuit - SBOA219 Inverting comparator with hysteresis circuit - SNOA997 Non-Inverting Comparator With Hysteresis Circuit - SBOA313 Zero crossing detection using comparator circuit - SNOA999 PWM generator circuit - SBOA212 How to Implement Comparators for Improving Performance of Rotary Encoder in Industrial Drive Applications - SNOAA41 A Quad of Independently Func Comparators - SNOA654

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2024 * Initial Release www.ti.com TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TLV4H290-SEP TLV4H390-SEP ADVANCE INFORMATION

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TLV4H290-SEP, TLV4H390-SEP SNOSDF0 – MAY 2024 www.ti.com

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www.ti.com 4-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples P4H290MDYYTSEP ACTIVE SOT-23-THIN DYY 14 250 TBD Call TI Call TI -55 to 125 Samples P4H390MDYYTSEP ACTIVE SOT-23-THIN DYY 14 250 TBD Call TI Call TI -55 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 4-Jul-2024 Addendum-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

0.1 C A B

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 ALTERNATIVE PACKAGE SINGULATION VIEW

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/C 04/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

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