P45N03LTG ETC2

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 3

Technical content

1 AUG-13-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P45N03LTG TO-220 Lead Free NIKO-SEM ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Gate-Source Voltage V GS ±20 V TC = 25 °C 45 Continuous Drain Current TC = 100 °C ID Pulsed Drain Current1 I DM 140 Avalanche Current I AR 20 A Avalanche Energy L = 0.1mH E AS 140 Repetitive Avalanche Energy2 L = 0.05mH E AR 5.6 mJ TC = 25 °C 65 Power Dissipation TC = 100 °C PD W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 Lead Temperature (1/16” from case for 10 sec.) T L 275 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJC 3 Junction-to-Ambient RθJA 70 Case-to-Heatsink RθCS 0.7 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1Ĉ ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = 250µA 25 Gate Threshold Voltage V GS(th) VDS = VGS, ID = 250µA 0.8 1.2 2.5 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±20V ±250 nA VDS = 20V, VGS = 0V 25 Zero Gate Voltage Drain Current I DSS VDS = 20V, VGS = 0V, TJ = 125 °C 250 µA 1. GATE 2. DRAIN 3. SOURCE PRODUCT SUMMARY V (BR)DSS R DS(ON) I D 25 20mƸ 45A G D S

2 AUG-13-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P45N03LTG TO-220 Lead Free NIKO-SEM On-State Drain Current1 I D(ON) V DS = 10V, VGS = 10V 45 A VGS = 7V, ID = 18A 20 30 Drain-Source On-State Resistance1 RDS(ON) VGS = 10V, ID = 20A 15 28 mƸ Forward Transconductance1 g fs V DS = 15V, ID = 30A 16 S DYNAMIC Input Capacitance C iss 600 Output Capacitance C oss 290 Reverse Transfer Capacitance C rss VGS = 0V, VDS = 15V, f = 1MHz 100 pF Total Gate Charge2 Q g 25 Gate-Source Charge2 Q gs 2.9 Gate-Drain Charge2 Q gd VDS = 0.5V(BR)DSS, VGS = 10V, ID = 20A 7.0 nC Turn-On Delay Time2 t d(on) 7.0 Rise Time2 t r VDS = 15V, RL = 1Ƹ 7.0 Turn-Off Delay Time2 t d(off) ID ≅ 30A, VGS = 10V, RGS = 2.5Ƹ 24 Fall Time2 t f 6.0 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S 45 Pulsed Current3 I SM 150 A Forward Voltage1 V SD I F = IS, VGS = 0V 1.3 V Reverse Recovery Time t rr 37 nS Peak Reverse Recovery Current I RM(REC) IF = IS, dlF/dt = 100A / µS 200 A Reverse Recovery Charge Q rr 0.043 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2Ĉ. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P45N03LTG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

3 AUG-13-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P45N03LTG TO-220 Lead Free NIKO-SEM TO-220 (3-Lead) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. C 20 J 4.4 4.6 4.8 G 0.72 0.8 0.88 N 7 °