P2003EVG ETC2

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P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG S O P - 8 Lead-Free NIKO-SEM OCT-20-2004 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage V DS -30 V Gate-Source Voltage V GS ±20 V TC = 25 °C -9 Continuous Drain Current TC = 70 °C ID Pulsed Drain Current1 I DM -50 A TC = 25 °C 2.5 Power Dissipation TC = 70 °C PD 1.3 W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJc 25 °C / W Junction-to-Ambient R θJA 50 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = -250µA -30 Gate Threshold Voltage V GS(th) VDS = VGS, ID = -250µA -1 -1.5 -3 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±20V ±100 nA VDS = -24V, VGS = 0V -1 Zero Gate Voltage Drain Current I DSS VDS = -20V, VGS = 0V, TJ = 125 °C -10 µA On-State Drain Current1 I D(ON) V DS = -5V, VGS = -10V -50 A VGS = -4.5V, ID = -7A 25 35Drain-Source On-State Resistance1 RDS(ON) VGS = -10V, ID = -9A 15 20 mƸ Forward Transconductance1 g fs V DS = -10V, ID = -9A 24 S 4 : G A T E 5,6,7,8 :DRAIN 1,2,3 :SOURCE PRODUCT SUMMARY V (BR)DSS R DS(ON) I D -30 20mƸ -9A G S D

P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG S O P - 8 Lead-Free NIKO-SEM OCT-20-2004 DYNAMIC Input Capacitance C iss 1610 Output Capacitance C oss 410 Reverse Transfer Capacitance C rss VGS = 0V, VDS = -15V, f = 1MHz 200 pF Total Gate Charge2 Q g 17 24 Gate-Source Charge2 Q gs 5 Gate-Drain Charge2 Q gd VDS = 0.5V(BR)DSS, VGS = -10V, ID = -9A 6 nC Turn-On Delay Time2 t d(on) 5.7 Rise Time2 t r VDS = -15V, RL = 1Ƹ 10 Turn-Off Delay Time2 t d(off) ID ≅ -1A, VGS = -10V, RGS = 6Ƹ 18 Fall Time2 t f 5 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S -2.1 Pulsed Current3 I SM -4 A Forward Voltage1 V SD I F = -1A, VGS = 0V -1.2 V 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2Ĉ. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P2003EVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG S O P - 8 Lead-Free NIKO-SEM OCT-20-2004 Body Diode Forward Voltage Variation with Source Current and Temperature 25° C 0.6 0.1 0.0001 0.001 0.01 SD 0.2 0.4 V = 0V 100 T = 125° CA GS 0.8 1.0 -55° C 1.2 -Is - Reverse Drain Current(A) -V - Body Diode Forward Voltage(V)

P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG S O P - 8 Lead-Free NIKO-SEM OCT-20-2004

P-Channel Logic Level Enhancement Mode Field Effect Transistor P2003EVG S O P - 8 Lead-Free NIKO-SEM OCT-20-2004 SOIC-8(D) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. C 5.8 6.0 6.2 J 0.22 D 0.38 0.445 0.51 K 0 ° 4 ° 8 ° E 1.27 L F 1.35 1.55 1.75 M G 0.1 0.175 0.25 N