P1402CDG ETC2

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Technical content

1 NOV-05-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free NIKO-SEM ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Gate-Source Voltage V GS ±12 V TC = 25 °C 45 Continuous Drain Current TC = 100 °C ID Pulsed Drain Current1 I DM 140 A TC = 25 °C 48 Power Dissipation TC = 100 °C PD W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 Lead Temperature (1/16” from case for 10 sec.) T L 275 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJC 2.6 Junction-to-Ambient RθJA 110 °C / W 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1Ĉ ELECTRICAL CHARACTERISTICS (T C = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = 250µA 20 Gate Threshold Voltage V GS(th) VDS = VGS, ID = 250µA 0.45 0.75 1.25 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±12V ±100 nA VDS = 16V, VGS = 0V 1 Zero Gate Voltage Drain Current I DSS VDS = 13.2V, VGS = 0V, TJ = 125 °C 10 µA On-State Drain Current1 I D(ON) V DS = 5V, VGS = 4.5V 45 A VGS = 2.5V, ID = 9A 18 26 Drain-Source On-State Resistance1 RDS(ON) VGS = 5V, ID = 18A 11 14 mƸ Forward Transconductance1 g fs V DS = 10V, ID = 18A 26 S 1. GATE 2. DRAIN 3. SOURCE PRODUCT SUMMARY V(BR)DSS R DS(ON) I D 20 14mƸ 45A G D S

2 NOV-05-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free NIKO-SEM DYNAMIC Input Capacitance C iss 500 Output Capacitance C oss 310 Reverse Transfer Capacitance C rss VGS = 0V, VDS = 15V, f = 1MHz 125 pF Total Gate Charge2 Q g 17 Gate-Source Charge2 Q gs 1.5 Gate-Drain Charge2 Q gd VDS = 0.5V(BR)DSS, VGS = 5V, ID = 18A 10.5 nC Turn-On Delay Time2 t d(on) 7.5 Rise Time2 t r V DS = 10V, 83 Turn-Off Delay Time2 t d(off) ID ≅ 18A, VGS = 5V, RGS = 3.3Ƹ 18 Fall Time2 t f 23 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S 45 Pulsed Current3 I SM 140 A Forward Voltage1 V SD I F = IS, VGS = 0V 1.3 V Reverse Recovery Time t rr 37 nS Peak Reverse Recovery Current I RM(REC) IF = IS, dlF/dt = 100A / µS 200 A Reverse Recovery Charge Q rr 0.043 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2Ĉ. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P1402CDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.

3 NOV-05-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free NIKO-SEM Body Diode Forward Voltage Variation with Source Current and Temperature Is - Reverse Drain Current(A) 0.0001 0.001 0.01 0.40.2 0.6 V = 0V 0.1 T = 125° C 25° C GS 1.00.8 1.2 -55° C 1.4 V - Body Diode Forward Voltage(V)SD

4 NOV-05-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free NIKO-SEM

5 NOV-05-2004

N-Channel Logic Level Enhancement Mode Field Effect Transistor P1402CDG TO-252 (DPAK) Lead-Free NIKO-SEM TO-252 (DPAK) MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. A 9.35 10.4 H 0.89 2.03 B 2.2 2.4 I 6.35 6.80 C 0.45 0.6 J 5.2 5.5 D 0.89 1.5 K 0.6 1 E 0.45 0.69 L 0.5 0.9 G 5.2 6.2 N G A H J I B C M L K D E F 13 2