P01N02LJA ETC1

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1 AUG-30-2002

N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 NIKO-SEM ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Gate-Source Voltage V GS ±15 V TC = 25 °C 1.2 Continuous Drain Current TC = 100 °C ID 1.0 Pulsed Drain Current1 I DM 12 A TC = 25 °C 0.6 Power Dissipation TC = 100 °C PD 0.5 W Operating Junction & Storage Temperature Range T j, Tstg -55 to 150 Lead Temperature (1/16” from case for 10 sec.) T L 275 THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS Junction-to-Case RθJC 65 Junction-to-Ambient RθJA 230 °C / W 1Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT STATIC Drain-Source Breakdown Voltage V (BR)DSS VGS = 0V, ID = 250 µA 25 Gate Threshold Voltage V GS(th) VDS = VGS, ID = 250 µA 0.7 1.0 2.5 V Gate-Body Leakage I GSS V DS = 0V, VGS = ±15V ±250 nA VDS = 20V, VGS = 0V 25 Zero Gate Voltage Drain Current I DSS VDS = 20V, VGS = 0V, TJ = 125 °C 250 µA On-State Drain Current1 I D(ON) V DS = 10V, VGS = 10V 1.2 A VGS = 7V, ID = 1.2A 120 180 Drain-Source On-State Resistance1 R DS(ON) VGS = 10V, ID = 1.2A 70 120 mΩ Forward Transconductance1 g fs V DS = 20V, ID = 1.2A 16 S PRODUCT SUMMARY V(BR)DSS R DS(ON) I D 25V 70mΩ 1.2A G D S 4 : G A T E 5,6,7,8 :DRAIN 1,2,3 :SOURCE

2 AUG-30-2002

N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 NIKO-SEM DYNAMIC Input Capacitance C iss 120 Output Capacitance C oss 100 Reverse Transfer Capacitance C rss VGS = 0V, VDS = 15V, f = 1MHz pF Total Gate Charge2 Q g 11 Gate-Source Charge2 Q gs 3.0 Gate-Drain Charge2 Q gd VDS = 0.5V(BR)DSS, VGS = 10V, ID = 1A 5.8 nC Turn-On Delay Time2 t d(on) 7 Rise Time2 t r VDS = 15V, RL = 1Ω 20 Turn-Off Delay Time2 t d(off) ID ≅ 1A, VGS = 10V, RGS = 50Ω 13 Fall Time2 t f 19 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current I S 1.2 Pulsed Current3 I SM 12 A Forward Voltage1 V SD I F = IS, VGS = 0V 1.3 V Reverse Recovery Time t rr 70 nS Reverse Recovery Charge Q rr IF = IS, dlF/dt = 100A / µS 0.22 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “102B”

3 AUG-30-2002

N-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary) P01N02LJA J-LEAD8 NIKO-SEM J-LEAD8 MECHANICAL DATA mm mm Dimension Min. Typ. Max. Dimension Min. Typ. Max. A 0.50 H 0.10 0.20 B 0.15 0.3 I 0.048 C 1.65 1.85 J 0 0.1 F 0.70 0.90 1.00 M G 1.10 N