NTAG SmartSensor temperature monitor
Document overview
- Manufacturer or author: NXP B.V.
- PDF pages: 46
Technical content
Datasheet sections
- 1 General description
- 2 Features and benefits
- 2.1 System
- 2.2 Memory
- 2.3 Digital peripherals
- 2.4 Analog peripherals
- 2.5 Communication interfaces
- 2.6 Clock generation
- 2.7 Power control
- 2.8 General
- 3 Applications
- 4 Ordering information
- 5 Marking
- 6 Block diagram
- 7 Pinning
- 7.1 HVQFN24
- 7.2 WLCSP25
- 7.3 NHS3100W8
- 8 Functional description
- 8.1 Arm Cortex-M0+ core
- 8.2 Memory map
- 8.3 System configuration
- 8.3.1 Clock generation
- 8.3.2 Reset
- 8.4 Power management
- 8.4.1 System power architecture
- 8.4.2 Power management unit (PMU)
- 8.5 Nested vectored interrupt controller (NVIC)
- 8.5.1 Features
- 8.5.2 Interrupt sources
- 8.6 I/O configuration
- 8.6.1 PIO0 pin mode
- 8.6.2 PIO0 I2C-bus mode
- 8.6.3 PIO0 current source mode
- 8.7 Fast general-purpose parallel I/O
- 8.7.1 Features
- 8.8 I2C-bus controller
- 8.8.1 Features
- 8.8.2 General description
- 8.8.3 I2C-bus pin description
- 8.9 SPI controller
- 8.9.1 Features
- 8.9.2 General description
- 8.9.3 Pin description
- 8.9.3.1 Pin detailed description
- 8.10 RFID/NFC communication unit
- 8.10.1 Features
- 8.10.2 General description
- 8.11.1 Features
- 8.11.2 General description
- 8.12.1 Features
- 8.12.2 General description
- 8.13 Watchdog timer (WDT)
- 8.13.1 Features
- 8.13.2 General description
- 8.14 System tick timer
- 8.14.1 Features
- 8.14.2 General description
- 8.15 Real-time clock (RTC) timer
- 8.15.1 Features
- 8.15.2 General description
- 8.16 Temperature sensor
- 8.16.1 Features
- 8.16.2 General description
- 8.17 Serial wire debug (SWD)
- 8.18 On-chip flash memory
- 8.18.1 Reading from flash
- 8.18.2 Writing to flash
- 8.18.3 Erasing/programming flash
- 8.19 On-chip SRAM
- 8.20 On-chip EEPROM
- 8.20.1 Reading from EEPROM
- 8.20.2 Writing to EEPROM
- 9 Limiting values
- 10 Static characteristics
- 11 Dynamic characteristics
- 11.1 I/O pins
- 11.2 I2C-bus
- 11.3 SPI interfaces
- 12 Package outline
- 13 Abbreviations
- 14 References
- 15 Revision history
- 16 Legal information
NTAG SmartSensor temperature monitor Rev. 8.03 — 27 May 2021 Product data sheet
1 General description
The NXP Semiconductors NHS3100 is a member of the NTAG SmartSensor product family. The IC is optimized for temperature monitoring and logging. It has an embedded NFC interface, an internal temperature sensor, and a direct battery connection. These features support an effective system solution with a minimal number of external components and a single layer foil implementation for temperature monitoring. The NHS3100 works either battery-powered or NFC-powered. The embedded Arm Cortex-M0+ offers flexibility to the users of this IC to implement their own dedicated solution. The NHS3100 contains multiple features, including multiple power-down modes and a selectable CPU frequency of 8 MHz and down for ultra-low power consumption. Users can program this NHS3100 with the industry-wide standard solutions for Arm Cortex-M0+ processors. As of September 22, 2017, the NFC forum has certified this device (certification ID: 58516). CAUTION Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards.
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
2 Features and benefits
2.1 System
- Arm Cortex-M0+ processor running at frequencies of up to 8 MHz
- Arm Cortex-M0+ built-in nested vectored interrupt controller (NVIC)
- Arm serial wire debug (SWD)
- System tick timer
- IC reset input
2.2 Memory
- 32 kB on-chip flash programming memory
- 4 kB on-chip EEPROM of which 320 bytes are write-protected
- 8 kB SRAM
2.3 Digital peripherals
- Up to 12 general-purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors and repeater mode
- GPIO pins which can be used as edge and level sensitive interrupt sources
- High-current drivers (sink only; 20 mA) on four GPIO pins
- High-current drivers (sink only; 20 mA) on two I2C-bus pins
- Programmable watchdog timer (WDT)
2.4 Analog peripherals
- Temperature sensor with: – ±0.5 °C absolute temperature accuracy between −40 °C and 0 °C – ±0.3 °C absolute temperature accuracy between 0 °C and +45 °C – ±0.5 °C absolute temperature accuracy between +45 °C and +85 °C
2.5 Communication interfaces
- NFC/RFID ISO 14443 type A interface; NFC Forum type 2 compatible
- I2C-bus interface supporting full I2C-bus specification and fast mode with a data rate of 400 kbit/s, with multiple-address recognition and monitor mode
2.6 Clock generation
- 8 MHz internal RC oscillator, trimmed to 2 %, accuracy, which is used for the system clock
- Timer oscillator operating at 32 kHz linked to an RTC timer unit
2.7 Power control
- Support for 1.72 V to 3.6 V external voltages
- The NHS3100 can also be powered from the NFC field.
- Activation via NFC possible
- Integrated power management unit (PMU) for versatile control of power consumption Product data sheet Rev. 8.03 — 27 May 2021
- Four reduced power modes for Arm Cortex-M0+: sleep, deep-sleep, deep power-down, and battery-off
- Power gating for each analog peripheral for ultra-low power operation
- < 50 nA IC current consumption in battery-off mode at 3.0 V
- Power-on reset (POR)
2.8 General
- Unique device serial number for identification
3 Applications
- Temperature measurement
- Temperature logging
- Cold chain validation
4 Ordering information
Table 1. Ordering information
5 Marking
Table 2. Marking codes
6 Block diagram
Cortex-M0+ and memories), and AHB/APB slave modules. Figure 1. NHS3100 block diagram
7 Pinning
configuration registers. The sections below show the pinning of the packages.
7.1 HVQFN24
Figure 2 shows the pad layout of the NHS3100 in the HVQFN24 package.
25 VSS
Figure 2. Pin configuration HVQFN24
1 PIO0_0/WAKEUP 13[1] PIO0_7/CT16B_M1
2 PIO0_1/CLKOUT 14[1] PIO0_3/CT16B_M0
3 PIO0_2/SSEL 15[1] PIO0_10/CT32B_M0/SWCLK
4 PIO0_6/SCLK 16[1] PIO0_11/CT32B_M1/SWDIO
5 PIO0_8/MISO 17[2] (reserved)
6 PIO0_9/MOSI 18[2] (reserved)
7 VDDBAT 19 LB
8 VSS 20 LA
9 RESETN 21[2] (reserved)
11 PIO0_4/SCL 23[2] (reserved)
12 PIO0_5/SDA 24[2] (reserved)
Table 3. Pad allocation table of the HVQFN24 package [1] High source current pads. See Section 8.6.3. [2] These pads must be tied to ground.
7 VDDBAT supply positive supply voltage
8 VSS supply ground
20 LA A NFC antenna/coil terminal A
Table 4. Pad description of the HVQFN24 package
9 RESETN I external reset input[4]
Table 4. Pad description of the HVQFN24 package...continued depends on the function selected through the IOCONFIG register block. power-down mode, it must be pulled LOW for a minimum of 100 μs. [3] Open drain, no pull-up or pull down. processor execution to begin at address 0. It has weak pull-up to VBAT or internal NFC voltage (whichever is highest).
7.2 WLCSP25
Figure 3 shows the ball layout of the NHS3100 in the WLCSP25 package. Figure 3. Ball configuration WLCSP25 Table 5. Ball allocation table of the WLCSP25 package
Table 5. Ball allocation table of the WLCSP25 package...continued [1] High source current balls. See Section 8.6.3. [2] These balls must be tied to ground. Table 6. Ball description of the WLCSP25 package
Table 6. Ball description of the WLCSP25 package...continued depends on the function selected through the IOCONFIG register block. power-down mode, it must be pulled LOW for a minimum of 100 μs. [3] Open drain, no pull-up or pull-down. processor execution to begin at address 0. It has weak pull-up to Vdd or internal NFC voltage (whichever is highest).
7.3 NHS3100W8
Figure 4 shows the bump layout of the NHS3100W8 gold bump version. Figure 4. Bump configuration Bump die: Top view, bumps up
1 PIO0_0/WAKEUP 7 TP1
2 TP0 8 VSS
3 LA 9 VDDBAT
4 LB 10 PIO0_6
5 PIO0_11/CT32B_M1/SWDIO 11 TP2
Table 7. Bump allocation table of the NHS3100W8 package
6 PIO0_10/CT32B_M0/SWCLK 12 TP3
Table 7. Bump allocation table of the NHS3100W8 package...continued
9 VDDBAT supply positive supply voltage
10 PIO0_6 I/O GPIO
3 LA A NFC antenna/coil terminal A
4 LB A NFC antenna/coil terminal B
2 TP0 - test pin - do not connect
7 TP1 - test pin - do not connect, or connect to ground
11 TP2 - test pin - do not connect
12 TP3 - test pin - do not connect
Table 8. Bump description of the NHS3100W8 package depends on the function selected through the IOCONFIG register block. LOW for a minimum of 100 μs to exit deep power-down mode.
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8 Functional description
8.1 Arm Cortex-M0+ core
See the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed description of the Arm Cortex-M0+ processor. The NHS3100 Arm Cortex-M0+ core has the following configuration:
- System options – Nested vectored interrupt controller (NVIC) – Fast (single-cycle) multiplier – System tick timer – Support for wake-up interrupt controller – Vector table remapping register – Reset of all registers
- Debug options – Serial wire debug (SWD) with two watchpoint comparators and four breakpoint comparators – Halting debug is supported
8.2 Memory map
Figure 5 shows the memory and peripheral address space of the NHS3100. The only AHB peripheral device on the NHS3100 is the GPIO module. The APB peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space. All peripheral register addresses are 32-bit word aligned. Byte and halfword addressing is not possible. All reading and writing are done per full word. Product data sheet Rev. 8.03 — 27 May 2021
Figure 5. NHS3100 memory map
8.3 System configuration
8.3.1 Clock generation
The NHS3100 clock generator unit (CGU) includes two independent RC oscillators.
Note: Some features are not available when using the lower clock speeds. frequency to minimize dynamic current consumption during the boot cycle. system clock divider settings, while the digital part uses the system clock (AHB clock 0). Figure 6. NHS3100 clock generator block diagram
8.3.2 Reset
- RESETN pin
- Watchdog reset
- Software reset
8.4 Power management
sources and the powering of the different voltage domains in the IC.
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8.4.1 System power architecture
The NHS3100 accepts power from two different sources: from the external power supply pin VDDBAT or from the built-in NFC/RFID rectifier. The NHS3100 has a small automatic source selector that monitors the power inputs (VBAT and VNFC, see Figure 7) as well as pin RESETN. The PSWBAT switch is kept open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given, the always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT and VNFC are present. The automatic source selector unit in the PMU decides on the powering of the internal domains based on the power source.
- If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal domains after a trigger on pin RESETN or via NFC.
- If a voltage ≤ 1.72 V is detected on VBAT, and a higher voltage is detected on VNFC, the internal domains are powered from VNFC.
- If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are powered from VBAT.
- Switch-over between power sources is possible. If both VBAT and VNFC are available initially, the system is powered from VBAT. If VBAT then becomes unavailable (because it is switched off externally, or by a PSWBAT/PSWNFC power switch override), the internal domains are immediately powered from VNFC. Switchover is supported in both directions.
- The user can force the selection of the VBAT input by disabling the automatic power switch, which disables the automatic source selector voltage comparator. When on NFC power only (passive operation), connect one or more 100 nF external capacitors in parallel to a GPIO pad and set that pad as an output driven to logic 1. Choosing a high-drive pin is preferred. Several pins can be connected in parallel. PSWNFC and PSWBAT are the power switches. When an RF field is present, PSWNFC connects power to the VDD_ALON power net. When a positive edge is detected on RESETN, PSWBAT connects power from the battery. If no RF power is available, the PMU can open this PSWBAT switch, effectively switching off the device. After connecting VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected on RESETN or RF power is applied. Each component of the NHS3100 resides in one of several internal power domains, as indicated in Figure 7. The domains are VBAT, VNFC, VDD_ALON, VDD1V2 and VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are either powered or not powered, depending on the mode of the NHS3100. There are 5 modes:
- Active
- Sleep
- Deep-sleep
- Deep power-down
- Battery-off The VDD_ALON domain contains brownout detection (BOD). When this feature is enabled, it raises a BOD interrupt if the VDD_ALON voltage drops below 1.8 V. The PMU controls the active, sleep, deep-sleep, and deep power-down modes and so also the power flow to the different internal components. Product data sheet Rev. 8.03 — 27 May 2021
The PMU has two LDOs powering the internal VDD1V2 and VDD1V6 voltage domains. When powered via VNFC, a 1.2 nF buffer capacitor is included at the input of the LDOs. and the power gate have a leakage of less than 50 nA. Figure 7. NHS3100 power architecture Table 9. IC power states [1] DPDN indicates whether the system is in deep power-down mode.
Figure 9. NHS3100 power-up sequence
8.4.2 Power management unit (PMU)
purpose registers in the PMU can be used to retain data during deep power-down mode. the PMU also raises a BOD interrupt when it is configured. addition, it contains the overrides for the power source selection.
8.5 Nested vectored interrupt controller (NVIC)
dramatically reducing the interrupt latency.
8.5.1 Features
- NVIC that is a part of the Arm Cortex-M0+
- Tightly coupled interrupt controller provides low interrupt latency
- Controls system exceptions and peripheral interrupts
- Four programmable interrupt priority levels with hardware priority level masking
- Software interrupt generation
8.5.2 Interrupt sources
may have one or more interrupt lines to the nested vectored interrupt controller (NVIC). priority about which line is connected where, except for certain standards from Arm. Table 12. Connection of interrupt source to the nested vectored interrupt controller corresponds to the RTC on/off timer.
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8.6 I/O configuration
The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable:
- Pin function
- Internal pull-up/pull-down resistor or bus keeper function
- Low-pass filter
- I2C-bus mode for pads hosting the I2C-bus function The IOCON registers control the function (GPIO or peripheral function), the input mode, and the hysteresis of all PIO0_m pins. In addition, the I2C-bus pins can be configured for different I2C-bus modes. The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins are GPIO pins, the GPIO0DIR registers determine if the pin is configured as an input or output. For any peripheral function, the pin direction is controlled automatically depending on the functionality of the pin. The GPIO0DIR registers have no effect on peripheral functions.
8.6.1 PIO0 pin mode
The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull- down resistors for each pin or to select the repeater mode. The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is no pull-up or pull-down enabled. When the pin is at logic 1, the repeater mode enables the pull-up resistor. When the pin is at logic 0, it enables the pull-down resistor. If this mode is configured as an input and is not driven externally, it causes the pin to retain its last known state. The state retention is not applicable to the deep power- down mode. Repeater mode is typically used to prevent a pin from floating when it is temporarily not driven. Allowing it to float can use significant power.
8.6.2 PIO0 I2C-bus mode
If the FUNC bits of registers PIO0_4 and PIO0_5 select the I2C-bus function, the I2C-bus pins can be configured for different I2C-bus modes:
- Standard-mode/Fast-mode I2C-bus with input glitch filter (including an open-drain output according to the I2C-bus specification)
- Standard open-drain I/O functionality without input filter
8.6.3 PIO0 current source mode
PIO0_3, PIO0_7, PIO0_10, and PIO0_11 are high-source pads that can deliver up to 20 mA to the load. These PIO pins can be set to either digital mode or analog current sink mode. In digital mode, the output voltage of the pad switches between VSS and VDD. In analog current drive mode, the output current sink switches between the values set by the ILO and IHI bits. The maximum pad voltage is limited to 5 V. Product data sheet Rev. 8.03 — 27 May 2021
Figure 10. Pin configuration with current source mode
8.7 Fast general-purpose parallel I/O
a specific peripheral function. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.
- GPIO registers are on the Arm Cortex-M0+ I/O bus for fastest possible single-cycle I/O timing
- An entire port value can be written in one instruction
- Mask, set, and clear operations are supported for the entire port All GPIO port pins are fixed pin functions. The switch matrix enables or disables these functions on the pins. So, each GPIO port pin is assigned to one specific pin and cannot be moved to another pin.
8.7.1 Features
- Bit level port registers allow a single instruction to set and clear any number of bits in one write operation
- Direction control of individual bits
- After reset, all I/Os default to GPIO inputs without pull-up or pull-down resistors. The I2C-bus true open-drain pins PIO0_4 and PIO0_5 and the SWD pins PIO0_10 and PIO0_11 are exceptions
- Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin
- Direction (input/output) can be set and cleared individually
- Pin direction bits can be toggled Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8.8 I2C-bus controller
8.8.1 Features
Standard I2C-bus compliant (Ref. 3) interfaces may be configured as master, slave, or master/slave.
- Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus
- Programmable clock allows adjustment of I2C-bus transfer rates
- Data transfer is bidirectional between masters and slaves
- Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
- Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer
- Supports standard mode (100 kbit/s) and fast mode (400 kbit/s)
- Optional recognition of up to four slave addresses
- Monitor mode allows observing all I2C-bus traffic, regardless of slave address
- The I2C-bus can be used for test and diagnostic purposes
- The I2C-bus contains a standard I2C-bus compliant interface with two pins
- Possibility to wake up NHS3100 on matching I2C-bus slave address
8.8.2 General description
Two types of data transfers are possible on the I2C-bus, depending on the state of the direction bit (R/W):
- Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.
- Data transfer from a slave transmitter to a master receiver The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. The slave then transmits the data bytes to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. As a repeated START condition is also the beginning of the next serial transfer, the I2C-bus is not released. The I2C-bus interface is byte oriented and has four operating modes:
- Master transmitter mode
- Master receiver mode
- Slave transmitter mode
- Slave receiver mode The I2C-bus interface is completely I2C-bus compliant. It supports power-off of the NHS3100 independent of other devices on the same I2C-bus. The I2C-bus interface requires a minimum 2 MHz system clock to operate in normal mode. It requires 8 MHz for fast mode. Product data sheet Rev. 8.03 — 27 May 2021
8.8.3 I2C-bus pin description
Table 13. I2C-bus pin description compatible with the I2C-bus specification.
8.9 SPI controller
8.9.1 Features
- Compatible with Motorola SPI, 4-wire Texas Instruments Synchronous Serial Interface (SSI), and National Semiconductor Microwire buses
- Synchronous serial communication
- Supports master or slave operation
- Eight-frame FIFOs for both transmit and receive
- 4-bit to 16-bit frame
8.9.2 General description
two data flows carries meaningful data.
8.9.3 Pin description
Table 14. SPI pin description
8.9.3.1 Pin detailed description
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor HIGH. SCK only switches during a data transfer. At any other time, the SPI/SSP interface either stays in its inactive state or is not driven (remains in high-impedance state). Frame sync/slave select When the SPI/SSP interface is a bus master, it drives this signal to an active state before the start of serial data. It then releases it to an inactive state after the data has been sent. The active state can be HIGH or LOW depending upon the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal qualifies the presence of data from the master according to the protocol in use. When there is only one master and slave, the master signals, frame sync, or slave select, can be connected directly to the corresponding slave input. When there are multiple slaves, further qualification of frame sync/slave select inputs is normally necessary to prevent more than one slave from responding to a transfer. Master input slave output (MISO) The MISO signal transfers serial data from the slave to the master. When the SPI/SSP is a slave, it outputs serial data on this signal. When the SPI/SSP is a master, it clocks in serial data from this signal. It does not drive this signal and leaves it in a high-impedance state when the SPI/SSP is a slave and not selected by FS/SSEL. Product data sheet Rev. 8.03 — 27 May 2021
serial data from this signal.
8.10 RFID/NFC communication unit
8.10.1 Features
- ISO/IEC14443A part 1 to part 3 compatible
- MIFARE (Ultralight) EV1 compatible
- NFC Forum Type 2 compatible
- Easy interfacing with standard user memory space READ/WRITE commands
- Passive operation possible
8.10.2 General description
The RFID/NFC interface allows communication using 13.56 MHz proximity signaling. Figure 11. Block diagram of the RFID/NFC interface communication to this shared memory. Forum Type 2 NDEF messaging and ISO/IEC 11073.
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor 8.11 16-bit timer
8.11.1 Features
One 16-bit timer with a programmable 16-bit prescaler.
- Timer operation
- Four 16-bit match registers that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation
- Up to two CT16B external outputs corresponding to the match registers with the following capabilities: – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match
- Up to two match registers can be configured as pulse width modulation (PWM). It allows the use of up to two match outputs as single edge controlled PWM outputs
8.11.2 General description
The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. The use of the match registers that are not pinned out to control the PWM cycle length is recommended. Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor 8.12 32-bit timer
8.12.1 Features
One 32-bit timer with a programmable 32-bit prescaler.
- Timer operation
- Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match – Stop timer on match with optional interrupt generation – Reset timer on match with optional interrupt generation
- Up to two CT32B external outputs corresponding to the match registers with the following capabilities: – Set LOW on match – Set HIGH on match – Toggle on match – Do nothing on match
- Up to two match registers can be configured as PWM allowing the use of up to two match outputs as single edge controlled PWM outputs
8.12.2 General description
The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. Use of the match registers that are not pinned out to control the PWM cycle length is recommended.
8.13 Watchdog timer (WDT)
If the microcontroller enters an erroneous state, the purpose of the watchdog timer (WDT) is to reset it within a reasonable amount of time. When enabled, if the user program fails to feed (or reload) the WDT within a predetermined amount of time, the WDT generates a system reset.
8.13.1 Features
- If not periodically reloaded, it internally resets the microcontroller
- Debug mode
- Enabled by software but requires a hardware reset or a WDT reset/interrupt to be disabled
- If enabled, incorrect/incomplete feed sequence causes reset/interrupt
- Flag to indicate WDT reset
- Programmable 24-bit timer with internal prescaler
- Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 224 × 4) in multiples of TWDCLK × 4 Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
- The WDT clock (WDCLK) source is a 2 MHz clock derived from the SFRO, or the external clock as set by the SYSCLKCTRL register
8.13.2 General description
The WDT consists of a divide by four fixed prescaler and a 24-bit counter. The clock is fed to the timer via a prescaler. The timer decrements when clocked. The minimum value by which the counter is decremented is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence, the minimum WDT interval is (TWDCLK × 256 × 4) and the maximum is (TWDCLK × 224 × 4), in multiples of (TWDCLK × 4).
8.14 System tick timer
8.14.1 Features
- Simple 24-bit timer
- Uses dedicated exception vector
- Clocked internally by the system clock or the system clock divided by two
8.14.2 General description
The SYSTICK timer is a part of the Cortex-M0+. The SYSTICK timer can be used to generate a fixed periodic interrupt for use by an operating system or other system. Since the SYSTICK timer is a part of the Cortex-M0+, it facilitates porting of software by providing a standard timer available on Cortex-M0+-based devices. The SYSTICK timer can be used for management software. See the Cortex-M0+ Devices - Generic User Guide (Ref. 2) for details.
8.15 Real-time clock (RTC) timer
8.15.1 Features
The real-time clock (RTC) block contains two counters:
- A countdown timer generating a wake-up signal when it expires.
- A continuous counter that counts seconds since power-up or the last system reset The countdown timer runs on a low-speed clock and runs in an always-on power domain. The delay and a clock tuning prescaler can be configured via the APB bus. The RTC countdown timer generates the deep power-down wake-up signal and the RTC interrupt signal (wake-up interrupt 12). The deep power-down wake-up signal is always generated, while the interrupt can be masked according to the settings in the RTCIMSC register.
8.15.2 General description
The RTC module consists of two parts:
- The RTC core module, implementing the RTC timers themselves. This module runs in the always-on VDD_ALON domain.
- The AMBA APB slave interface. This module allows configuration of the RTC core via an APB bus. It runs in the switched power domain. Product data sheet Rev. 8.03 — 27 May 2021
8.16 Temperature sensor
8.16.1 Features
a calibrated value in Kelvin.
8.16.2 General description
- It determines the value of
Table 15. Conversion time for different resolution of TSEN
8.17 Serial wire debug (SWD)
breakpoints and two watchpoints.
- Supports Arm SWD mode
- Direct debug access to all memories, registers, and peripherals
- No target resources are required for the debugging session
- Four instruction breakpoints that can also be used to remap instruction addresses for code patches. Two data comparators that can be used to remap addresses for patches to literal values.
- Two data watchpoints that can also be used as triggers 1 Vbe is the base-emitter voltage of a bipolar transistor. Basically, the temperature sensor measures the voltage drop over a diode formed by the base-emitter junction of a bipolar transistor. It compares the Vbe at different current levels (from which follows the ΔVbe). Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8.18 On-chip flash memory
The NHS3100 contains a 32 kB flash memory of which 30 kB can be used as program and data memory. The flash is organized in 32 sectors of 1 kB. Each sector consists of 16 rows of 16 × 32- bit words.
8.18.1 Reading from flash
Reading is done via the AHB interface. The memory is mapped on the bus address space as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement.
8.18.2 Writing to flash
Writing to flash means copying a word of data over the AHB to the page buffer of the flash. It does not actually program the data in the memory array. Subsequent erase and program cycles do this programming.
8.18.3 Erasing/programming flash
Erasing and programming are separate operations. Both are only possible on memory sectors that are unprotected and unlocked. Protect/lock information is stored inside the memory itself, so the controller is not aware of protection status. So, if a program/erase operation is performed on a protected or locked sector, it does not flag an error.
- Protection: At the exit from reset, all sectors are protected against accidental modification. To allow modifications, a sector must be unprotected. It can then be protected again after that the modification has been performed.
- Locking: Each flash sector has a lock bit. Lock bits can be set but cannot be cleared. Locked sectors cannot be erased and reprogramed.
8.19 On-chip SRAM
The NHS3100 contains a total of 8 kB on-chip SRAM memory configured as 256 × 2 × 4 × 32 bit.
8.20 On-chip EEPROM
The NHS3100 contains a 4 kB EEPROM. This EEPROM is organized in 64 rows of 32 × 16-bit words. Of these rows, the last four contain calibration and test data and are locked. The boot loader uses this data or it is made accessible to the application via the firmware application programming interface (API).
8.20.1 Reading from EEPROM
Reading is done via the AHB interface. The memory is mapped on the bus address space, as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement. Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
8.20.2 Writing to EEPROM
Erasing and programming is performed, as a single operation, on one or more words inside a single page. Previous write operations have transferred the data to be programmed into the memory page buffer. The page buffer tracks which words were written to (offset within the page only). Words not written to, retain their previous content. Product data sheet Rev. 8.03 — 27 May 2021
9 Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Table 16. Limiting values
10 Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified. Table 17. Static characteristics
Plot of IDD / VDD when Arm running a while; 1 loop in normal mode; no NFC field present. Figure 12. Active current consumption Table 18. Temperature sensor characteristics sensor can be user-calibrated to reach higher accuracy.
Table 19. Antenna input characteristics Table 20. EEPROM characteristics
11 Dynamic characteristics
11.1 I/O pins
These characteristics apply to standard port pins and RESETN pin. Tamb = −40 °C to +85 °C. Table 21. I/O dynamic characteristics
11.2 I2C-bus
Table 22. I2C-bus dynamic characteristics [1] Parameters are valid over operating temperature range unless otherwise specified. undefined region of the falling edge of SCL. [3] Cb = total capacitance of one bus line in pF. series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [5] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. the data must be valid by the setup time before it releases the clock. [7] tSU;DAT is the data setup time that is measured against the rising edge of SCL; applies to data in transmission and the acknowledge. tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is released. This procedure is in accordance with the standard-mode I2C-bus specification. Also, the acknowledge timing must meet this setup time.
Figure 13. I2C-bus pins clock timing
11.3 SPI interfaces
Table 23. Dynamic characteristics of SPI pins in SPI mode
- The main clock frequency fmain
- The SPI peripheral clock divider (SSPCLKDIV)
- The SPI SCR parameter (specified in the SSP0CR0 register)
- The SPI CPSDVSR parameter (specified in the SPI clock prescale register) [2] Tamb = −40 °C to +105 °C [3] tcy(clk) = 12 × Tcy(PCLK) [4] Tamb = 25 °C for normal voltage supply: VDD = 3.3 V Product data sheet Rev. 8.03 — 27 May 2021
- Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Figure 16. Package outline
Figure 17. WLCSP25 package outline
Figure 18. Bumped die package outline
13 Abbreviations
Table 24. Abbreviations
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
14 References
[1] DDI0484C_cortex_m0p_r0p1_trm Cortex-M0+ Devices - Technical Reference Manual [2] DUI0662B_cortex_m0p_r0p1_dgug Cortex-M0+ Devices - Generic User Guide [3] UM10204 user manual I2C-bus specification and user manual; 2014, NXP Semiconductors Product data sheet Rev. 8.03 — 27 May 2021
- Text has been updated throughout the document NHS3100 v.7 20190411 Product data sheet - NHS3100 v.6 Modifications: • Section 7 "Pinning" updated
- Text has been updated throughout the document NHS3100 v.6 20180615 Product data sheet - NHS3100 v.5 Modifications: • NFC certification and logo have been added
- Text has been updated throughout the document NHS3100 v.5 20161205 Product data sheet - NHS3100 v.4 Modifications • Addition of NHS3100W8 package data NHS3100 v.4 20160905 Product data sheet - NHS3100 v.3 Modifications • General update
- Section 10 "Static characteristics" updated
- Drawing revisions NHS3100 v.3 20160601 Preliminary data sheet - NHS3100 v.2 Modifications • General update NHS3100 v.2 20160531 Objective data sheet - NHS3100 v.1 Modifications • Section 7 "Pinning" updated
- Section 8.4.2 "Power Management Unit (PMU)" major revision
- Section 11.2 "I2C-bus" updated
- Section 11.3 "SPI interfaces" added
- Section 12: WLCSP25 package added
- Section 1: Cautions added
- Section 10 "Static characteristics" updated
- Section 8.7 "Fast General-Purpose parallel I/O" added NHS3100 v.1 20150811 Objective data sheet - -
Table 25. Revision history
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor
16 Legal information
16.1 Data sheet status
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Product data sheet Rev. 8.03 — 27 May 2021
NXP Semiconductors NHS3100 NTAG SmartSensor temperature monitor No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.
16.4 Licenses
Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/ IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software.
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP B.V. Product data sheet Rev. 8.03 — 27 May 2021