NAFE11388B40BS

NXP Semiconductors

Universal ±25 V 8-Input Low Power AFE Rev. 1 - 4 November 2022

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NAFE11388_V01 NXP

Document overview

Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
PDF pages: 111

Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Applications
4 Ordering information
4.1 Ordering options
4.2 Product family
5 Block diagram
6 Pinning information
6.1 Pinning
6.2 Pin description
7 Functional description
7.1 Overview
7.2 Precise and fast data acquisition
7.3 Detailed description
7.3.1 Architecture block diagram
7.3.2 High-voltage multiplexer — HVMUX
7.3.2.1 Analog input protection diodes and
7.3.2.2 HV input multiplexer - HVMUXIN
7.3.3 Programmable gain amplifier
7.3.3.1 PGA input operating ranges
7.3.3.2 PGA input common mode ranges
7.3.4 Low-voltage multiplexer - LVMUX
7.3.5 Analog-to-digital converter
7.3.5.1 ADC buffer
7.3.5.2 Sigma delta ADC
7.3.5.3 Frequency response
7.3.5.5 Step response
7.3.5.6 ADC data rate
7.3.5.7 Noise performance vs data rate
7.3.6 Gain and offset calibration
7.3.6.1 Gain and offset calibration coefficients
7.3.6.2 Factory calibrated coefficients
7.3.6.3 Loading and use
7.3.7 Temperature coefficient correction
7.3.8 Voltage reference
7.3.8.1 Low-drift voltage reference
7.3.8.2 Coarse voltage reference
7.3.8.3 Voltage reference selector
7.3.9 Temperature sensor
7.3.10 General-purpose input/output
7.3.11 Clock sources
7.3.11.1 Internal RC oscillator
7.3.11.2 Oscillator with external crystal
7.3.11.3 External oscillator
7.3.11.4 Clock selection
7.3.11.5 Auto-selection of clock source
7.3.11.6 User selection of clock sources
7.3.11.7 Clock period drift detection
7.4 Channel configuration and multichannel
7.4.1 Channel configuration
7.4.2 Working with multichannel sequencer
7.4.2.1 Channel enable
7.4.2.2 On-the-fly channel configuration
7.5 ADC Conversion and Reading modes
7.5.1 Reading start event
7.5.2 Reading process stop event
7.5.2.1 CMD_ABORT
7.5.2.2 CMD_END
7.5.3 Reading period
7.5.3.1 Calculate the effective reading period
7.5.3.2 Fastest reading period in SCCR mode
7.5.3.3 Effective output data rate with CH_DELAY
7.5.4 ADC synchronization
7.5.4.1 ADC_SYNC bit
7.5.4.2 Synchronize multi-NAFE with SYNC pulse
7.5.4.3 Synchronize NAFE to host with SYNC pin
7.5.4.4 Synchronize the host to the NAFE through
7.5.4.5 Synchronize the NAFE and host to the
7.5.4.6 Reading conversion start - SYNC pulse
7.5.5 Reading modes
7.5.6 Reading sequence
7.5.7 CMD_SS (single-channel single-reading)
7.5.7.1 Flow chart - SCSR
7.5.7.2 Timing diagram - SCSR
7.5.7.3 Code example - SCSR
7.5.7.4 Reading period for SCSR
7.5.8 CMD_SC (single-channel continuous-
7.5.8.1 Flow chart - SCCR
7.5.8.2 Timing diagram - SCCR
7.5.8.3 Code example - SCCR
7.5.8.4 Reading period for SCCR
7.5.9 CMD_MM (multichannel multireading)
7.5.9.1 Flow chart - MCMR
7.5.9.2 Timing diagram - MCMR
7.5.9.3 Code example - MCMR
7.5.9.4 Reading period for MCMR
7.5.10 CMD_MC (multichannel continuous-
7.5.10.1 Flow chart - MCCR
7.5.10.2 Timing diagram - MCCR
7.5.10.3 Code example - MCCR
7.5.10.4 Reading period for MCCR
7.5.11 CMD_MS (multichannel single-reading)
7.5.11.1 Flow chart - MCSR
7.5.11.2 Timing diagram - Flow chart - MCSR
7.5.11.3 Code example - Flow chart - MCSR
7.5.11.4 Reading period for MCSR
7.6 ADC code to voltage translation
7.7 Diagnostic features
7.7.1 Input under-range and over-range
7.7.2 REFH and REFL for diagnostic
7.7.3 Voltage supply rail monitoring
7.7.4 Thermal monitoring and thermal shutdown
7.7.5 Alarm
7.7.6 Interrupts

Universal ±25 V 8-Input Low Power AFE Rev. 1 — 4 November 2022 Product data sheet Document information Information Content Keywords NAFE11388, 8-channel, analog front-end (AFE), 24-bit ADC resolution Abstract Highly configurable multichannel precision AFE for industrial applications.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

1 General description

The NAFE11388 is a highly configurable industrial-grade multichannel universal input analog front-end (AFE) that meets high-precision measurement requirements. The device integrates low-leakage, high-voltage (HV) fast multiplexers, low-offset and low- drift programmable gain amplifier (PGA) and buffers, high data-rate 24-bit Delta-Sigma analog-to-digital converter (ADC), and low-drift voltage reference. All of the HV analog pins are diode-protected internally for electromagnetic compatibility (EMC) and miswiring scenarios. The NAFE11388 is equipped with various diagnostic and supplies supervisory circuitry for condition monitoring and anomaly detection. Two precise calibration voltage sources are made available for ease of end-to-end system self-calibration and predictive maintenance. The NAFE11388 family of products is designed for programmable logic controllers (PLCs), I/O modules, data loggers, instrumentation, and high-precision sensor and data acquisition systems. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

2 Features and benefits

Eight configurable HV inputs – Single-ended or differential, with ranges up to ±25 V – Independent configurations for voltage and current ranges – Overvoltage protected up to ±36 V for less than one hour
Fast data rates – 7.5 SPS to 288 kSPS – Simultaneous 50 Hz/60 Hz line rejection – ENOB: 17-bit at 72 kSPS
High accuracy – 0.005 %FS accuracy at room after user calibration – 0.1 %FS accuracy over -25 ℃ to 105 ℃
System calibration – End-to-end calibration with integrated precise voltage sources – Accurate factory-calibrated products available
±3 ⁰C internal temperature sensor
0.2% internal oscillator accuracy at room temperature
Diagnostic system for faults detection and prediction
CRC error detection
Ten GPIOs
32 MHz SPI interface
Robust 8 kV HBM ESD and IEC61000-4-5 2 kV surge protection
Power supply: HV: ±7 V to ±24 V, LV: 3.3 V
125 mW low power consumption
Operating temperature range TA: -40 ℃ to +125 ℃
Package: 64 pin, 9 mm x 9 mm x 0.85 mm HVQFN NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

3 Applications

Data acquisition system
PLC, DCS I/O modules
Industrial automation and process control NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

4 Ordering information

Table 1. Ordering information

4.1 Ordering options

1000 TA = -40 °C to +125 °C

260 TA = -40 °C to +125 °C

1300 TA = -40 °C to +125 °C

Table 2. Ordering options

4.2 Product family

5 Block diagram

6 Pinning information

6.1 Pinning

Figure 2. Pin configuration in 64-lead 9 mm x 9 mm x 0.85 mm VQFN package

6.2 Pin description

9 AGND Ground Analog ground

14 AGND Ground Analog ground

16 AGND Ground Analog ground

17 HVSS Supply

High-voltage negative supply, 0.1 µF || 4.7 µF cap to AGND.

18 AGND Ground Analog ground

19 AGND Ground Analog ground

20 AGND Ground Analog ground

21 AVDD Supply 3.3 V analog power supply, 0.1 µF || 4.7 µF cap to AGND.

22 AGND Ground Analog ground

23 REF_BYP AO Buffered voltage reference bypass, 100 pF (max loading) cap

27 AGND Ground Analog ground

28 CAPP_

29 CAPN_

30 REFP_

31 REFN_

33 AGND Ground Analog ground

34 AGND Ground Analog ground

36 RSTB DI Chip reset, active-low (CMOS push-pull or open drain with

37 SPI_

ADDR DI SPI address 0 (with internal 100 kΩ pulldown).

38 DGND Ground Digital ground

39 INTB DO Active low interrupt output (CMOS push-pull or open drain

40 SYNC DI ADC sync pulse input

41 CSB DI Chip select input, active-low (with internal 100 kΩ pullup)

42 SCLK DI SPI clock input

43 MOSI DI SPI data input

44 MISO DO SPI data output

45 DRDY DO ADC data ready output, active-high

46 DVDD Supply 3.3 V digital power supply, 0.1 µF || 4.7 µF cap to DGND.

47 DGND Ground Digital ground

48 LDO_DIG AO Internal 1.8 V LDO bypass, 0.1 µF || 4.7 µF uF cap to DGND.

50 EXTCLK/

51 DGND Ground Digital ground

52 GPIO9 DI, DO General-purpose digital input/output or system clock output

53 GPIO8 DI, DO General-purpose digital input/output

54 GPIO7 DI, DO General-purpose digital input/output

55 GPIO6 DI, DO General-purpose digital input/output

56 GPIO5 DI, DO General-purpose digital input/output

57 DVDD Supply 3.3 V digital power supply, 0.1 µF || 4.7 µF cap to DGND.

58 DGND Ground Digital ground

59 GPIO4 DI, DO General-purpose digital input/output

60 GPIO3 DI, DO General-purpose digital input/output

61 GPIO2 DI, DO General-purpose digital input/output

62 GPIO1 DI, DO, AI

63 GPIO0 DI, DO, AI

64 AGND Ground Analog ground

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

7 Functional description

7.1 Overview

The NAFE11388 is a highly configurable, universal eight-input AFE with various integrated diagnostic features. At HV analog inputs, the low-leakage pins could be configured anywhere from eight single-ended to four differential signals, with external common input AICOM or internal AGND reference. Three selectable PGA gain settings of 0.2 V/V, 0.4 V/V, and 0.8 V/V are available to provide differential full ranges of ±25 V to ±6.25 V. In general, all of the HV input characteristics are specified to the linear (nominal) input ranges for all of the channel gain settings, which is 80 % of the full input range. In addition to the differential signals at PGA output, one auxiliary differential input GPIO0- GPIO1, four low-voltage diagnostic signals are also multiplexed to ADC: power supplies AVDD, HVDD, HVSS, and an independent coarse voltage reference (REF_coarse). The voltage reference (VREF) derived voltage sources REFH and REFL are available through pins for external measurement. These two voltage sources are also connected as inputs to high-voltage multiplexer (HVMUX). They could be used for on-chip self- calibration or self-diagnostic purposes, regardless of the voltage reference sources, which can be either external, internal, or mixed. When supplied with the factory-calibrated coefficients, REFH and REFL facilitate routine calibrations without the need for additional accurate components. An independent on-chip temperature sensor is included for continuous die temperature monitoring with a 16-bit readout. This temperature reading is also used to trigger an overtemperature warning at 145 ⁰C, auto-shutdown at 165 ⁰C, or the user-programmable temperature alarm. The NAFE11388 comes with ten GPIOs that satisfy most of the needs for monitoring and control in typical applications. The selectable clock sources could be either the internal oscillator or a crystal oscillator, or external clock. In addition, a data and conversion synchronization is available via SYNC and DRDY pins, and the last falling edge of the SPI clock. Succeeding to 24-bit ΔΣ modulator, a multistage digital filter was designed to offer a wide range of data rates with a selectable cascade of SINC filters and the option of Single-Cycle Settling mode versus Normal Settling mode. In multichannel, fast-switching applications, the user may trade off speed/accuracy and fine-tune the effective data rate. Simultaneous 50 Hz and 60 Hz line rejection is available in lower data rates. The software-configurable sequencer enables high data-rate input channel scanning at system level. Five efficient reading modes are available for ADC data conversion: single-channel single-reading (SCSR), single-channel continuous-reading (SCCR), multichannel single- reading (MCSR), multichannel multireading (MCMR), and multi-channel continuous- reading (MCCR). The user may issue command CMD_BURST_DATA to read back multiple channels data in a single SPI transaction. See Table 17 for conversion start commands.

7.2 Precise and fast data acquisition

The NAFE11388 is suitable for data acquisition of high-precision and high-speed analog inputs. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

288 ksps to 7.5 sps in Normal Settling mode
72 ksps to 1.5 sps in Single-Cycle Settling mode Figure 3 shows the scanning time required when HV MUX switches from one input to another (effectively presenting a step function), and PGA follows to settle with limited bandwidth and the required ADC conversion time at a specified data rate.

Figure 3. Scanning time per input

7.3 Detailed description

This section describes the building blocks integrated in the NAFE11388.

7.3.1 Architecture block diagram

7.3.2 High-voltage multiplexer — HVMUX

AI1P, AI2P, AI3P, AI4P are connected to the positive high-voltage multiplexer HVMUXINP input.
AI1N, AI2N, AI3N, AI4N are connected to the negative high-voltage multiplexers HVMUXINN input. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

negative high-voltage input multiplexers HVMUXINP and HMMUXINN, respectively.

7.3.2.1 Analog input protection diodes and clamping

clamping circuits for electrostatic discharge (ESD) and surge protection.

29 V DC CLAMP

Figure 4. Input pins protection Each HV input pin is equipped with input protection diodes connected to HVDD, HVSS. to AGND is installed for each HV input pin for reliability. See Section 11.1. and during printed-circuit board (PCB) assembly. input current to the specified value.

7.3.2.2 HV input multiplexer - HVMUXIN

pseudo-differential mode, the NAFE provides high common-mode rejection. software configuration selecting the respective inputs of HVMUX. software configuration selecting the respective inputs of HVMUX. AIxP or AIxN inputs and the negative wire of signal to AICOM. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE The selected input to positive and negative HVMUX should be configured appropriately to match the physical connections. When CH_CHOP = 1 is set, two ADC conversions will be performed. Therefore the final ADC output is the average of the difference of these two ADC intermediate outputs. As such, the channel offset is canceled and the effective output data rate is half of the programmed value. Note: The ADC output polarity sign is inverted internally and automatically whenever AIxP input is connected to AICOM or GND while AIxN input is AI1N..AI4N, REFH, REFL.

7.3.2.2.1 Analog common input (AICOM)

To ensure precise single-ended measurements, AICOM pin should be connected in series with a 2.5 kΩ resistor and connected to an external GND reference physically close to the measured positive signal on the printed-circuit board (PCB).

7.3.2.2.2 REFH and REFL

REFH and REFL provide stable and accurate voltage sources derived from VREF_BYP. REFH and REFL are 92 % and 8 %, of VREF_BYP, with a nominal value of 2.3 V and 0.2 V, respectively. REFH and REFL are connected to inputs of both HVMUXINP and HVMUXINN multiplexer. REFH and REFL could be used for system-level self-calibration on the field, failure prediction, and predictive maintenance. Factory OPT_COEF1 and OPT_COEF2 is available for REFH and REFL on optional part numbers.

7.3.2.2.3 Low-leakage circuit

The NAFE11388 provides a high-input impedance of 1 GΩ and low-input leakage current less than 5 nA at 105 °C. In combination with its low-noise and low-offset drift PGA, the device is well-suited for precision temperature measurement with RTD and TC.

7.3.3 Programmable gain amplifier

The programmable gain amplifier (PGA) is a low-noise, programmable gain, differential input, differential output amplifier. The PGA operates in Gain or Attenuation mode, depending on the gain selected. Typically, the PGA is programmed to utilize the input NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.3.3.1 PGA input operating ranges

and resolution for the different types of input signals and PGA gain setting. Table 5. HV input ranges and resolutions

7.3.3.2 PGA input common mode ranges

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Then, for And

7.3.4 Low-voltage multiplexer - LVMUX

The internal node voltages (scaled HVDD and HVSS, AVDD, VREF_Coarse, GPIO0- GPIO1) and PGA outputs are routed to the ADC input using the low-voltage multiplexer.

7.3.5 Analog-to-digital converter

7.3.5.1 ADC buffer

The ADC buffer is used to drive the sampling circuit of the ADC, where its differential output pins, CAPP and CAPN, are to be loaded with external C0G type capacitor.

7.3.5.2 Sigma delta ADC

The ADC is based on sigma delta architecture that provides low-noise and high-speed acquisition in Single-Channel and Multichannel mode. The sigma delta architecture includes a sigma delta modulator followed by a configurable digital filter. The ADC modulator is a third-order ΣΔ modulator. The modulator samples the analog input voltage at a high-sample rate (fMOD = fsys_clk / 2) and converts the analog input to a bit stream that is processed by the following digital filter. The digital filter processes the modulator output data to produce the high-resolution conversion result. The digital filter filters and decimates the data. Software selection of a certain digital filter depends on the trade-off between resolution, data rate, and line-cycle rejection acceptable in a system. The ADC digital filter consists of two SINC filter stages. The first stage is a variable decimation SINC4 filter followed by the second stage variable-decimation, variable-order SINC filters. The optimized high-speed SINC4 filter averages and down-samples the modulator data to produce high-speed data rates from 288 ksps to 6 ksps. The low-speed digital filter performs additional filtering and decimation to produce data rates of 4.5 ksps to 7.5 sps. The low-speed stage is a programmable-order SINC filter as SINC1, SINC2, SINC3, SINC4. The data rate is programmed by the CH_CONFIG1.ADC_DATA_RATE bits. The digital filters are controlled by CH_CONFIG1.ADC_SINC bits. Note: SINCx filter has settling time of x clock cycles, where x is the order. To manage the SINC filter settling, the NAFE11388 offers two different Conversion modes. The Single-Cycle Settling mode is suggested for a multichannel system to avoid the settling error. The Normal Settling mode is suggested for single channel to get a faster data rate or lower noise.

7.3.5.3 Frequency response

The low-pass filtering effect of the SINC filters sets the overall frequency response of the ADC. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

Figure 7. SINC Normal mode rejection vs frequency vs data rata

7.3.5.5 Step response

Normal settling: Fits better for single-channel reading, providing lower noise measurements.
Single-cycle settling: Fits better for multichannel reading, providing settled output. Figure 8 shows the relative settling time of the digital filter for the normal settling for different orders of SINC filter. Time (i) 0 160 aaa-046688 Amplitude (division) STEP_IN

8 SINC_1

Figure 8. SINC filter step response to high, the output takes four samples to settle. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 9. Normal Settling mode and SINC4 Figure 10. Single-Cycle Settling mode and SINC4

7.3.5.6 ADC data rate

16-bit format by setting ADC_DATA_OUT_16BIT bit in SYS_CONFIG0 register. Table 6. Data rate (system clock: 4.608 MHz) with the lowest OSR, SINC4 only in Normal Settling mode.

7.3.5.7 Noise performance vs data rate

(corresponding input full-scale ranges of ±25 V to ±6.25 V) as input-referred values. higher or lower noise performance results because of the statistical nature of the noise.

7.3.5.7.1 Noise 24-bit option

Table 7. Noise µVrms (24-bit low power)...continued

7.3.5.7.2 ENOB 24-bit option

Table 8. ENOB 24-bit option...continued

7.3.5.7.3 Noise 16-bit option

Table 9. Noise µVrms (16-bit low power)...continued

7.3.5.7.4 ENOB 16-bit option

Table 10. ENOB (16-bit low power)...continued

7.3.6 Gain and offset calibration

Gain: GAIN_COEF0[23:0] to GAIN_COEF15[23:0]
Offset: OFFSET_COEF0[23:0] to OFFSET_COEF15[23:0]
Optional: OPTC_COEF0[23:0] to OPTC_COEF13[23:0] To reduce the calibration error, the bit-width of gain, offset, and self-calibration coefficient registers are 24-bit wide, the same as main ADC. The above user-calibration coefficients can be read and written by the user. During device power up or reset, the factory calibrated coefficients stored in NVM are loaded into the preset registers, if available. The user may overwrite with different calibration coefficients as needed. In general, there are three categories of calibration coefficients:
System offset and gain calibration coefficients for voltage or current input
System offset and gain calibration coefficients for resistance and RTD input
Self-calibration values – 2.5 V VREF – 2.3 V REFH and 0.2 V REFL These features enable accurate dynamic self-calibration without external voltage sources and advanced predictive maintenance. Table 11 describes the calibration gain/offset coefficient pair, addressable by coefficient pointer CH_CONFIG1.CH_CAL_GAIN_OFFSET. Note: The gain and offset coefficients are channel-gain setting dependent. Pointer Gain register ADDR \\h Offset register ADDR \\h NVM stored coefficient and setting 0 GAIN_COEF0[23:0] 80 OFFSET_COEF0[23:0] 90 Gain = 0.2 V/V, single-ended AIxx-AICOM 1 GAIN_COEF1[23:0] 81 OFFSET_COEF1[23:0] 91 Gain = 0.4 V/V, single-ended AIxx-AICOM 2 GAIN_COEF2[23:0] 82 OFFSET_COEF2[23:0] 92 Gain = 0.8 V/V, single-ended AIxx-AICOM

3 GAIN_COEF3[23:0] 83 OFFSET_COEF3[23:0] 93 -

4 GAIN_COEF4[23:0] 84 OFFSET_COEF4[23:0] 94 -

5 GAIN_COEF5[23:0] 85 OFFSET_COEF5[23:0] 95 -

6 GAIN_COEF6[23:0] 86 OFFSET_COEF6[23:0] 96 -

7 GAIN_COEF7[23:0] 87 OFFSET_COEF7[23:0] 97 -

8 GAIN_COEF8[23:0] 88 OFFSET_COEF8[23:0] 98 -

9 GAIN_COEF9[23:0] 89 OFFSET_COEF9[23:0] 99 -

10 GAIN_COEF10[23:0] 8A OFFSET_COEF10[23:0] 9A -

11 GAIN_COEF11[23:0] 8B OFFSET_COEF11[23:0] 9B -

12 GAIN_COEF12[23:0] 8C OFFSET_COEF12[23:0] 9C -

13 GAIN_COEF13[23:0] 8D OFFSET_COEF13[23:0] 9D -

14 GAIN_COEF14[23:0] 8E OFFSET_COEF14[23:0] 9E -

15 GAIN_COEF15[23:0] 8F OFFSET_COEF15[23:0] 9F -

Table 11. System gain and offset calibration registers...continued Table 12. Optional calibration registers

7.3.6.1 Gain and offset calibration coefficients

internal adder and multiplier for offset and gain compensation. to 7F_FFFF\\h. A register value of 00_0000\\h has no offset correction. Gain calibration registers are 24-bit wide. Their values are straight binary format. 40_0000\\h. Table 13 shows the full range of gain factor correction. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 13. Gain calibration coefficient and factor Table 14. Offset calibration coefficient and factor

7.3.6.2 Factory calibrated coefficients

the user-calibration coefficients registers. time upon power up, reset or CMD_RELOAD. calibrated coefficient pairs as necessary. address the calibrated coefficient pair to be used for each channel setup. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE GAIN_COEF1(at 0x81) is paired with OFFSET_COEF1(at 0x91), and GAIN_COEF15(at 0x8F) is paired with OFFSET_COEF15(at 0x9F).

7.3.6.3 Loading and use

Upon chip power up, the factory calibration coefficients are uploaded from NVM to user-calibration coefficient registers GAIN_COEFi[23:0], OFFSET_COEFi[23:0], OPTC_COEFi[23:0]. When CHIP_READY bit in SYS_STATUS0 register is asserted to 1, that indicates the chip is ready to perform conversion. For ADC conversion on the logical channel (default is channel 0, CH0), a pair of offset and gain coefficients is mated with each logical channel by register CH_CONFIG1.CH_CAL_GAIN_OFFSET[3:0]. Before the conversion takes place, the value in the designated pair of offset and gain coefficient will be latched into the internal registers to be used for compensating internal gain and offset errors. The user may shuffle GAIN_COEF and OFFSET_COEF when setting up the logical channel after initialization or power up. For example, setting channel CH0 to gain = 0.8 V/V, the user will need to set GAIN_COEF0[23:0] and OFFSET_COEF0[23:0] with the calibrated coefficient to gain = 0.8 V/V and so forth. See Table 11 for the stored location of each gain-dependent coefficients. The selected channel for read/write register configuration is indicated by using the pointer position. The position is displayed in bit CONFIG_CH_PTR[3:0]. Similarly, the active ADC conversion on channel-pointer position is shown in bit ADC_CONV_CH[3:0] SPI command CMD_RELOAD will reload the factory calibrated coefficients from internal non-volatile memory into registers GAIN_COEF, OFFSET_COEF and SELF_CAL_COEF. This will overwrite previously modified values. When CMD_RELOAD is issued, the status bit SYS_STATUS0.CHIP_READY will be deasserted. It will then be asserted when NVM data reloading is complete.

7.3.7 Temperature coefficient correction

TCC_OFF = 0 enables a temperature coefficient correction that reduces the temperature drift error. Set this bit to 1 to disable the TCC feature for any of the following three situations:

REF_EXT is used
The ratiometric measurement is used with internal reference (SYS_CONFIG0.REF_SEL[1:0] = 00h)
The following input signals are used: REFH (= VREF*0.92), REFL (= VREF*0.08)

7.3.8 Voltage reference

7.3.8.1 Low-drift voltage reference 1

The NAFE11388 integrates a voltage reference with calibrated TCC coefficients to reduce the drift error over temperature. Set register bits TCC_OFF = 0 to apply TCC coefficients for non-ratiometric measurement. If external voltage reference is used as ADC reference, set TCC_OFF = 1.

7.3.8.2 Coarse voltage reference 2

The NAFE11388 includes a second and independent internal coarse voltage reference for diagnostic purpose. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.3.8.3 Voltage reference selector

7.3.9 Temperature sensor

warning and shutdown factory defaults are 145 ℃ and 165 ℃, respectively.

7.3.10 General-purpose input/output

0 V to VDD when pins GPIO0..9 are configured as GPIO. Figure 11. General-purpose input/output GPIO pins for either out or input function as programmed by user. data from PAD, looping back from GPO_DATA register and/or GPIO edges detection. respectively, are implemented as follows. set to 1 (W1C) by the previous event. Some GPIOs, such as GPIO0, GPIO1, GPIO2, and GPIO9 serve dual functions. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

LVMUXIN multiplexer. The input common voltage range is from 0.5 V to 2.5 V. SYS_CONFIG0.MCLK_OUT_ENABLE. GPIO2 can provide CRC_ERROR status flag by writing '1' to SYS_CONFIG0.CRC_EN.

7.3.11 Clock sources

Figure 12 shows the clock architecture. Figure 12. Clock architecture

7.3.11.1 Internal RC oscillator

operation without support of any external clock source. The internal oscillator nominal frequency is 18.432 MHz.

7.3.11.2 Oscillator with external crystal

7.3.11.3 External oscillator

as well as coherent sampling of the input signal. The external oscillator should be applied to pin EXTCLK/XI. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

7.3.11.4 Clock selection

The NAFE11388 provides two mechanisms for system clock source selection:

Auto-selection upon power on
User selection via system register configuration

7.3.11.5 Auto-selection of clock source

The automatic clock selection detects the presence of either the crystal oscillator or an external clock pulse upon power up and switches over to the available clock source. The first phase detects if the clock is present at XI pin, by expecting at least 256 clock pulses within a 1 ms window. If the first detection phase is true, then the second detection is skipped and the logic sets the SRC_SEL[1:0] to 2’b10. Detection is complete at this point with the external clock used as the system clock. When the first phase detection is not true, the second phase is set to detect if the crystal is installed. The logic looks for at least 256 clock pulses within a 31 ms window. If the second phase detection is true, the logic sets the SRC_SEL[1:0] to 2'b11. Detection is complete at this point with the external crystal set as the system clock. If both phases of detection are not true, the SRC_SEL [1:0] is not updated. It remains at the default 2’b00, which implies the internal clock is used. Then, CLK_DET_DONE is asserted 1 when both phases are complete. After CLK_DET_DONE = 1, the internal digital CHIP_RDY is asserted to 1.

7.3.11.6 User selection of clock sources

The user selection option allows the user to select the desired clock after power on. The clock source can be selected by writing to the clock source system configuration register. Check the presence of the external clock while making external clock selection in system configuration register to ensure proper functioning of the NAFE11388. If the external clock is detected and the NAFE11388 switches to the external clock, the system status register is updated accordingly. If the external clock is not detected, the NAFE11388 maintains the previous clock configuration.

7.3.11.7 Clock period drift detection

Whenever SRC_SEL[1:0] is set to 2’b11 or 2’b10 by the user or by the auto-detect logic, one-time switch over at power-on reset (POR), the clock period monitoring circuit is activated to continuously measure the clock period difference between the external clock and internal RC Oscillator. The typical value of clock period difference is set to 20 % at POR. The clock comparison logic issues an alarm when the running average clock count difference is greater than 20 %. The internal oscillator clock is the main reference. The alarm status bit for clock variation is user accessible via SPI register. The average time window is ~128 ms. If external clock is selected to be used as the system clock source and while EXTCLK_FREQ_ALRM bit is enabled, the external clock alarm interrupt triggers (EXTCLK_FREQ_INT = 1) whenever the EXTCLK is over the 20 % period difference. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.4 Channel configuration and multichannel sequencer

7.4.1 Channel configuration

Figure 13. Logical channel structure

Channel configuration registers: CH_CONFIG0, CH_CONFIG1, and CH_CONFIG2. – CH_CONFIG0 (0x20\\h) – Select input channel, either high voltage (HV_AIP/HV_AIN, HV_SEL=1) or low voltage (LVSIG_IN[2:0], HV_SEL = 0). – Select one of the eight channel gains if high-voltage input is selected. – Disable/enabled the channel temperature coefficients correction (TCC_OFF = 1). – CH_CONFIG1 (0x21\\h) – Set the pointer (CH_CAL_GAIN_OFFSET[3:0]) to select one of the 16 calibrated gain and offset coefficient pairs in the calibrated channel coefficient registers: GAIN_COEF0…15 and OFFSET_COEF0…15. – Set the pointer (CH_THRS[3:0]) to select one of the 16 channel over- and under-range threshold pairs: CH_CONFIG5.OVR_THRS0…15 and CH_CONFIG6.UDR_THRS0…15. – Select one of 29 possible data rates: ADC_DATA_RATE[4:0]. – Select one of the five possible filter options for second-stage SINC filter: ADC_SINC[2:0]. – CH_CONFIG2 (0x22\\h) – Select one of the 64 possible preset channel delays before ADC start conversion: CH_DELAY[5:0]. – Select ADC Settling mode, single-cycle, or normal: ADC_NORMAL_ SETTLING. – Select to reset ADC digital filters at the start of every ADC conversion: ADC_FILTER_RESET. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE – Select to enable input channel level chopping with two ADC conversions (Precision mode): CH_CHOP = 1.

Channel gain coefficients: GAIN_COEF0..15 [23:0] (0x80 – 0x8F) – These 16 24-bit calibrated gain coefficients are used to correct the gain error for the selected logic channel. The uncalibrated default is equivalent to 1 V/V.
Channel offset coefficients: OFFSET_COEF0..15[23:0] (0x90 – 0x9F) – These 16 24-bit calibrated offset coefficients are used to correct the offset error for the selected logic channel. The uncalibrated default offset value is 0 V.
Channel input range detect threshold – CH_CONFIG5 (0x50..0x5F): Over-range 24-bit threshold setting These 16 24-bit registers are used to set the over-range threshold values. – CH_CONFIG6 (0x60..0x6F): Under-range 24-bit threshold setting These 16 24-bit registers are used to set the under-range threshold values.
Channel output data – CH_DATAi[23:0]: Holds ADC converted output data as selected by CMD_CHi. CH0 data is address 0x40 and CH15 data address is 0x4F.
Channel status – CH_STATUS0[i]: Over-range status bit. CH0 status is in bit[0] and CH15 is in bit[15]. – CH_STATUS1[i] - Under-range status bit. CH0 status is in bit[0] and CH15 is in bit[15]. Upon startup, chip reset, and register clear, each of the logical channels is to be reconfigured once. Channel gain/offset coefficients are preloaded from the on-chip NVM after POR. The user could overwrite these coefficients after the POR. Channel select, CMD_CHi :
SPI command CMD_CHi is used to select the logic channel CHi, and the CH_DATAi, where i = 0..15 is the channel index.
Channel configuration is activated after the conversion command is issued.
The activated logical channel is indicated by reading CONFIG_CH_PTR[3:0] in SYS_STATUS0 register. For single-channel conversion, the host will issue (CMD_SS, CMD_SC), then wait for DRDY signal asserted high where ADC data is ready for the host to read. Figure 14 shows a typical sequence before CMD_SS or CMD_SC is issued. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

enabled logical data channel(s). enabled logical data channel(s). Figure 14. Steps to setup for single-channel conversion reading following setup and the conversion result will be stored at CH_DATA5. Example how to select, config, enable, run, read data. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

7.4.2 Working with multichannel sequencer

The sequencer will step through CH0 to CH15 (or current channel to CH15) to execute the enabled channels (CH_CONFIG4.MCH_EN[15:0]) and store ADC output in the corresponding ADC_DATA output register (CH_DATA0..CH_DATA15). ADC conversion can be set either to Single-Cycle Settling mode or Normal Settling mode with CH_CONFIG4.ADC_SINGLE_NORMAL = 0 or 1, respectively. However, single- cycle settling is typically preferable in many applications. When CMD_MM or CMD_MC command is issued, the sequencer will begin ADC conversions on the enabled channels and stop upon completing the conversion of the last enabled channel. At the end of the Sequencer mode, SYS_STATUS0.ADC_CONV_CH[3:0] is set to CH0. The DRDY pin will transition from 0 to 1 when ADC_DATA is ready for the host to read. The register SYS_STATUS0.ADC_CONV_CH[3:0] can be used for tracking the current ADC channel. ADC busy status is indicated in either status bit SYS_STATUS0.SINGLE_CH_ACTIVE or SYS_STATUS0.MULTI_CH_ACTIVE. expected behavior of the sequencer with the use of SYNC pulse and reading command as triggers. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

enabledlogical datachannel(s). enabledlogical datachannel(s). for enabledlogical channel(s). for enabledlogical channel(s). Figure 15. Steps to setup for multichannel conversion reading

7.4.2.1 Channel enable

in multichannel sequencer conversions. channels are enabled in multichannel sequencer conversions.

7.4.2.2 On-the-fly channel configuration

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Note: Any register setting changes on ADC active channel (SINGLE_CH_ACTIVE or MULTI_CH_ACTIVE) will not be taken into effect until next ADC conversion command CMD_ is issued.

7.5 ADC Conversion and Reading modes

The NAFE11388 reading process starts when a start event is received, and finishes with an event that signals the completion of reading. The reading process includes four main steps: 1. Reading start event received. 2. Wait a period equal to the configured programmable delay. 3. Execute one or more analog-to-digital conversions. 4. Send the DRDY signal when the reading process is complete.

7.5.1 Reading start event

The NAFE11388 provides two types of reading start event to fit simplicity and performance. One reading event is command based. It is intrinsic in the SPI command transaction. The other is triggered through SYNC pin. The SPI reading process starts on the last falling edge of the SPI command clock. The SYNC reading process begins on the rising edge of the SYNC pulse at the SYNC pin.

7.5.2 Reading process stop event

The reading process can be stopped by the host issuing either SPI commands or a SYNC pulse. This command is useful if the host wants to stop an infinite reading process executed autonomously by the NAFE11388. The SPI commands to stop reading in progress are CMD_ABORT or CMD_END.

7.5.2.1 CMD_ABORT

While the NAFE reading period is active and the ADC is converting, if a CMD_ABORT command is received, the ongoing conversion is aborted, and the device returns to its initial waiting state. The corresponding CH_DATA register will not be updated.

7.5.2.2 CMD_END

While the NAFE reading period is active and the ADC is converting, if CMD_END is received, ADC conversion is allowed to complete (contrary to CMD_ABORT) and CH_DATA register is updated with new results before device returns to its initial waiting state.

7.5.3 Reading period

The reading period is defined as the time interval between the reading start event and the reading end event. If SYS_CONFIG0.ADC_SYNC = 0, the conversion start event is the last falling edge of the SPI command clock. If SYS_CONFIG0.ADC_SYNC = 1, the conversion start event is the rising edge of the SYNC pulse. The reading completion event is the rising edge of the DRDY signal. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

readings after first reading.

Single-channel single-reading (SCSR)
Single-channel continuous-reading (SCCR)
Multichannel single-reading (MCSR)
Multichannel multireading (MCMR)
Multichannel continuous reading (MCCR) The system clock frequency is 4.608 MHz. The period of system (T_sys_clk) is 1/(4.608 MHz) = 217 ns with the master clock at 18.432 MHz. Master clock 18,432,000 System clock 4,608,000 Prog delay code Prog delay (# sysclk) Programmable delay(s) 0 0 000.000E+0 1 2 434.028E-9 2 4 868.056E-9 3 6 1.302E-6 4 8 1.736E-6 5 10 2.170E-6 6 12 2.604E-6 7 14 3.038E-6 8 16 3.472E-6 9 18 3.906E-6 10 20 4.340E-6 11 28 6.076E-6 12 38 8.247E-6 13 40 8.681E-6 14 42 9.115E-6 15 56 12.153E-6 16 64 13.889E-6 17 76 16.493E-6 18 90 19.531E-6 19 128 27.778E-6 20 154 33.420E-6 21 178 38.628E-6 22 204 44.271E-6 23 224 48.611E-6

Table 15. Channel programmable delay...continued

7.5.3.1 Calculate the effective reading period

are provided in the Reading mode sections.

7.5.3.2 Fastest reading period in SCCR mode

it is possible to achieve a data rate up to 288 ksps.

7.5.3.3 Effective output data rate with CH_DELAY

programmable delay, CH_CONFIG2.CH_DELAY[5:0]. Table 16 shows examples of the most common reading periods. Table 16. Popular reading periods NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7.5.4 ADC synchronization

Synchronize multi NAFE with SYNC pulse at SYNC pin
Synchronize the NAFE to host for conversion start by SYNC pulse
Synchronize the host to the NAFE through DRDY signal
Synchronize the NAFE and the host clock to the same clock, by one of the following methods: – Configure the NAFE to use external clock and apply 18.432 MHz clock pulses at EXTCLK/XI pin – Configure the NAFE to output its system clock to GPIO9

7.5.4.1 ADC_SYNC bit

start is only triggered by a rising edge at the SYNC pin. and SYS_CONFIG0.ADC_SYNC is set to 1.

Select the Reading mode
Trigger the conversion start The conversion start with SYNC pulse is supported in all Reading modes. Table 17 summarizes the Reading mode and start commands. Conversion start trigger ADC_SYNC = 0 ADC_SYNC =1 SCSR CMD_SS SYNC pin SCCR CMD_SC SYNC pin MCSR CMD_MS SYNC pin MCMR CMD_MM SYNC pin Reading modes MCCR CMD_MC SYNC pin Trigger event on CMD_xy is the last SPI command falling edge check Trigger event on SYNC pin is the pulse rising edge

Table 17. Reading mode and start commands

7.5.4.2 Synchronize multi-NAFE with SYNC pulse at SYNC pin

all the connected devices start the conversion on the rising edge of the SYNC pulse.

7.5.4.3 Synchronize NAFE to host with SYNC pin

The SYNC input enables the host to control the start conversion of the NAFE. Consequently, this provides a synchronization mechanism driven by the host. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7.5.4.4 Synchronize the host to the NAFE through DRDY signal

critical for synchronizing the reading time for an infinite reading loop.

7.5.4.5 Synchronize the NAFE and host to the same clock

Apply an external 18.432 MHz master clock to XI/EXTCLK pin and set SYS_CONFIG0.CK_SRC_SEL[1:0] = 1. This enables coherent measurements and the possibility to synchronize the SPI data fetching using this clock as a timer.
Use internal 4.608 MHz system clock at GPIO9 pin configuring SYS_CONFIG0.MCLK_OUT_ENABLE = 1 in SYS_CONFIG0 register. This implementation enables synchronization to the NAFE so the host can synchronize the SPI data fetching using this clock as a timer.

7.5.4.6 Reading conversion start - SYNC pulse

of the SYNC pulse at the pin. SYNC pulse width should be a minimum of two system clock cycles. reading period for the second reading and beyond. SYNC pulse triggers the conversion start for all the reading modes.

1 CMD_SCP

Figure 16. Conversion start

7.5.5 Reading modes

Single-channel single-reading (SCSR) set by the CMD_SS command
Single-channel continuous-reading (SCCR) set by the CMD_SC command
Multichannel single-reading (MCSR) set by the CMD_MS command
Multichannel multireading (MCMR) set by the CMD_MM command

Multichannel continuous-reading (MCCR) set by the CMD_MC command

The following sections describe the reading modes in details.

7.5.6 Reading sequence

Figure 17. Reading modes

Idle state. Wait for a start event: SPI start command or SYNC pulse
Update the active channel configuration and pointer location (as needed)
Wait for the timer of programmable delay to expire
Start and complete ADC conversion on the selected channel, check active converting
Loop increment for Continuous-Reading and Multireading modes:

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE c. In Multireading mode: MCMR – ADC jumps to Step 2 until the reading completion of the last enabled channel defined in CH_CONFIG4.MCH_EN[15:0]. The loop is then broken and ADC returns to Step 1. In Single-Reading mode SS mode, the host issues the conversion start by sending CMD_SS if SYS_CONFIG0.ADC_SYNC = 0, or the SYNC pulse if SYS_CONFIG0.ADC_SYNC = 1. After the NAFE completes the reading conversion process, it returns to idle and waits for the next instruction command or next SYNC pulse. In Continuous-Reading SCCR and MCCR modes, the host issues the conversion start by sending CMD_SC, CMD_MC, or the SYNC pulse (when SYS_CONFIG0.ADC_SYNC = 1 is set). After the NAFE completes first reading conversion process, it jumps to Step 2 and continues the reading process forever or until is interrupted. There are three ways to interrupt an ADC conversion: 1. CMD_END: Stop ADC conversion reading process after the current conversion is completed. 2. CMD_ABORT: Abort the ADC conversion reading process immediately. 3. Conversion start event: a. If SYS_CONFIG0.ADC_SYNC = 0, the last falling edge of SPI command restarts a new conversion. A pulse at the SYNC pin is ignored. b. If SYS_CONFIG0.ADC_SYNC = 1, a rising edge signal at SYNC pin will trigger ADC a new conversion start.

7.5.7 CMD_SS (single-channel single-reading)

Start Single-Channel Single-Reading (conversion) mode. If SYS_CONFIG0.ADC_SYNC = 0, the conversion start is triggered by this SPI command at the last SPI clock falling edge. If SYS_CONFIG0.ADC_SYNC = 1, the conversion start is triggered by SYNC rising edge. In both cases, the conversion is executed on the selected channel. After the conversion is complete, the device returns to its waiting state. Data can be read serially via the MISO pin after the DRDY pin asserts high, or after the reading process is complete. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.5.7.1 Flow chart - SCSR

7.5.7.2 Timing diagram - SCSR

Keep the CSB low after the command was issued. Then wait for DRDY assert high. Data is available at the MISO pin at every rising of SCLK. MSB outputs first.
Deassert the CSB high, then wait until the DRDY goes high and read the channel data. aaa-046695 ADCdata[23:0] CSB SCLK MOSI ID 1 16 1 16 1 24 DRDY

1 CMD_SS

Figure 19. CMD_SS timing diagram with CSB high

2 T_Sys_clk

1 XCMD_SS

Figure 20. CMD_SS timing diagram with CSB low

7.5.7.3 Code example - SCSR

7.5.7.4 Reading period for SCSR

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Hence,

7.5.8 CMD_SC (single-channel continuous-reading)

Start Single-Channel Continuous-Reading (conversion) mode. If bit SYS_CONFIG0.ADC_SYNC = 0, the conversion start is triggered by this SPI command at the last clock falling edge. If bit SYS_CONFIG0.ADC_SYNC = 1, the conversion start is triggered by SYNC rising edge. In both cases, the conversion is executed on the selected channel until it is interrupted or restarted. The conversion could be interrupted by CMD_ABORT or CMD_END, or could be aborted and restarted by a SYNC pulse if SYS_CONFIG0.ADC_SYNC = 1 or any conversion command if SYS_CONFIG0.ADC_SYNC = 0. Data can be read serially via the MISO pin after the DRDY pin asserts high or after the reading is completed. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.5.8.1 Flow chart - SCCR

7.5.8.2 Timing diagram - SCCR

Keep the CSB low after the command was issued. Then wait for DRDY pin assert high and read the channel data. Data is available at MISO pin at every rising of SCLK. MSB outputs first.
De-assert the CSB high, then wait until the DRDY goes high and read the channel data. aaa-046697 * ThepulsewidthofDRDYcanbeprogrammedviaDRDY_PWDTbitinSYSTEM_CONFIG0bit15.0:2systemclocksand1:8systemclocks * NoteNAFEreading1stperiodislongert+2sys_clkofthesuccessiveNAFEreading CSB SCLK MOSI ID 1 16 1 24 1 24 1 24 DRDY

1 CMD_SC

Figure 22. CMD_SC timing diagram CSB low/high

7.5.8.3 Code example - SCCR

7.5.8.4 Reading period for SCCR

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE T_sys_clk =1/sys_clk = 1/4608000 = 0.217 us T_prog_delay = 76 * T_sys_clk #Table Channel Programmable Delay T_conv = 1/12000 = 83.3 us #Table Data Rate Hence, On first reading, T_reading = 0.217 us * ( 2 ± 1 + 76 ) + 83.33 us = 100.3 ± 0.217 us On subsequent readings, T_reading = 0.217 us * ( 0 + 76 ) + 83.33 us = 99.83 us.

7.5.9 CMD_MM (multichannel multireading)

Start Multichannel Multireading (conversion) mode. If SYS_CONFIG0.ADC_SYNC = 0, the conversion start is triggered by this SPI command at the last clock falling edge. If SYS_CONFIG0.ADC_SYNC = 1, the conversion start is triggered by SYNC rising edge. After first conversion, the sequencer will start conversion by sequencing on the enabled channel set via CH_CONFIG4.MCH_EN[15:0] register, from CH0 to CH15. Upon the completion of the last enabled channel, the device returns to waiting state. The conversion could be interrupted by CMD_ABORT or CMD_END, or could be aborted and restarted by SYNC pulse if SYS_CONFIG0.ADC_SYNC = 1 or any conversion command if ADC_SYNC = 0. If an SPI conversion command or a SYNC pulse is issued before completion of the current conversion, ADC aborts the conversion immediately and restarts the conversion starting from first enabled channel. Data can be read serially via the MISO pin after the DRDY pin asserts high or after the reading is completed. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.5.9.1 Flow chart - MCMR

CMD_CHi =N; where N= 0...15. Figure 23. Flow chart MCMR

7.5.9.2 Timing diagram - MCMR

1 CMD_MM

Figure 24. Timing diagram - MCMR

7.5.9.3 Code example - MCMR

7.5.9.4 Reading period for MCMR

7.5.10 CMD_MC (multichannel continuous-reading)

Start Multichannel Continuous-Reading (conversion) autonomous mode. The CMD_MC is similar to CMD_MM with infinite loop until it is interrupted or restarted. CMD_MC sets multichannel continuous-reading (conversion) mode. at the last clock falling edge. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE If SYS_CONFIG0.ADC_SYNC = 1, the conversion start is triggered by SYNC rising edge. After first conversion, the sequencer will start conversion by sequencing on the enabled channel set via CH_CONFIG4.MCH_EN[15:0] register, from CH0 to CH15. After the conversion completion of the last enabled channel, the device restarts a new cycle in an infinite loop. The conversion could be interrupted by CMD_ABORT or CMD_END; or could be aborted and restarted by SYNC pulse if SYS_CONFIG0.ADC_SYNC = 1 or any conversion command if SYS_CONFIG0.ADC_SYNC = 0. If an SPI conversion command or a SYNC pulse is issued before completion of the current conversion, ADC aborts the conversion immediately and restarts the conversion, starting from first enabled channel. Data can be read serially via the MISO pin after the DRDY pin asserts high or after the reading is completed. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.5.10.1 Flow chart - MCCR

CMD_CHi =N; where N= 0...15. Figure 25. Flow chart - MCCR

7.5.10.2 Timing diagram - MCCR

Figure 26. Timing diagram - MCCR

7.5.10.3 Code example - MCCR

7.5.10.4 Reading period for MCCR

On subsequent readings, T_fixed = 0.

7.5.11 CMD_MS (multichannel single-reading)

Start Multichannel Single-Reading (conversion) mode. at the last clock falling edge. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Upon completion of each ADC conversion, the logic channel pointer is auto-incremented to the next enabled channel and awaits the arrival of a conversion start trigger. The ADC loops back to the first enabled channel when the last enabled channel is complete. This reading mode could be terminated by issuing the CMD_END or CMD_ABORT. If SYNC pulse or same conversion command is issued before completion of the conversion on the current channel, ADC aborts the conversion immediately and restarts the conversion on the current channel. (This is different from MM and MC modes, which restart on the first enabled channel) Data can be read serially via the MISO pin after the DRDY pin asserts high or after the reading is completed. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.5.11.1 Flow chart - MCSR

7.5.11.2 Timing diagram - Flow chart - MCSR

Figure 28. Timing diagram - Flow chart - MCSR

7.5.11.3 Code example - Flow chart - MCSR

7.5.11.4 Reading period for MCSR

7.6 ADC code to voltage translation

LVMUX diagnostic voltage readout is scaled with a fixed gain of 2.5. The temperature sensor 16-bit code continuous readout is independent of main the ADC. The code to temperature translation is provided in Table 18. Table 18. ADC code conversion formulas

7.7 Diagnostic features

available, as described in the following sections.

15 OVER_TEMP_ALRM RW 0x0 Overtemperature warning at 145 °C

14 HVDD_ALRM RW 0x0 Enable alarm for HVDD supply detect below preset threshold. 13 HVSS_ALRM RW 0x0 Enable alarm for HVSS supply detect above preset threshold. 12 ADVDD_ALRM RW 0x0 Enable alarm for DVDD supply detect below preset threshold. Table 19. Alarm and interrupt NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

10 GPI_POS_ALRM RW 0x0 Enable alarm for rising edge detected at any GPI pins. 9 GPI_NEG_ALRM RW 0x0 Enable alarm for falling edge detected at any GPI pins. 8 CONFIG_ERROR_ALRM RW 0x0 Enable alarm for register configuration error.

7 OVRRNG_ALRM RW 0x0 Enable alarm when one or more data channels is over-range

6 UNDRNG_ALRM RW 0x0 Enable alarm when one or more data channels is under-range.

5 OVRLOAD_ALRM RW 0x0 Enable alarm when one or more data channels is overloaded

4 EXTCLK_FREQ_ALRM RW 0x0 Enable alarm when EXTCLK or XTAL clock period deviates >

20 % from 18.432 MHz INTOSC. threshold is set in THRS_TEMP register bit.

15 OVER_TEMP_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

14 HVDD_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 13 HVSS_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 12 ADVDD_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 10 GPI_POS_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 9 GPI_NEG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 8 CONFIG_ERROR_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 7 OVRRNG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 6 UNDRNG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 5 OVRLOAD_ALRM RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 4 EXTCLK_FREQ_ALRM RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. 0 TEMP_ALRM RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY. Table 19. Alarm and interrupt...continued The alarm clearing behavior is determined by GLOBAL_ALRM_STICKY.

7.7.1 Input under-range and over-range

thresholds for under- or over-range detection based on its ADC output. OVRRNG_INT = 1 and UNDRNG_INT = 1, respectively. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7.7.2 REFH and REFL for diagnostic

as a reference channel or channel self-test in the field.

7.7.3 Voltage supply rail monitoring

7.7.4 Thermal monitoring and thermal shutdown

warning interrupt, TEMP_INT. The NAFE includes a thermal shutdown circuit to protect the device from overheating. The thermal monitoring circuit asserts an alarm if the temperature is in the range 145 ⁰C. The circuit resets the chip when the junction temperature reaches 165 ⁰C.

7.7.5 Alarm

internal oscillator clock is more than 20 %. GPI_ENABLE, GPI_EDGE_POS, GPI_EDGE_NEG.

7.7.6 Interrupts

prepended with channel-specific status byte, by enabling SYS_CONFIG0.STATUS_EN. Each of the status bit is OR’s of all 16 channels. The logic equivalence is shown in Figure 29. Figure 29. Interrupt NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Each individual status bit is concatenated in single byte listed in Table 20. Table 20. Status byte description CMD_CLEAR_DATA or CMD_CLEAR_REG. cleared until the host issues CMD_CLEAR_DATA or CMD_CLEAR_REG. status bits are ADC underload/overload, ADC over-range and ADC under-range. Note: Writing 1 to the bit that is 0 in GAI register, will not alter it to 1. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Figure 30. Alarm meaning interrupt comes and goes regardless of GAI register read or not.

7.7.8 Configuration or loading error

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

7.8 SPI interface and controls

7.8.1 SPI signal pins

The SPI-compatible serial interface is used to read the conversion data, internal register content and to configure the device and control the ADC. The serial interface consists of four signals: CSB, SCLK, MOSI, and MISO. One external pin, SPI_ADDR, is used as SPI address such that the host can address two devices without using a separate CSB pin. In addition, DRDY and SYNC signals allow the handshaking and data synchronization between the host and the device. The conversion data are provided with an optional CRC code for improved data integrity. 24-bit ADC word can be read with and without 8-bit CRC appended at the end of data. The SPI pin functions are described in the following sub-sections.

7.8.1.1 CSB (active low)

CSB is an input pin that enables the communication between the host and the chip. CSB must remain low for the entire data transaction. When CSB is set to high, the serial interface is reset, SCLK input and command inputs are ignored.

7.8.1.2 SCLK

SCLK is the serial interface clock that operates up to 32 MHz. It is a noise-filtered, Schmitt-triggered input used to clock data in and out of the chip. Serial input data is latched in the falling edge of SCLK and serial data outputs from the chip are updated on the rising edge of SCLK.

7.8.1.3 MOSI

MOSI is the serial data input to the chip. MOSI is used to input commands and register data to the chip.

7.8.1.4 MISO

MISO is the serial data output from the chip. MISO data contains: internal registers data, ADC results, status byte, and/or 8-bit CRC if CRC_EN and/or STATUS_EN are set to 1, respectively. When CSB is high, MISO is in high-impedance. When CSB is low, MISO is updated on the rising edge of the SCLK.

7.8.1.5 SPI_ADDR

SPI_ADDR is an additional input pin used to address a second device with a single CSB to reduce the number of chip select signals required.

7.8.1.6 DRDY

DRDY (rising edge) is an output pin that indicates the conversion status. DRDY is driven to high when the new conversion result is stored in the SPI buffer and ready for reading. DRDY pulse stays high for 2 x T_sys_clk if SYS_CONFIG0.DRDY_PWDT bit = 0. Otherwise, the pulse stays high for 8 x T_sys_clk if DRDY_PWDT bit = 1. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

7.8.1.7 SYNC

high transition on the SYNC pin given that the SYS_CONFIG0.ADC_SYNC bit = 1. The minimum width of SYNC pulse should be 2 x T_sys_clk.

7.8.1.8 INTB (active low)

7.8.2 SPI communication protocols

to the device or the device to the host depending on write or read operation, respectively. RW_L should be set to 0 for write, whereas it should be 1 for read. Figure 31. SPI write timing Figure 32. SPI read timing

7.8.2.1 Write without CRC

transaction. SPI write command is used to configure the internal registers of the chip. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

0xA5 to D23-D16 (bit location 23 to 16) of register 0x0020. Figure 33. Write without CRC

7.8.2.2 Read without CRC

The second bit after the first SPI bit frame "RW_L" is 1 indicates it is a read transaction. Figure 34. Read without CRC

7.8.2.3 CRC-8 generator

y = x8 + x2 + x + 1 equivalent to binary number is 100000111. on the data transfer operation. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

SYS_CONFIG0.CRC_ERROR_ON_GPIO2 is set to 1. SYS_STATUS0.CRC_ERROR bit is cleared upon reading.

7.8.2.5 Write with CRC

For 16-bit register write: The host first calculates the 8-bit CRC_A on 16-bit address and appends the 8-bit CRC_A after the address. The host then calculates the 8-bit CRC_D on 16-bit data and appends the 8-bit CRC_D after 16-bit data.
For 24-bit register write: The host first calculates the 8-bit CRC_A on 16-bit address and appends the 8-bit CRC_A after the address The host then calculates the 8-bit CRC_D on 24-bit data and appends the 8-bit CRC_D after 24-bit data. In both cases, the host should send an extra 8-bit clock to receive back the calculated CRC_D from the device. The 16-bit address register includes device ID bit, RW_L bit, RA bits, and don’t care bit (0). CSB SCLK MOSI MISO aaa-046711 ID 1 16 17 24 25 40 41 48 49 56

0 X CRC-2 CRC-2 (WDATA) 0X0WDATA[15:0]

*CRC-2 =2 byte is calculated by Host to produce CRC-2. Figure 35. Host writes to register 16-bit with CRC enabled

0 X CRC-2 CRC-3 (WDATA) 0X0WDATA[23:0]

*CRC-2 =2 byte is calculated by Host to produce CRC-2. Figure 36. Host writes to register 24-bit with CRC enabled

7.8.2.6 Read with CRC

data from the 16-bit register.

1 X CRC-2

Figure 37. Host read data from the 24-bit register

7.8.2.7 System configuration with CRC

Two-byte command: Two-byte command format with no data return.

The figure below shows the timing of two-byte command with non-return ADC data.

Command examples: CMD_CH0, … CMD_CH15, CMD_ABORT, CMD_END, CMD_CLEAR_ALARM, CMD_CLEAR_DATA, CMD_RESET, CMD_REOAD The host calculates the CRC of the two-input command bytes. Device CRC-2 byte is calculated by device, output based on the two received command bytes. If the two CRC values match, the command is executed at the beginning of the last falling edge of SCLK of the fourth byte in the sequence. Asserting CSB high before the command completes will result in command termination. When a new command starts, the device must see the CSB transition from high to low. If both CRC_EN, and STATUS byte output format are enabled, then the CRC calculation includes status byte plus the ADC conversion data, CRC4 for 24-bit ADC and CRC3 for 16-bit ADC. CSB aaa-046714 *CRC-2 =2 byte is calculated by Host toproduce CRC-2. Thetwo byte (16 bits) includes ID, RW, Command and Xbit SCLK Device CRC-2Z Status[7:0] ADCn[23:0] ADCn+1[23:0]CRC4 *CRC-4= 4byte is calculated by Deviceon the Status[7:0] +ADC[23:0] to produceCRC-4 CRC-4Status[7:0] MOSI MISO ID RW_L X CRC-2 00hCommand 16 17 24 25 32 40 64 65 73 81 82 105 1124133 DRDY CMD_SSends at this clock edge

Figure 38. Conversion command data read operation 2/24-bit ADC, CRC_Enable = 1, Figure 39. Regular read 24-bit data with CRC_EN = 1 NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

CRC-2 means 2 byte is calculated by Host to produce CRC-2. Figure 40. Two-byte command format with return data Two-byte command: Two-byte command format with data return. A return data command, including register read command, RW_L bit is always set to 1. Figure 41 shows the timing of two-byte command with ADC data return.

Command examples: CMD_SS, CMD_SC, CMD_MM, CMD_MC, and CMD_BURST_DATA The host calculates CRC of the two-input bytes and sends the CRC-2 after the 16-bit command. Device CRC-2 byte is calculated by device, output based on the two received command bytes. If the two CRC values match, the command is executed. After the host sends CRC byte, it can continue to send eight more clocks to get the device calculated CRC before DRDY goes high. The host can keep the CSB low, while waiting for DRDY to assert HI, then provide the number of clocks required to retrieve the ADC conversion data along with its respective calculated CRC. If the device is 24-bit ADC, then CRC calculation will be based on three ADC bytes. If the device is 16-bit ADC, then CRC calculation will be based on two ADC bytes. CSB DRDY SCLK MOSI MISO aaa-046717 ID 1 16 17 24 25 32 00h 33 56 57 64 65 97 9889 CMD_SSends at this clock edge 128121 RW_L X CRC-2 Device CRC-2 ADCn [23:0] ADCn+1[23:0] ADCn+2[23:0] *CRC-2 = 2byte is calculated by Host to produceCRC-2. Thetwo byte (16bits) includes ID, RW, Command, and Xbit *CRC-3 =3 byte is calculated by Device on the ADC[23:0] toproduce CRC-3 CRC-3CRC-3 CRC-3Z Command

Figure 41. Conversion command data read operation 2/24-bit ADC, CRC_ENABLE = 1,

7.8.3 SPI programming and commands

summary of all the instruction commands. offset at address 0x20\\h and RA5 bit is always set to 1 when accessing the registers.

7.8.3.1 Commands definition

7.8.3.1.1 CMD channel selection

Table 21. CMD channel selection

7.8.3.1.2 CMD initialize/clear

Chip power-on reset (POR)
RSTB accessible by pulling the pin to ground
CMD_RESET Hardware reset is achieved by pulling pin RSTB = 0 V or POR. When in reset, all HV input pins and GPIO pins are in high-Z input mode, internal voltage reference is used, ADC digital filters are cleared, all user registers are set to their default values and all NVM shadow register content will be reloaded. The input clock source will be defaulted back to internal RC oscillator and go through autoclock switching within 50 ms if the external clock is applied or crystal is installed. CMD_RESET is the same as the hardware reset by pulling RSTB pin down to GND. Issuing the CMD_CLEAR_ALARM command clears GLOBAL ALARM INTERRUPT bits at register address: 0x33\\h. Issuing the CMD_CLEAR_DATA command will clear all channel data (CH_DATA0 – CH_DATA15) registers to 0x000000. Issuing the CMD_CLEAR_REG command clears the user registers, except the clock source select, SYS_CONFIG0.CK_SRC_SEL [1:0]. The clock source select bit does not get cleared even if they are part of the user’s registers. The user can change this register after POR, while any conversion is in active. For instance, if CK_SRC_SEL held a value other than 0 before the command was issued, it would stay the same after this command was issued. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

Note: CRC_EN is also cleared. Issuing the CMD_RELOAD command reloads NVM contents to shadow registers. coefficients. This command does not reset user registers. Table 22. CMD initialize/clear

7.8.3.1.3 CMD reading modes

Table 23. CMD reading modes the conversion is executed on the selected channel until it is interrupted or restarted. 0, the conversion start is triggered by this SPI command at the last clock falling edge. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7.8.3.1.4 CMD burst data

Table 24. CMD burst data CH15 sequentially (determined by MCH_EN[15:0] bits). Note: If MCH_EN = 0x8000, data in CH_DATA15 is read. Figure 42. Burst data command NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

7.8.3.1.5 CMD CRC

Table 25. CMD CRC CMD_CALC_CRC_CONFG: Calculate CRC sum for all 16-bit user configuration registers and save result to 0x25\\h(CRC_CONFIG_REGS). CMD_CALC_CRC_COEF: Calculate CRC sum for all 24-bit CAL coefficient and threshold registers and save result to 0x26\\h(CRC_COEF_REGS). CMD_CALC_CRC_FAC: Calculate all factory OTP trim registers and save result to 0x27\\h(CRC_TRIM_INT[15:0]). register address at 0x25, 0x26, or 0x27 if CMD_CALC_CRC_CONFG, CMD_CALC_CRC_COEF, or CMD_CALC_CRC_FAC is used respectively.

7.8.3.1.6 Read/Write

1 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 eg: Read register CH_CONFIG0 :

0 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 eg: Write register CH_CONFIG0 :

Table 26. Read/Write

7.8.3.2 Channel data readback

Directly after conversion, read data is stored to the channel data register indicated by the rising edge of DRDY. The conversion result is automatically

transferred to the SPI data buffer while the host provides the SPI clock. However, the CSB needs to stay low after the start conversion event has been issued.

Read data from the channel data register. This requires a new SPI transaction that addresses and fetches the channel data register.

7.9 Register map

16-bit configuration and status registers NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

24-bit coefficient registers
24-bit or 16-bit data registers for 24-bit or 16-bit options 7.9.1 16-bit channel-based configuration CH_CONFIG0..2[15:0] are channel-based registers. Before reading or writing to CH_CONFIG registers of a channel, select the channel by issuing CMD_CHi to set Register(16-bit) Bit order Bit name RW Reset Short description 15:12 HV_AIP[3:0] RW 0x0 HV Positive input pin select: 0\\h = internal GND, 1\\h = AI1P, 2\\h = AI2P, 3\\h = AI3P, 4\\h = AI4P, 5\\h = REFH, 6\\h = REFL, 7\\h = AICOM, 8\\h = not used, 9\\h to F\\h = not used. 11:8 HV_AIN[3:0] RW 0x0 HV Negative input pin select: 0\\h = internal GND, 1\\h = AI1N, 2\\h = AI2N, 3\\h = AI3N, 4\\h = AI4N, 5\\h = REFH, 6\\h = REFL, 7\\h = AICOM, 8\\h = not used, 9\\h to F\\h = not used. 7:5 CH_GAIN[2:0] RW 0x0 Select the channel gain (V/V): 0\\h = 0.2x, 1\\h = 0.4x, 2\\h = 0.8x, 3\\h-7\\h = unused. 4 HV_SEL RW 0x0 Select HV or LV signals for ADC conversion: 0 = LVSIG_IN, 1\\h = HV_AIP-HV_AIN signals. 3:1 LVSIG_IN[2:0] RW 0x0 LV signals (pos, neg) select: 0\\h = (REF/2,REF/2), 1\\h = (GPIO0,GPIO1), 2\\h = (REF_Coarse,REF/2), 3\\h = (VADD,REF/2), 4\\h = (VHDD,REF/2), 5\\h = (REF/2,VHSS), CH_CONFIG0 0x20\\h

0 TCC_OFF RW 0x0 Proprietary Channel Temperature Coefficient Correction: 0\\h = TCC ON, 1\\h = TCC OFF

Coefficient Registers. See Table 13 . 11:8 CH_THRS[3:0] RW 0x0 Channel Over- and under-range threshold: See Table 28. previous conversion, 1\\h = reset digital filters. 15:0 MCH_EN[15:0] RW 0x0000 Enable logical configurable channel for ADC conversion in Sequencer mode: 0 = disable, 1 = enable. Table 27. 16-bit channel-based configuration NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Output data: DATA0..15
Over-range alarm threshold: OVR_THRS0..15
Under-range alarm threshold: UDR_THRS0..15
Factory or user-calibration gain coefficients: GCC0..15
Factory or user-calibration offset coefficients: OCC0..15 The non-channel based registers OPTC0..15 are optional coefficients used for storing factory calibrated parameters. Register (24-bit) Bit order Bit name RW Reset Short description CH_DATA0..15 0x40\\h - 0x4F\\h 23:0 DATA0[23:0] .. DATA15[23:0] R 0x00_0000 Channel output data. Each channel has a corresponding data register. DATA0[23:0] is converted output of CH0.. DATA15[23:0] is converted output of CH15. CH_CONFIG5 0x50\\h - 0x5F\\h 23:0 OVR_THRS0[23:0] .. OVR_THRS15[23:0] RW 0x00_0000 Over-range threshold setting for each logical data channel. CH_CONFIG6 0x60\\h 0x6F\\h 23:0 UDR_THRS0[23:0] .. UDR_THRS15[23:0] RW 0x00_0000 Under-range threshold setting for each logical data channel. GAIN_COEF0..15 0x80\\h-0x8F\\h 23:0 GCC[23:0] RW 0x Calibrated gain coefficients. The user may alter or update the values to fit their application. For each of the logical channel setup, these GAIN_COEF registers are indexed addressable by pointer set by register bits CH_CAL_GAIN_OFFSET[4:0]. Initially after CHIP_READY, the content of these registers are populated with factory-calibrated coefficients, refer to TABLE_FAC_COEF if applicable. Note: Whenever the chip is in RESET, the factory-calibrated coefficient is reloaded from OTP into the registers. These same registers are used for displaying the factory calibrated coefficient upon RESET in certain order. However, the user has full read/write access and may reshuffle the order and coefficient values according to user-configured channels. OFFSET_COEF0..15 0x90\\h-0x9F\\h 23:0 OCC[23:0] RW 0x Calibrated offset coefficients. The user may alter or update the values to fit their application. For each of the logical channel setup, these OFFSET_COEFF registers are indexed addressable by pointer set by register bits CH_CAL_GAIN_OFFSET[4:0]. Initially after CHIP_READY, the content of these registers are populated with factory-calibrated coefficients, refer to TABLE_FAC_COEF if applicable. Note: Whenever the chip is in RESETx, the factory-calibrated coefficient is reloaded into the registers from OTP. These same registers are used for displaying the factory-calibrated coefficient upon RESETx in certain order. However, the user has full read/write access and may reshuffle the order and values, then update CH_CAL_GAIN_OFFSET accordingly. OPT_COEF0..13 0xA0\\h-0xAD\\h 23:0 OPTC[23:0] RW 0x00_0000 Extra register for temporary storing coefficients, eg it can be used as Self-calibrated ADC values with internal VREF and REFH, REFL at CH_GAIN or Calibrated values with Excitation sources. See Table 12.

Table 28. 24-bit channel-based coefficient and data registers

7.9.3 System-level configurations and status registers

0x25\\h 15:0 CRC_CONF_REGS[15:0] R 0x0000 Integrated CRC result of all Configuration registers. 0x26\\h 15:0 CRC_COEF_REGS[15:0] R 0x0000 Integrated CRC result of all user's coefficient registers. 0x27\\h 15:0 CRC_TRIM_REGS[15:0] R 0x0000 Integrated CRC result of all factory trim OTP registers. Table 29. System-level configurations and status registers NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

0x35\\h 15:0 CH_OVR[15:0] R 0x0000 Channel over-range, logical CH15 is bit 15, CH0 is bit 0. 0x36\\h 15:0 CH_UDR[15:0] R 0x0000 Channel under-range, logical CH15 is bit 15, CH0 is bit 0.

15 DRDY_PWDT RW 0x0 DRDY pulse width duration (# of SYSCLK cycle): 0\\h = 2, 1\\h = 8

14 ADC_DATA_OUT_16BIT RW 0x0 ADC data register readout: 0\\h = 24 bit, 1\\h = 16 bit

12 MCLK_OUT_ENABLE RW 0x0 Enable the master clock(2*SYSCLK) output to GPIO9 pin. This bit supersedes and ignores the other GPIO9 setting. 0\\h = Both REF_BYP and REF_ADC use REF_INT. 1\\h = REF_BYP uses REF_INT and REF_ADC uses REF_EXT. 2\\h = REF_BYP uses REF_EXT and REF_ADC uses REF_INT. 3\\h = REF_BYP uses REF_EXT and REF_ADC uses REF_EXT. Note: Internal reference is always powered on. 7 CRC_EN RW 0x0 Enable CRC: 0\\h = disable, 1\\h = enable. Table 29. System-level configurations and status registers...continued NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

5 ADC_SYNC RW 0x0 ADC Synchronization mode enabled for host-driven with SYNC pulse at pin. This works with all conversion modes. 2 SPI_DOUT_DRIVE RW 0x0 Increase DOUT output drive if high capacitance loading. 1 INTB_DRIVER_TYPE RW 0x0 INTB pin driver type: 0 = 100 Kohm pullup with open drain, 1 = CMOS push-pull. 15 SINGLE_CH_ACTIVE R 0x0 Single-channel conversion mode indicator, which includes CH_DELAY. 0\\h = idle, 1\\h = active. 14 MULTI_CH_ACTIVE R 0x0 Multichannel Conversion mode indicator, which includes CH_DELAY. 0\\h = idle, 1\\h = active.

12 CRC_ERROR R 0x0 CRC error encountered

7:4 ADC_CONV_CH[3:0] R 0x0 The current active logical channel. 15 OVER_TEMP_ALRM RW 0x0 Overtemperature warning at 145 ℃. 14 HVDD_ALRM RW 0x0 Enable alarm for HVDD supply detect below preset threshold. 13 HVSS_ALRM RW 0x0 Enable alarm for HVSS supply detect below preset threshold. 12 ADVDD_ALRM RW 0x0 Enable alarm for DVDD supply detect below preset threshold. 10 GPI_POS_ALRM RW 0x0 Enable alarm for rising edge detected at any of GPI pins. 9 GPI_NEG_ALRM RW 0x0 Enable alarm for falling edge detected at any of GPI pins. 8 CONFIG_ERROR_ALRM RW 0x0 Enable alarm for register configuration error. 7 OVRRNG_ALRM RW 0x0 Enable alarm for one or more data channel is over-range. 6 UNDRNG_ALRM RW 0x0 Enable alarm for one or more data channel is under-range. 5 OVRLOAD_ALRM RW 0x0 Enable alarm for one or more data channels is over-loaded or under-loaded. 4 EXTCLK_FREQ_ALRM RW 0x0 Enable alarm when XTAL or EXTCLK frequency varies with internal CLK by XX. 0 TEMP_ALRM RW 0x0 Enable programmable temperature alarm; the triggering threshold is set in THRS_TEMP register bits. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

14 HVDD_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

13 HVSS_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

12 ADVDD_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

10 GPI_POS_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

9 GPI_NEG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

8 CONFIG_ERROR_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

7 OVRRNG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

6 UNDRNG_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

5 OVRLOAD_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

4 EXTCLK_FREQ_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

0 TEMP_INT RW 0x0 Bit clear behavior controlled by GLOBAL_ALRM_STICKY

15:0 THRS_TEMP[15:0] RW 0x0000 Temperature threshold in 2's complement for setting custom temperature alarm. 0x7F\\h 15:0 CRC_TRIM_INT[15:0] R 0x CRC sum of internal trims, to be used for comparison against CRC_TRIM_REGS[15:0]. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

8 Limiting values

8.1 Maximum rating

may lead to malfunction or permanent damage to the device. Table 30. Absolute maximum rating [1] maximum ratings is not implied. Device reliability may be affected if stressed at or beyond limits for extended periods. [2] Supply pins HVDD-AGND and AGND-HVSS are dc-clamped to 29 V. could sustain up to 60 V at ±24 mA with 2.5 kΩ external series resistor for duration of up to one hour. [4] Output pins REFH, REFL are diode-clamped to REF_BYP and AGND internally. limited to ±10 mA whenever the voltage at pin is 0.3 V (a) above AVDD/DVDD or (b) below AGND/DGND. [6] Digital output pins, current limit is ±10 mA. capacitor connection is recommended. Any other loading will affect the device functionality adversely. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

8.2 ESD stress rating and latch-up

Table 31. ESD stress rating and latch-up or above its ratings is not implied. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

9 Thermal characteristics

Table 32. Thermal characteristics limits may cause a malfunction or permanent damage to the device. suffixes) and enter the core ID to view all orderable parts and parametric. exposed pad surface temperature at the package bottom side dead center. not meant to predict the performance of a package in an application-specific environment. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

external 2.5 kΩ resistor in series with 1 nF capacitor connected to GND. See Figure 44. V/V, 0.4 V/V, and 0.8 V/V, respectively. GEv is gain error expressed in [V] as GE*FS. Table 33. HV input ranges NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Calibrated offset error without factory CAL coefficients. Calibrated gain error without factory CAL coefficients. Table 34. HV input accuracy before calibration NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 35. HV input accuracy after calibration and additional errors could arise from other test setup and conditions. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Single-ended inputs. Internal reference, TA = -25 °C to +105°C. Single-ended inputs. Internal reference, TA = -40 °C to +125°C. internal reference and G = 0.2 V/V, CH_CHOP = 1, TCC_OFF = 1. internal reference and G = 0.8 V/V, CH_CHOP = 1, TCC_OFF = 1. Table 36. HV input temperature and aging drift characteristics [1] Data is based on standard high-temperature operating life (HTOL) method. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Power supplies accuracy HVDD, HVSS and DVDD through ADC readback. Table 38. LV MUX inputs/GPIO0-GPIO1 as analog input Table 39. Temperature sensor Table 40. Internal voltage reference (VREF) [1] An initial accuracy error could be affected by mechanical stress post assembly. [2] Data is based on standard high-temperature operating life (HTOL) method. Table 41. Clock oscillators NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

Table 42. Power supplies [1] Not production tested and only limited samples were verified at ± 28 V supplies. Table 43. GPIO and digital I/O pins Table 44. SPI timing and characteristics NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

11.1 Typical application block diagram

64 AGND

61 GPIO2

60 GPIO3

59 GPIO4

56 GPIO5

55 GPIO6

54 GPIO7

53 GPIO8

52 GPIO9

63 GPIO0

62 GPIO1

51 DGND

58 DGND

57 DVDD

50 EXTCLK/XI

48 LDO_DIG13 12

18.432 MHz

47 DVDD

46 DGND

38 DGND

37 SPI_ADDR

40 SYNC

45 DRDY

44 MISO

43 MOSI

36 RSTB

35 AVDD

33 AGND

34 AGND

42 SCLK

39 INTB

0.1 F DC_3V3

Figure 44. Typical application block diagram Note: Dash boxes on AI1N, AI2P, AI2N inputs represent the dashed circuitry on AI1P.

11.2 Design for EMC

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

11.3 Programmable logic controller I/O module

11.3.1 Design example: ±10 V input module

AI3P, AI3N, AI4P and AI4N in Figure 44 illustrates an example of a ±10 V analog input channels for programmable logic controller (PLC). These HV inputs can be protected by current limiting with the series resistor along with its internal clamping diodes to HVDD and HVSS supplies. The signal from the transmitter is filtered by the external RC filter to remove EMI and RFI interference when operated in noisy environments. The negative input signal is connected to AICOM at 0 V. The ADC measures the differential voltage between inputs AI1P and AICOM. The input configuration is single-ended with the input voltage driven ±10 V relative to AICOM at 0V. The internal oscillator is selected and EXTCLK/XI pin is shorted to DGND. The serial interface and digital control lines of the ADC are connected to the host. Two Zener diodes are installed to clamp the high-voltage supply (HVDD-AGND and AGND-HVSS) to provide overvoltage protection if an input signal is present with module power off.

11.3.2 Design requirements

The ADC programmability allows various tradeoffs of sample rate, conversion noise, and conversion latency.

11.3.2.1 Design goal values

Accuracy: ±0.05 %
Temperature range (internal module): -25 °C to +105 °C
Acquisition period: 50 μs
Effective resolution: 19 bits

11.3.2.2 Design parameter value

Nominal signal range: ±10 V
Extended range: ±12 V
Input impedance: 1000 MΩ
Overvoltage rating: ±40 V

11.3.2.3 Detailed design procedure

A key consideration in the design of an analog input module is the error over the ambient temperature range resulting from the drift of gain, offset, reference voltage, and linearity error. This includes the initial offset and gain (including reference voltage error) after factory calibration. Figure 45 shows the maximum drift error of the NAFE over the -25 °C to +105 °C temperature range. The maximum error drift is < 0.02 % in the temperature range of -10 °C to 90 °C and 0.04 % in the temperature range -25 °C to 105 °C. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

Figure 45. Temperature drift test meets the design requirement. Figure 46. ADC conversion results

11.4 Power supplies and component selection

11.4.1 HV input pin protection and HV supply clamp

case of surge events, TVS diodes could be added at the source side, before the resistor. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

11.4.2 Power supply sequencing

As with many multiple-power supply systems, proper sequencing of the different supplies during power up and power down is a common practice to ensure robust device biasing without unnecessary electrical overstress. Though NAFE11388 devices were tested for robustness under various power supply ramping rates and order of sequences, testing is insufficient to cover all applications. Thus, for NAFE11388 devices, it is recommended to ramp up AVDD, DVDD before HVDD and/or HVSS. Ramping down HVDD and/or HVSS to ~3 V or less before starting to ramp down AVDD and DVDD, is also recommended. In most cases, any ramp rate slower than ±10 V/µs on HVDD, HVSS is acceptable.

11.4.3 HV input pin resistor

An external 2.5 kΩ series resistor is required at each of the AIxP, AIxN and AICOM pins. Higher resistance can lower the current limit in case of fault conditions with the expense of higher voltage error due to pin or board leakages and mismatches. Lower resistance is generally not advised in view of system reliability against surge and ESD events. For precision HV applications, high-pulse load MELF resistors are typically used and often with TC > 100 ppm/⁰C. With low input leakage current and the differential input architecture in the NAFE11388, the requirement on the temperature coefficient of the resistor is largely relaxed. If 1 % resistance tolerance is used, it meets the accuracy requirement in most applications. Note: For precise, high common-mode rejection single-ended measurement, AICOM pin in series with the same resistor type and value is to be used, instead of internal GND.

11.4.4 Crystal

The NAFE11388 offers multiple 18.432 MHz clock-source options:

Internal oscillator
Crystal oscillator
External clock source/module For robustness, a crystal with higher drive level >100 µW is recommended.

11.4.5 Capacitors

Use of high-grade capacitors is recommended for the following pins: REFP_ADC/REFN_ADC (1 μF, X7R) and CAPP/CAPN (1 nF, C0G).

11.4.6 Grounds and plane

Good layout practices are crucial to realize the full performance of the ADC. For best performance, dedicate an entire PCB layer to a ground plane. Do not route any other signal traces on this layer.

11.5 System-level calibration

11.5.1 Procedures for gain and offset calibrations

This section describes the steps in performing digital calibration for offset and gain error correction. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

11.5.1.1 Transfer characteristics

The NAFE11388 integrates an offset and gain correction circuitry. The offset correction (Oc) precedes the gain correction (Gc) in digital domain. The ideal transfer characteristic is The actual transfer characteristic is Where Ga and Oa are the actual gain and actual offset respectively. The calibrated transfer characteristic is Where Gc and Oc are the correction gain and offset coefficients, respectively.

11.5.1.2 Voltage and current input gain and offset calibration procedures

This section describes the steps for performing offset and gain digital calibration for voltage or current input.

11.5.1.2.1 Steps for gain CAL

Set 2. Set 3. Put a voltage source equals to x1, about +100 % of full-scale. 4. Read 5. Put a voltage source equals to x2, about -100 % of full-scale. 6. Read 7. Calculate 8. Set

11.5.1.2.2 Steps for offset CAL

Plug 2. Calculate 3. Set

11.5.2 Factory calibration and self-calibration

The NAFE11388 offers different calibration features to improve system accuracy at lower cost. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE The NXP factory-calibrated devices increase initial system accuracy while reducing the capital expenditure for expensive test instruments and reducing the production test time. The NAFE11388 stores factory-calibrated coefficients based on two points self-calibration to reduce the gain and offset error. The NAFE11388 includes two voltage sources to perform built-in or dynamic end-to- end self-calibrations. The ratiometric REFH and REFL voltage sources derived from the REF_BYP in combination with 0 V source (GND-GND) provide a precise and calibrated source for gain and offset calibration of all signal paths except reference voltage. The two points gain and offset calibration is performed measuring REFH-GND (or REFL-GND) and GND-GND and comparing against the internal stored value REFH-GND (or REFL- GND) and GND-GND = 0 V to calculate the gain and offset coefficients. Typically, REFH- GND with a typical value of 2.3 V, is suggested for low-channel gain, while RFEL-GND, with a typical value of 0.2 V, is suggested for high-channel gain. For systems that require low offset, an offset calibration could be performed measuring AICOM-AICOM to calculate and calibrate the offset error. Alternately, the NAFE11388 offers an automatic offset reduction circuit that is enabled by setting, CH_CONFIG1.CH_CHOP = 1, to activate the Precision mode. In this mode, the ADC runs two conversions and takes the average of the difference for offset removal. Note: The output data rate is halved. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

12 Typical operating characteristics

⁰C, unless otherwise specified. Table 45. Typical operating characteristics NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved.

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Rev Date Description v.1 20221104 Initial version

Revision history

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE

14 Legal information

14.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products.

14.4 Trademarks

Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Tables Tab. 28. 24-bit channel-based coefficient and data Tab. 29. System-level configurations and status Tab. 36. HV input temperature and aging drift Tab. 38. LV MUX inputs/GPIO0-GPIO1 as analog NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE Figures Fig. 2. Pin configuration in 64-lead 9 mm x 9 mm x Fig. 7. SINC Normal mode rejection vs frequency Fig. 14. Steps to setup for single-channel Fig. 15. Steps to setup for multichannel conversion Fig. 35. Host writes to register 16-bit with CRC Fig. 36. Host writes to register 24-bit with CRC Fig. 38. Conversion command data read operation 2/24-bit ADC, CRC_Enable = 1, Status_ Fig. 41. Conversion command data read operation 2/24-bit ADC, CRC_ENABLE = 1, Status_ Fig. 47. Package outline HVQFN64 Fig. 48. Package outline detail HVQFN64 Fig. 49. Reflow soldering footprint part 1 for Fig. 50. Reflow soldering footprint part 2 for NAFE11388 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 1 — 4 November 2022

NXP Semiconductors NAFE11388 Universal ±25 V 8-Input Low Power AFE 7.9.2 24-bit channel-based coefficient and data

7.9.3 System-level configurations and status

11.4.1 HV input pin protection and HV supply

11.5.1.2 Voltage and current input gain and offset

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2022 NXP B.V. All rights reserved. For more information, please visit: http://www.nxp.com Date of release: 4 November 2022 Document identifier: NAFE11388

Selected Specification

NXP Semiconductors NAFE11388B40BS overview.

Summary

Universal ±25 V 8-Input Low Power AFE Rev. 1 - 4 November 2022

Description

Universal ±25 V 8-Input Low Power AFE Rev. 1 - 4 November 2022

Source title NAFE11388B40BS Datasheet(PDF) - NXP Semiconductors

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