82S212 ETC

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BOLAR MEMORY DIVISION MAY 1982 | SS eed 2304-BIT BIPOLAR RAM (256 x9) 8282412 (T.S.) | DESCRIPTION The 828212 is available in both the com- PIN CONFIGURATION ‘The organization of the 82S212 allows ‘mercial and military temperature ranges. byte wide storage of data, including parity. For the commercial temperature range N, F PACKAGE* Where parity is not required, the ninth bit (0*C to 75°C) specify N82S212F or N and can be used as a tag for each word stored. _for the military temperature range (~ 55°C oO [23] vec: Tho 826212 is ideal for scratch-pad, push- to + 125°C) specify S82S212F. a a down stacks, buffer memories, and other 7 Internal memory applications in which FEATURES oo [25] x6 ‘space and performance requirements dic- * Address access time: os (24 Fra] as tate a wide data path in favor of word N62S212: 45ns max os CE [ray a depth. $828212: 70ns max a . 9 as The 828212 data inputs and outputs are Taratate eupute” O.amWibit oq Fae common (common 1/0) with separate Out- | schottky clamped TTL * put disable (OD) line that allows ease of y clamp io cor read/write operations using a common eo fe} fia) 40 as APPLICATIONS “* * Cache memory 00 [75] fa) & * Butter storage ovo GH] fay we — TRUTH TABLE * Writable control store “Fecorsip 5 DN N=Plastic TOP VIEW IN/OUT — Disable output 1 High Z Disable R/W x High Z Write 1 Data in Read ° Data out X= Dont care BLOCK DIAGRAM TYPICAL 1/0 STRUCTURE asus "0 a rl { « 1 | “a MEMORY CELL MATRIX 1s patie at “ on os - =| -———. “ ‘ Coo i : co \\ [| evo cx. = one

2 Dy Dr Dy D4 Ds Dy Oy Oy +

Veo ‘Supply voltage +7 Vde Vin Input voltage 455 Vde Vo Off-state output voltage +55 vde Temperature range: °c Ta Operating Commercial Oto +75 Military 85 to +125 Tst6 Storage 85 to +150 Signetics 59

BIPOLARMEMORY DIVISION MAY 1982 2304-BIT BIPOLAR RAM (2569) 828242 (T.S.) an DC ELECTRICAL CHARACTERISTICS" _Ng28212: 0°C <T, s +75°C, 4.75V < Voc < 5.25V TEST CONDITIONS [___Nezsziz[sezsaiz [| ramaneren’ | [min [ tye | max | min [ typ | max | Input voltage v Va. Low Voc= Min 80 Vin High Voc = Max Vic Clamp? Voc = Min, ty = = 12mA -15 ‘Output voltage v Vou Low? Voc = Min, lo, = 8.0mA Input current al hy Low Vin = 0.45V ~ 150 In High Vin = 5.5V 40 ‘Output current _ loorr, ‘Hi-Z state GE=High or OD= High, Vour=5.5V 40 60 CE= High oF OD= High, Vous O8V = 100 = 100 los Short circuit > E = OD = Low, Vout = OV -70 = 80 ‘Capacitance Voo= 5.0V Cw Input Vin=2.0V Cout Output Vour=2.0V AC ELECTRICAL CHARACTERISTICS!’ ph, = 4700, R= 1k2, C= 30pF NB2S212: 0°C < Ty = +75°C, 4.75V < Voc = 5.25V 8828212: — 55°C < Th < + 125°C, 4.75V < Voc = 5.25V ve [| rom | cal ca own ‘Access time Ta Address Address 70 Enable time ns Tor Output Output op Tor Output Output__| Chip enable Disable time Too Output Output op Too Output Output _| Chip enable Pulse width Twe Write Twsc Setup time Write | Chip enable Twuo Hold time Chip enable | _Write Twso Setup time write Data Twuo Hold time Data write Twsa Setup time Write ‘Address: Twa __Hold time Address write Tso Setup time (from disabled state) | Chip enable oD Two _Hold time ) Chip enable NOTES 4. The operating ambient temperature ranges are guaranteed with transverse ai flow exceeding 400 linear feet per minute and a 2 minute warmup. 2. All voltages are with respect to network ground terminal 2. All typical values are at Veg =5V. Ta =25°C. “4. Measured on one pin at atime. 5. Duration of log test should not exceed one second

540 Signetics

BIPOLAR MEMORY DIVISION. MAY 4982 2304-BIT BIPOLAR RAM (256 x9) 828242 (T.S.) TIMING DIAGRAMS ENABLE /DISABLE ~ Imre ree vn yore __weomen ‘Assumes Tag ftom address to valid deta W = high READ MODE =z —— ee WRITE MODE —= J so eK : Twse- TwHe- . “ a ee a | : : = CE el [= we [etme ° w 1s od CAUTION = Date Bus conflict can occur with CE = 0, apply tetore Tog nin) TEST LOAD CIRCUIT VOLTAGE WAVEFORM LOADING CONDITION INPUT PULSES = 30v = . las al les ° ne te, iu] oe seesenasnewome i = A resiatra vane are typical and i ot Signetics 511