82S09 ETC1

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BIPOLAR MEMORY DIVISION MAY 4982 a 576-BITBIPOLARRAM(64x9)_—————— «82809182849 (0...) DESCRIPTION APPLICATIONS PIN CONFIGURATION The organization of this device allows byte © Butfer memory . storage of data, including parity. Where par- © Control register R,F.IN PACKAGE ity is not monitored, the ninth bit canbe used © FIFO memory as a tag or status indicator for each word © Push down stack -O [2 Yee stored. Ideal for scratch-pad, push-down © Scratch pad ay a stacks, buffer memories, and other internal ac ba», memory applications in which cost and per- formance requirements dictate a wide data wE pel * path in favor of word depth. . ony The 82809/ 19 features open collector out- “El pele puts, chip enable input, and a very low cur- a a Fent pnp input structure to enhance memory La “ expansion = Ee, During Write operation, the 82S19 output «fl fis} 0, goes toa “1”. ‘The 82S09/ 19 is available in the commer- a Fao, => commercial temperature ranges (0°C to w Ea = +75°C) specify N82S09/ 19, F or N and for ono [14] [is] ce the military temperature range (55°C to = contp +125°C) specify $82S09/ 19 |, R or F. N= Pinstic Top VIEW FEATURES = Flt Pan © Address access time: N82S09: 45ns max TRUTH TABLE $82S09: 80ns max 82819: 35n0 max [ wove [ce [we fw [UNC 582510: 60ne max |__s2soa | azsie | ‘© Write cycle time: N82S09/19: 45ns max Read o 1 x Complement of data stored '$82S09: 80ns max Write “0” o ° ° 1 1 $82S19: 70ns max Write "1" ° oO 1 0 1 ‘* Power dissipation: 1.3mW/bit typ Disabled 1 x x 1 1 © Input loading: N82S09/19: —100uA max X= Don't care $82S09/19: —150uA max © On-chip address decoding BLOCK DIAGRAM ‘© Schottky clamped ‘© Fully TTL compatible © 82S09 Output is Non-Blanked During Write oe © 82819 Output Is Blanked During Write e seo] he °, seo] . pam ° Ky ———— rer to Signetics 54

BIPOLAR MEMORY DIVISION MAY 1982 BROLAR MEMORY DIVISION MAY 1982 576-BIT BIPOLAR RAM (649) 82S09/82S419 (O.C.) eee ABSOLUTE MAXIMUM RATINGS Veo Supply voltage +7 Vae VIN Input voltage 45.5 Vde Output voltage Vde Vou High +55 TA Temperature range °c Operating 'N82S09/19 Oto +75 $82809/19 56 to +125 Ts16 Storage 65 to +150 DC ELECTRICAL CHARACTERISTICS1,7 Ns2so9/19: 0°C < Ta < +78°C, 4.78V < Voc < 5.25V | ramen | Toe Ts Teer conormions [we [tye [tex [win [tye [wax] ONT Input voltage Vie Low Voc = Min 85 80 Vin High Voc = Max vic ‘Clamp? Voc = Min, lin = —12mA 1.6. 18 ‘Output voltage Vou Lows Voc = Min, lo. = 8.0mA Input current TA he Low Vin = 0.45V hn High Vin = 5.8V Output current uA louk Leakage* Voc = Max, Vout = 5.6V 'ec__ Voc supply curent$ a Capacitance Voc = 8.0V cn Input Vin = 2.0V Cour Output Vour = 2.0V Feter to notes on next page.

52 Signetics

BIPOLAR MEMORY DIVISION MAY 1982 | 576-BIT BIPOLAR RAM (64x 9) 82S09/82S19 (0.C.) AC ELECTRICAL CHARACTERISTICS? f; = 6000, Ro = 9000, CL = 30pF, for 82809 Ry = 5102, Ro = 7500, CL = 30pF, for 82519 . N82S19: 0° = Ta < +75°C, 4.75V < Voc = 5.25V [snes [el [min [Typ [Max[Min [typ [Max] Min [Typ [Max|Min [Typ [Max] Access time TAA Address: 80 Tce Chip enable 50 Teo Disable time Output Chip enable 60 Two Valid time Output Write enable 80 TwR Write recovery time Output Write enable ‘Setup and hold time TwsaA ‘Setup time TWHA Hold time. sS Twsp _Setup time == TWHD Hold time Twsc ‘Setup time ? Hold time Write enable Pulse width ! Twe ‘Write enabie® nores 1. At voltage vation are wth eepect onatwok round termina | 2 eat ech put one tne, 3. Maneured win he oi lw sored. Opt sk creat is supplied through areistor 4. Menaured wih Vig apptod to TE. 5. Igglameasured sth the wi eoble and cio enable apt oounded al cter pute 12.5, and the ctpete open 6. Samu required to gearates& Wits nto the eloweet bt 7. The operating ambient temperate ranges are guarerted with ranavres ar fow ‘rceecing 400 inet fot pet mite and 8 Z-miate war. TEST LOAD CIRCUIT VOLTAGE WAVEFORM LOADING CONDITION INPUT PULSES 81 z ow. at} eh SF AAR Veo — =| [ese L t a sos hd me | [esos ae] fans sce ORE t ono A renator aos ae type and ohne Signetics 53

BIPOLAR MEMORY DIVISION MAY 4982 —T"TE ON MAY 1982 576-BIT BIPOLAR RAM (64x 9) 82S09/82S19 (O0.C.) eee TIMING DIAGRAMS MEMORY TIMING DEFINITIONS | TcE Delay between beginning of Chip | READ CYCLE Enable low (with Address valid) | and when Data Output becomes ” valid. abontes tw Top Delay between when Chip Enable becomes high and Data Output is ar srore, veo in off state. on 18 Taa Delay between beginning of valid 1 srore vou Address (with Chip Enable low) Tas and when Data Output becomes valid. Address Access Time Twsc Required delay between begin- ning of valid Chip Enable and be- ow ginning of Write Enable pulse. nr Ennai iv vv TwHD Required delay between end of ov Write Enable pulse and end of val- peter t= vee id Input Data. on sev we Twp Width of Write Enable pulse. vou TWSA Required delay between begin: ‘ing of valid Address and begin- Chip Enable/Disable Times ning of Write Enable pulse. Twsp Required delay between begin: ning of valid Data input and end of cle/asig Write Enable pulse. WRITE CYCLE/82519 Twp Delay between beginning of Write “s Enable pulse and when Data Out- sees Z Recures cour note ov TwWHC Required delay between end of |+——— ws ———+] Fa | —$ Write Enable pulse and end of Srinieel fam 48 Chip Enable. " IN TWHA Required delay between end of | ~ Write Enable pulse and end of val- me + id Address. Shur enaDce 18 Twr Delay between end of Write En- ov able pulse and when Data Output Twa =} Twe ef Twn os becomes valid. (Assuming ad- Sane cae wy Tw dress stil valid) wy Twa Delay betwoen beginning of Write l= Two + Enable pulse and when data out- vee put reflects complement of data on input. WRITE CYCLE/82S09 ov ___ ws wml as -/ ov Two | “ twsa —=f-— Ye el Foe s WaT EWABTE 1 vey ow , wv teen | a ey i 5-4 Signetics