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Technical content

Features

Rev.1.10 Jul 29, 2022 ■ On-chip 32-bit Arm Cortex-R52 processor

• High-speed realtime control with operating frequency of 200/400 MHz
• On-chip Single 32-bit Arm Cortex-R52 (revision r1p2)
• Tightly coupled memory (TCM) with ECC – CPU0: 128 KB/128 KB
• Instruction cache/data cache with ECC – CPU0: 16 KB per cache
• High-speed interrupt
• The FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single- precision and double-precision.
• The NEON, Advanced SIMD, supports integer or single precision results.
• Harvard architecture with 8-stage pipeline
• Supports the memory protection unit (MPU)
• Arm CoreSight architecture, includes support for debugging through JTAG and SWD interfaces. ■ Low power consumption
• Standby mode and module stop function ■ On-chip SRAM
• 1.5 MB of the on-chip SRAM with ECC
• 150/200 MHz ■ Data transfer
• DMAC: 8 channels × 2 units ■ Event link controller
• Module operations can be started by event signals rather than by interrupt handlers.
• Linked operation of modules is available even while the CPU is in the standby state. ■ Reset and power supply voltage control
• Four reset sources including a pin reset ■ Clock functions
• External clock/oscillator input frequency: 25 MHz
• CPU clock frequency: 200/400 MHz or 150/300 MHz
• System clock frequency: 200 MHz or 150 MHz
• Low-speed on-chip oscillator (LOCO): 240 kHz ■ Safety functions
• Register write protection, input clock oscillation stop detection and CRC
• Master Memory Protection Unit (MPU) ■ Security functions (optional)
• Boot mode with security through encryption
• JTAG authentication
• Cryptologic accelerator
• TRNG ■ Various communications interfaces
• Ethernet – EtherCAT slave Controller: 3 ports – Ethernet switch: 3 ports – Ethernet MAC: 1 port
• USB 2.0 high-speed host/functions: 1 channel
• CAN/CANFD (compliant with ISO11898-1): 2 channels
• SCI with 16-byte transmission and reception FIFOs: 6 channels
• I2C bus interface: 3 channel for transfer at up to 400 kbps
• SPI: 4 channels
• xSPI: 2 channels ■ External host interfaces
• Serial host interface (SHOSTIF)
• Parallel host interface (PHOSTIF) ■ External address space
• Buses for high-speed data transfer at up to 100 MHz
• Support for up to 4 CS areas
• 8- or 16-bit bus space is selectable per area ■ Up to 35 extended-function timers
• 16-bit × 8 + 32-bit MTU3 (9 channels), 32-bit GPT (18 channels): Input capture, output compare, PWM waveform output
• 16-bit CMT (6 channels), 32-bit CMTW (2 channels) ■ ΔΣ interface
• Up to 6 ΔΣ modulators are connectable externally. ■ Trigonometric function unit
• Simultaneous calculation of sine and cosine
• Simultaneous calculation of arctangent and hypot_k ■ 12-bit A/D converter
• 12 bits × 2 unit (4 channels for unit 0, 8 channels for unit 1) ■ Temperature sensor for measuring temperature within the chip ■ General-purpose I/O ports
• Input pull-up/pull-down
• The locations of input/output functions for peripheral modules are selectable from among multiple pins. ■ Operating temperature range
• Tj = -40 to +125°C Datasheet R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 1 of 127

1. Overview

1.1 Outline of Specifications

The MPU is a high-performance ASSP that has Arm Cortex®-R52 processor with Floating-Point Unit (FPU) and NEON™. It incorporates integrated peripheral functions necessary for system configuration. Table 1.1 CPU Feature Functional description Arm® Cortex®-R52 ● Single processor

• Operating frequency – 200 MHz/400 MHz (in case of 200 MHz system clock) – 150 MHz/300 MHz (in case of 150 MHz system clock)
• 32-bit CPU Cortex-R52 designed by Arm (core revision r1p2)
• Address space: 4 GB
• Instruction cache – 16 KB (with ECC)
• Data cache – 16 KB (with ECC)
• Tightly coupled memory (TCM) – ATCM: 128 KB (with ECC) 0 wait – BTCM: 128 KB (with ECC) 0 wait – CTCM: 0 KB (with ECC)
• Instruction set: Arm v8-R architecture, so support includes Thumb ® and Thumb-2
• Data arrangement – Instructions: Little endian – Data: Little endian
• 2-stage memory protection unit (MPU) FPU ● Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at single- and double-precision.
• Registers 64-bit single-word registers: 64 bits × 32 (can be used as 16 double-word registers: 128 bits × 16) NEON The Advanced SIMD supporting integer or single precision results Table 1.2 Memory Feature Functional description On-chip system SRAM with ECC ● Capacity: Up to 1.5 MB (512 KB × 3 units) (with ECC)
• Operating frequency: 150 MHz/200 MHz
• SEC-DED (single error correction/double error detection) Error injection supported One-time programmable memory ● Overwrite protection
• Redundancy support
• Available information – Unique ID – Authentication settings – Trimming data – Boot mode setting – User area Table 1.3 System (1 of 2) Feature Functional description Operating modes The operating mode can be selected from the following eight boot modes:
• xSPI0 boot mode (CS0 × 1 boot Serial Flash)
• xSPI0 boot mode (CS0 × 8 boot Serial Flash)
• 16-bit bus boot mode (CS0 NOR Flash)
• SHOSTIF boot mode
• PHOSTIF boot mode
• xSPI1 boot mode (CS0 × 1 boot Serial Flash)
• SCI boot mode
• USB boot mode RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 2 of 127

Table 1.3 System (2 of 2) Feature Functional description Clock generation circuit ● The input clock can be selected from an external clock or external resonator.

• Detection of input clock oscillation stopping
• The following clocks are generated: – CPU0 clock: System clock ×1 or ×2 – System clock: 150 or 200 MHz – High-speed peripheral module clock: 150 or 200 MHz – Middle-speed peripheral module clock: 75 or 100 MHz – Low-speed peripheral module clock: 37.5 or 50 MHz – ADC clock in the 12-bit A/D converter: 25 or 18.75 MHz – External bus clock: 100 MHz (max.) – Low-speed on-chip oscillator: 240 kHz (fixed) Reset RES# pin reset, software reset, error reset, CPU0 software reset Low-power consumption function ● Standby mode (Cortex-R52)
• Module stop function Interrupt controller (ICU) ● Peripheral function interrupts: 423 sources
• External interrupts: 16 sources (IRQ0 to IRQ15 pins)
• Software interrupts: 8 sources
• Non-maskable interrupts: 1 sources
• 32 levels specifiable for the order of priority Bus state controller (BSC) ● The external address space is divided into four areas (CS0, CS2, CS3, and CS5) for management.
• The following features are configurable for each area independently: Bus size (8 or 16 bits): Available sizes depend on the area. Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas). Idle wait cycle insertion (between same area access cycles or different area access cycles). Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous). The address/data multiplexed I/O (MPX) interface is also available.
• Outputs a chip select signal (CS0# to CS5#) according to the target area (CS assert or negate timing can be selected by software).
• SDRAM refresh Auto refresh or self-refresh mode selectable
• SDRAM burst access Table 1.4 Direct memory access Feature Functional description Direct memory access controller (DMAC)
• 2 unit (8 channels each unit)
• Transfer modes: Single transfer mode and block transfer mode
• Transfer size - Unit 0: 1/2/4/8/16/32/64 bytes - Unit 1: 1/2/4/8/16/32 bytes
• Activation sources: Software trigger, external DMA requests (DREQ), external interrupts, and interrupt requests from peripheral functions Table 1.5 I/O Ports Feature Functional description General-purpose I/O ports ● 225-pin FBGA – I/O pins: 134 – Input pins: 1 – Pull-up/pull-down resistors: 135
• 121-pin FBGA – I/O pins: 71 – Input pins: 0 – Pull-up/pull-down resistors: 71
• The locations of input/output functions are selectable from among multiple pins. RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 3 of 127

Table 1.6 Event link Feature Functional description Event link controller (ELC) ● Up to 217 event signals can be interlinked with the operation of modules.

• In particular, the operation of timer modules can be started by input event signals.
• Event-linked operation of signals of ports 16 and port 18 is to be possible. Table 1.7 Timers (1 of 2) Feature Functional description Multi-function timer pulse unit 3 (MTU3) ● 9 channels (16 bits × 8 channels, 32 bits × 1 channel)
• Maximum of 28 pulse-input/output and 3 pulse-input possible
• Select from among 10, 11, 12, or 14 counter-input clock signals for each channel (with maximum operating frequency of 200 MHz)
• Input capture function
• 39 output compare/input capture registers
• Counter clear operation (synchronous clearing by compare match/input capture)
• Simultaneous writing to multiple timer counters (TCNT)
• Simultaneous register input/output by synchronous counter operation
• Buffered operation
• Support for cascade-connected operation
• Automatic transfer of register data
• Pulse output mode Toggle/PWM/complementary PWM/reset-synchronized PWM
• Complementary PWM output mode - Outputs non-overlapping waveforms for controlling 3-phase inverters - Automatic specification of dead times - PWM duty cycle: Selectable as any value from 0% to 100% - Delay can be applied to requests for A/D conversion. - Non-generation of interrupt requests at peak or trough values of counters can be selected. - Double buffer configuration
• Reset synchronous PWM mode Three phases of positive and negative PWM waveforms can be output with desired duty cycles.
• Phase-counting mode: 16-bit mode (channels 1 and 2), 32-bit mode (channels 1 and 2 in cascade connection)
• Counter functionality for dead-time compensation
• Generation of triggers for A/D converter conversion
• A/D converter start triggers can be skipped
• Digital noise filter function for signals on the input capture and external counter clock pins
• Event linking by the ELC General PWM timer (GPT) ● 32 bits × 18 channels
• Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels
• Select from among four counter-input clock signals for each channel (with maximum operating frequency of 200 MHz)
• 2 input/output pins per channel
• 2 output compare/input capture registers per channel
• For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use.
• In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms.
• Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow)
• Synchronizable operation of the several counters
• Modes of synchronized operation (synchronized, or displaced by desired times for phase shifting)
• Generation of dead times in PWM operation
• Through combination of 3 counters, generation of automatic 3-phase PWM waveforms incorporating dead times
• Starting, clearing, stopping, switching, up/down counters, and input capture in response to external or internal triggers
• Starting, clearing, stopping, switching, up/down counters, and input capture in response to input level comparison
• Internal trigger sources: software and compare-match
• Generation of triggers for A/D converter conversion
• Digital noise filter function for signals on the input capture and external trigger pins
• Event linking by the ELC RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 4 of 127

Table 1.7 Timers (2 of 2) Feature Functional description Compare match timer (CMT) ● (16 bits × 2 channels) × 3 units

• Select from among four counter-input clock signals for each channel (with maximum operating frequency of 50 MHz) Compare match timer W (CMTW) ● (32 bits × 1 channel) × 2 units
• Compare-match, input-capture input, and output-comparison output are available.
• Select from among four counter-input clock signals for each channel (with maximum operating frequency of 50 MHz)
• Interrupt requests can be output in response to compare-match, input-capture, and output- comparison events. Watchdog timer (WDT) ● 14 bits × 1 channel
• Select from among six counter-input clock signals for each channel (with maximum operating frequency of 50 MHz) Port output enable 3 (POE3) ● Control of the high-impedance state of the MTU3 waveform output pins
• 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#
• Initiation on detection of short-circuited outputs (detection of simultaneous PWM output to the active level)
• Initiation by input clock oscillation-stoppage detection, PLL oscillation anomaly detection, DSMIF error detection, or software
• Additional programming of output control target pins is enabled Port output enable for GPT (POEG) ● Controlling the output disable for GPT waveform output
• Initiation by input level detection of GTETRG pins
• Initiation by output disable request from GPT
• Initiation by detection of oscillation stop, DSMIF error, or by software Real time clock (RTC) ● A 100 year calendar from 2000 to 2099
• BCD code display
• Clock source is division of main oscillator or PLL.
• Automatic adjustment function for leap years Table 1.8 Communication interfaces (1 of 3) Feature Functional description Ethernet MAC (GMAC) ● 1 port
• IEEE802.3
• IEEE1588-2008
• IEEE802.3-az-2010 for EEE
• 10BASE, 100BASE, and 1000BASE supported
• Full duplex and half duplex are supported
• Programmable frame length to support both standard and jumbo frames up to 16 KB
• 17 MAC address registers for the address filter block
• Variety of flexible addresses filtering modes are supported
• Advanced IEEE 1588-2002 & 2008 Ethernet frame time-stamping supported
• MII/RMII/RGMII interface is supported RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 5 of 127

Table 1.8 Communication interfaces (2 of 3) Feature Functional description Ethernet switch (ETHSW) ● 3-port PHY interfaces

• IEEE802.3
• Support for 10/100/1000 Mbps data transfer
• Full and half duplex (1000 Mbps supports full-duplex only)
• Hardware switching, lookup, and filtering
• QoS with frame prioritization
• Priority control based on VLAN Priority (IEEE802.1q), which enables priority reassignment
• Classification and priority assignment based on IPv4 DiffServ Code Point Field, IPv6 Class of Service
• Queue with eight priority levels
• Multicasting and broadcasting
• VLAN frame
• IEEE 1588-2008 compatible
• Programmable addition, removal and manipulation of ingress and egress VLAN tags, supporting single and double-tagged VLAN frames on each port
• Cut-through and hub features
• Device level ring (DLR)
• Programmable egress rate limit per port
• Ingress Configurable Broadcast/multicast storm protection per port
• IEEE802.1X source address authentication supported
• IEEE802.1X guest VLAN supported
• PRP functionality (IEC 62439-3 edition 2.0- 2012)
• Configurable Time Multiplexed (TDMA) output queue scheduler supporting real-time network infrastructures using time slots for bandwidth reservation enabling deterministic delays
• Pattern matchers 12 channels
• Independent two timer module are available for timestamping and time for TDMA.
• Remote monitoring through SNMP
• Powerlink capable hub
• Ingress filtering and frame header manipulation (active stream identification, flow metering) with Enhanced Frame Parser
• 4 additional PTP timer pulse generators
• MAC to MAC connection
• MII/RMII/RGMII interface is supported EtherCAT slave controller (ESC)*1 ● 1 channel (3 ports)
• EtherCAT Slave Controller IP core (made by Beckhoff Automation GmbH) implemented
• MII/RMII/RGMII interface is supported by external RGMII converter. USB 2.0 HS host/function module ● 1 port
• Compliance with the USB 2.0 specification
• OTG support
• Transfer rate High speed (480 Mbps), full speed (12 Mbps), low speed (1.5 Mbps, host only)
• Communications buffer – Incorporates 1 KB of RAM for host mode – Incorporates 8 KB of RAM for function mode
• DMAC (2 channels) incorporated Serial communication interface (SCI) ● 6 channels
• 5 communication mode – Asynchronous interfaces – 8-bit clock synchronous interface – Simple I2C (master-only) – Simple SPI – Smart card interface
• Clock source is select from among four internal clock signals
• Bit rate specifiable with the on-chip baud rate generator
• Full-duplex and half-duplex communication
• Data length: 7 to 9 bits (Asynchronous mode)
• Bit rate modulation
• Double speed mode
• Loopback function to enable self-diagnosis (Asynchronous, Clock synchronous mode) I2C bus interface (IIC) ● 3 channels
• Communication formats: I2C bus format or SMBus format
• Master or slave mode selectable
• Supports the multi-master
• Maximum transfer rate: 400 kbps (Standard mode and Fast mode) RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 6 of 127

Table 1.8 Communication interfaces (3 of 3) Feature Functional description CAN-FD module (CANFD) ● 2 channels

• Comply with CAN-FD ISO 11898-1 (2015)
• Communication speed – Classical CAN mode: 1 Mbps – CAN FD mode: Nominal bit rate: max. 1 Mbps Data bit rate: max. 8 Mbps
• Total 192 message buffers (in case frame size is 76 bytes) – Individual buffers: 64 for TX – Shared buffers: 128 for TX and RX including FIFO
• Selectable ID type with 11-bit Standard and 18-bit Extended
• Selectable Frame type: Data Frame and Remote Frame
• Up to 256 receive rules Serial peripheral interface (SPI) ● 4 channels
• SPI transfer facility – Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select), and RSPCK (SPI clock) signals enable serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) – Capable of handling serial transfer as a master or slave
• Data formats – Switching between MSB first and LSB first – The number of bits in each transfer can be changed to any number of bits from 8 to 16, or 20, 24, or 32 bits. – 128-bit buffers for transmission and reception – Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits)
• Buffered structure – Double buffers for both transmission and reception
• RSPCK can be stopped automatically with the reception buffer full for master reception Expanded serial peripheral interface (xSPI)
• 2 channels
• Comply with JESD251
• Multiple slave up to 2 slaves (channel 0 only)
• Protocol mode: 1/4/8pin with SDR/DDR 1S-1S-1S, 4S-4D-4D, 8D-8D-8D
• Support OctaFlash, OctaRAM, HyperFlash and HyperRAM
• Protocol mode: 2/4pin with SDR compatible with QSPI 1S-2S-2S, 2S-2S-2S 1S-4S-4S, 4S-4S-4S
• Configurable address length
• Configurable initial access latency cycle
• Support XiP mode
• Support up to 64 MB address space each CS
• Prefetch function for burst-read with low latency
• Outstanding buffer for burst-write with high throughput
• Manual command configurable up to 4 commands
• Output clock/input strobe port timing shift
• Automatic command after released reset: up to 4 commands Note 1. EtherCAT is a registered trademark of Beckhoff Automation GmbH, Germany. RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 7 of 127

Table 1.9 Analog Feature Functional description 12-bit A/D converter (ADC12) ● 12 bits × 2 units (unit 0: 4 channels, unit 1: 8 channels)

• 12-bit resolution
• Conversion time 0.84 µs per channel
• Operating mode Scan mode (single scan mode, continuous scan mode, or 3 group scan mode) Group priority control
• Sample-and-hold function Common sample-and-hold circuit included In addition, channel-dedicated sample-and-hold function (3 channels: in unit 0 only) included
• Sampling variable Sampling time can be set up for each channel
• Double trigger mode (A/D conversion data duplicated)
• Three ways to start A/D conversion Software trigger, timer (MTU3, GPT) trigger, external trigger
• Event linking by the ELC Temperature sensor unit (TSU) ● 1 channel
• Relative precision: ±1°C (typ) Table 1.10 Hardware accelerator for industrial interfaces Feature Functional description ΔΣ interface (DSMIF) ● 3 channels × 2 units
• Selectable 2 inputs (U/V) or 3 inputs (U/V/W)
• Up to 6 ΔΣ modulators are externally connectable
• Sinc filter can be selected as first, second or third order Trigonometric function unit (TFU) Calculation of sine, cosine, arctangent, hypot_k ( x 2 + y 2 / k )
• Simultaneous calculation of sine and cosine
• Simultaneous calculation of arctangent and hypot_k Table 1.11 Safety (1 of 2) Feature Functional description Memory protection unit (MPU) ● Cortex-R52 MPU Two stages MPUs (EL2 and EL1) 24 regions each MPU
• Master MPU Memory protection for masters except Cortex-R52 (DMAC, USB, Ethernet MAC, CoreSight, SHOSTIF, PHOSTIF) Register write protection function Protects important registers from being overwritten for in case a program runs out of control. CRC calculator (CRC) ● 2 channels
• CRC code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units
• Select any of four generating polynomials: – X 32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 (32- Ethernet) – X 32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1 (CRC-32C) – X 16 + X15 + X2 + 1 (CRC-16) – X 16 + X12 + X5 + 1 (CRC-CCITT) Clock monitor circuit (CLMA) ● Monitors the abnormal output clock frequency from the PLL circuit or low-speed on-chip oscillator.
• Input clock oscillation stop detection: Available Data operation circuit (DOC) The function to compare, add, or subtract 16-bit data RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 8 of 127

Table 1.11 Safety (2 of 2) Feature Functional description Isolated peripherals ● Safety dedicated peripherals are available: – GPT: 4 ch – SCI: 1 ch – IIC: 1 ch – SPI: 1 ch – CRC: 1 unit – RTC: 1 unit – GPIO: Sharable with normal GPIO – On-chip system SRAM with ECC

• They are mapped independently from normal peripherals so that access protection can be done by EL2 MPU. Table 1.12 Security Feature Functional description Security*1 ● Secure boot
• JTAG authentication
• SCI/USB boot authentication
• Cryptographic accelerators – Symmetric Cipher: AES 128/192/256 bits with CBC/ECB/CTR/GCM/XTS – Asymmetric Cipher: ECC 256 bits, RSA 1024/2048/3072 bits, RSAES-OAEP – Hash: SHA-1, SHA-2 – Message authentication: HMAC, CMAC, GMAC – Signature algorithms: ECDSA with NIST P-256, RSASSA-PSS, RSASSA-PKCS1
• TRNG Note 1. For details, contact our sales representative. Table 1.13 Debug Feature Functional description Debugging interface ● CoreSight architecture designed by Arm
• Debugging function by the JTAG/SWD interface, and trace function by the trace port interface Table 1.14 External host interface Feature Functional description Serial host interface (SHOSTIF) ● Serial communication is possible in slave mode.
• Supported interface – Motorola Serial Peripheral Interface (4-wire SPI) – Enhanced SPI Modes with Dual, Quad, or Octal SPI
• Serial clock polarity switching
• Serial clock phase switching
• Single Data Transfer
• Data size is up to 32 bits × 64 burst Parallel host interface (PHOSTIF) ● Synchronous/Asynchronous SRAM Interface Mode
• Synchronous Burst SRAM Type Transfer Mode
• Bus width: 8 or 16 bits
• Synchronous relations – HCKIO synchronous
• Write buffer
• Read buffer
• Multiplexing of addresses and data (Synchronous Burst SRAM Type only) Mailbox and semaphore (MBXSEM) ● Eight semaphores
• Four 32-bit mailboxes for both external host CPU to Cortex-R52 and Cortex-R52 to external host CPU
• Interrupts can be generated and cleared from both external host CPU and Cortex-R52 RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 9 of 127

Table 1.15 Others Feature Functional description Power supply voltage VDD = 1.1 V (Core) VCC18 = 1.8 V (PLL, USB, ADC, TSU) VCC33 = 3.3 V (I/O, USB) VCC1833 = 1.8 V or 3.3 V (RGMII/RMII/MII*1, xSPI) Operating temperature Tj = −40 to +125°C Packages 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 121 pin FBGA 10 × 10 mm, 0.8-mm pitch RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 10 of 127

1.2 Function Comparison

Table 1.16 Comparison of Functions for Different Packages Module/Function 225-pin FBGA 121-pin FBGA CPU ARM Cortex-R52 Single External bus External bus width 8, 16 bits Not supported Interrupt External interrupt NMI, IRQ0 to IRQ15 NMI, IRQ0 to IRQ3, IRQ5 to IRQ8, IRQ11 to IRQ13 DMA DMA controller (DMAC) 2 units (DMAC0: 8 channels, DMAC1: 8 channels) Timer Multi-function timer pulse unit 3 (MTU3) 9 channels 9 channels*1 General PWM timer (GPT) 18 channels 18 channels*1 Compare match timer (CMT) 6 channels Compare match timer W (CMTW) 2 channels 2 channels*1 Watchdog timer 1 channel Port output enable 3 (POE3) Available Available*1 Port output enable for GPT (POEG) Available Available*1 Real time clock (RTC) Available Communication function Ethernet MAC (GMAC) 1 port Ethernet switch (ETHSW) 3 ports (PHY interface) 2 ports (PHY interface) EtherCAT slave controller (ESC) 3 ports 2 ports USB 2.0 HS host/function module (USB) 1 port Not supported Serial communication interface (SCI) 6 channels 5 channels*1 I2C bus interface (IIC) 3 channels 3 channels CANFD module (CANFD) 2 channels 2 channels*1 Serial peripheral interface (SPI) 4 channels 2 channels*1 Expanded serial peripheral interface (xSPI) 2 channels (1.8 V or 3.3 V) 1 channel*1 (3.3 V) ΔΣ interface (DSMIF) 2 units (DSMIF0: 3 channels, DSMIF1: 3 channels) 2 units (DSMIF0: 2 channels, DSMIF1: 2 channels) Trigonometric function unit (TFU) Available 12-bit A/D converter (ADC12) 2 units (ADC120: 4 channels, ADC121: 8 channels) Not supported Temperature sensor unit (TSU) Available CRC calculator (CRC) 2 channels Clock monitor circuit (CLMA) Available Data operation circuit (DOC) Available Security*3 Optional One-time programmable memory (OTP) Available External host interface Serial host interface (SHOSTIF) 1 channel 1 channel*2 Parallel host interface (PHOSTIF) 1 channel Not supported Mailbox and Semaphore (MBXSEM) Available Event link controller (ELC) Available Note 1. A part of external signals are not available. Note 2. Up to quad connection Note 3. For details, contact our sales representative. RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 11 of 127

1.3 Product Lineup

Table 1.17 Product Lineup Group Part Number Package Security RZ/N2L R9A07G084M08GBG PLBG0225GB-A Available R9A07G084M04GBG PLBG0225GB-A Not available R9A07G084M08GBA PLBG0121GF-A Available R9A07G084M04GBA PLBG0121GF-A Not available RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 12 of 127

1.4 Block Diagram

Figure 1.1 shows a block diagram of the 225-pin device. OTP Security MBXSEM Peripheral modules for Non-Safety Peripheral modules for Motor Subsystem On-chip system SRAM with ECC xSPI × 2 channels Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Port 20 Port 21 Port 22 Port 23 Clock generation circuit BSC ESC × 3 ports TFU CANFD × 2 channels WDT × 1 channel POEG (unit 0) CMT × 6 channels (unit 0-2) CMTW × 2 channels (unit 0-1) POE3 12-bit A/D converter (unit 0) MTU3 GPT × 4 channels (unit 0) DSMIF × 6 channels (unit 0-1) SCI × 5 channels GMAC : Ethernet MAC ETHSW : Ethernet switch ESC : EtherCAT slave controller DMAC : DMA controller BSC : Bus state controller xSPI : Expanded serial peripheral interface WDT : Watchdog timer SCI : Serial communication interface SPI : Serial peripheral interface USB : USB 2.0 HS host/function module GIC : Generic interrupt controller MPU : Memory protection unit ELC : Event link controller MTU3 : Multi-function timer pulse unit 3 SHOSTIF : Serial host interface MBXSEM : Mailbox and Semaphore GPT : General PWM timer CMT : Compare match timer CMTW : Compare match timer W POE3 : Port output enable 3 POEG : Port output enable for GPT RTC : Real time clock IIC : I C bus interface CANFD : CANFD module DSMIF : ΔΣ interface TFU : Trigonometric function unit CRC : CRC (cyclic redundancy check) calculator CLMA : Clock monitor circuit DOC : Data operation circuit TSU : Temperature sensor unit PHOSTIF : Parallel host interface OTP : One-time programmable memory TSU ETHSW × 3 ports Port 24 TCM Cortex-R52 (CPU0) GIC MPU LLPP bus GMAC × 1 port USB × 1 port DMAC × 8 channels (unit 0) DMAC × 8 channels (unit 1) GPT × 10 channels (unit 1) POEG (unit 1) 12-bit A/D converter (unit 1) IIC × 2 channels SPI × 3 channels CRC (unit 0) DOC Peripheral modules for Safety GPT × 4 channels (unit 2) POEG (unit 2) RTC CRC (unit 1) SCI × 1 channel IIC × 1 channel SPI × 1 channel CLMA ELC SHOSTIF PHOSTIF Internal main bus Figure 1.1 Block diagram of a 225-pin device RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 13 of 127

1.5 Pin Functions

Table 1.18 lists the pin functions. Table 1.18 Pin functions (1 of 7) Classification Pin name I/O Description Power supply VDD Input Power supply pin. Connect this pin to the system power supply. VSS Input Ground pin. Connect this pin to the system power supply (0 V). VCC1833_0 VCC1833_1 VCC1833_2 VCC1833_3 VCC1833_4 Input Power supply pin for each I/O domains. (1.8 V or 3.3 V) This pin is available for BGA package product only. VCC33 Input Power supply pin for I/O pins. VCC18_PLL0, VCC18_PLL1 Input Power supply pins for the on-chip PLL oscillator AVCC18_TSU Input Power supply pin for the temperature sensor unit Clock XTAL Output Connected to a crystal resonator. When external clock signal is used, EXTAL pin should be driven low. XTAL pin should never be driven or loaded by anything other than crystal oscillator. The voltage level of EXTAL must not exceed core VDD (1.16 V). EXTAL Input EXTCLKIN Input Inputs the external clock. When a crystal resonator is connected, it should be driven low. CKIO Output Outputs the external bus clock for external devices. ETH0_REFCLK Output Outputs 25 MHz clock for EtherPHY 0 ETH1_REFCLK Output Outputs 25 MHz clock for EtherPHY 1 ETH2_REFCLK Output Outputs 25 MHz clock for EtherPHY 2 RMII0_REFCLK Output Outputs 50 MHz clock for RMII0 RMII1_REFCLK Output Outputs 50 MHz clock for RMII1 RMII2_REFCLK Output Outputs 50 MHz clock for RMII2 Operating mode control MDX Input This signal should be driven low. MD0 to MD2 Input Input the operating mode select signal. The signal level on these pins must not be changed during operation mode transition on release from the reset state. MDV0 to MDV4 Input Input the operating voltage select signal. The signal level on these pins must not be changed during operation mode transition on release from the reset state. MDD Input Input the enabling JTAG authentication by hash signal. The signal level on this pin must not be changed during operation mode transition on release from the reset state. System control RES# Input Inputs the reset signal. This MPU enters the reset state when this signal goes low. BSCANP Input Inputs the boundary scan enable signal. Boundary scan is enabled when this pin goes high. When boundary scan is not used, this pin should be driven low. RSTOUT# Output Outputs the reset signal externally RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 14 of 127

Table 1.18 Pin functions (2 of 7) Classification Pin name I/O Description Debugging interface TRST# Input Test reset pin for the on-chip emulator TMS I/O Test mode select pin for the on-chip emulator Functions as the SWDIO pin in serial wire debug (SWD) mode TDI Input Test data input pin for the on-chip emulator TDO Output Test data output pin for the on-chip emulator TCK Input Test clock pin for the on-chip emulator Functions as the SWCLK pin in serial wire debug (SWD) mode TRACECLK Output Outputs the clock for synchronization with trace data TRACECTL Output Outputs the enable signal for trace control TRACEDATA0 to TRACEDATA7 Output Output trace data Bus state controller (BSC) A25 to A0 Output Output the address D15 to D0 I/O Input and output the data CS0#, CS2#, CS3#, CS5# Output Output the chip select signal for the external memory or device. RD# Output Outputs the strobe signal which indicates a read is in progress. RD/WR# Output Outputs the strobe signal which indicates a read or write access BS# Output Outputs the status signal which indicates the start of the bus cycle AH# Output Outputs the address hold signal for the device that uses the multiplexed I/O interface WAIT# Input Inputs the external wait control signal which inserts a wait cycle into the bus cycle WE0# Output Outputs the write strobe signal to D7 to D0 WE1# Output Outputs the write strobe signal to D15 to D8 DQMLL Output Outputs the data mask enable signal to D7 to D0 when SDRAM is connected DQMLU Output Outputs the data mask enable signal to D15 to D8 when SDRAM is connected RAS# Output Outputs the row-address strobe signal to the SDRAM. This pin should be connected to the RAS# pin on the SDRAM. CAS# Output Outputs the column-address strobe signal to the SDRAM. This pin should be connected to the CAS# pin on the SDRAM. CKE Output Outputs the clock enable signal to the SDRAM. This pin should be connected to the CKE pin on the SDRAM. Direct memory access controller (DMAC) DREQ Input Inputs the DMA transfer request signal from the external device DACK Output Outputs the acknowledge signal which indicates acceptance of the DMA transfer request from the external device TEND Output Outputs the DMA transfer end signal Interrupt NMI Input Inputs the non-maskable interrupt request signal IRQ0 to IRQ15 Input Input the external interrupt request signal RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 15 of 127

Table 1.18 Pin functions (3 of 7) Classification Pin name I/O Description Multi-function timer pulse unit 3 (MTU3) MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D I/O TGRA0 to TGRD0 input capture input, output compare output, and PWM output pins MTIOC1A, MTIOC1B I/O TGRA1 and TGRB1 input capture input, output compare output, and PWM output pins MTIOC2A, MTIOC2B I/O TGRA2 and TGRB2 input capture input, output compare output, and PWM output pins MTIOC3A, MTIOC3B, MTIOC3C, MTIOC3D I/O TGRA3 to TGRD3 input capture input, output compare output, and PWM output pins MTIOC4A, MTIOC4B, MTIOC4C, MTIOC4D I/O TGRA4 to TGRD4 input capture input, output compare output, and PWM output pins MTIC5U, MTIC5V, MTIC5W Input TGRU5, TGRV5, and TGRW5 input capture input and dead time compensation input pins MTIOC6A, MTIOC6B, MTIOC6C, MTIOC6D I/O TGRA6 to TGRD6 input capture input/output compare output/PWM output pins MTIOC7A, MTIOC7B, MTIOC7C, MTIOC7D I/O TGRA7 to TGRD7 input capture input/output compare output/PWM output pins MTIOC8A, MTIOC8B, MTIOC8C, MTIOC8D I/O TGRA8 to TGRD8 input capture input/output compare output/PWM output pins MTCLKA, MTCLKB, MTCLKC, MTCLKD Input External clock input pins for MTU3 Port output enable 3 (POE3) POE0#, POE4#, POE8#, POE10#, POE11# Input Input the request signal to place the MTU3 in the high- impedance state General PWM timer (GPT)/ Port output enable for GPT (POEG) GTETRGA, GTETRGB, GTETRGC, GTETRGD Input External trigger input and output-disable request input pins GTETRGSA, GTETRGSB Input External trigger input and output-disable request input pins (SAFETY) GTIOC0A to GTIOC17A, GTIOC0B to GTIOC17B I/O Input capture input/output compare output/PWM output pins GTADSML0, GTADSML1, GTADSMP0, GTADSMP1 Output Output pins for monitoring A/D conversion start requests Compare match timer W (CMTW) CMTW0_TIC0, CMTW0_TIC1, CMTW1_TIC0, CMTW1_TIC1 Input CMTW input capture input pins CMTW0_TOC0, CMTW0_TOC1, CMTW1_TOC0, CMTW1_TOC1 Output CMTW output compare output pins Real time clock (RTC) RTCAT1HZ Output RTC 1 Hz output pin RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 16 of 127

Table 1.18 Pin functions (4 of 7) Classification Pin name I/O Description Serial communication interface (SCI) SCK0 to SCK5 I/O Clock I/O pins (clock synchronous mode/simple SPI mode/smart card mode) RXD0 to RXD5 Input Input the receive data (asynchronous mode/clock synchronous mode/smart card mode) TXD0 to TXD5 Output Output the transmit data (asynchronous mode/clock synchronous mode/smart card mode) CTS0# to CTS5# Input Input the start of transmission (asynchronous mode/ clock synchronous mode) active-low RTS0# to RTS5# Output Output the reception (asynchronous mode/clock synchronous mode) active-low SCL0 to SCL5 I/O Input/output the I2C clocks (simple I2C mode) SDA0 to SDA5 I/O Input/output the I2C data (simple I2C mode) MISO0 to MISO5 I/O Input/output the data for slave transmission (simple SPI mode) MOSI0 to MOSI5 I/O Input/output the data for master transmission (simple SPI mode) SS0# to SS5# Input Chip-select input pins (simple SPI mode) active-low DE0 to DE5 Output Driver enable output pins (asynchronous mode) I2C bus interface (IIC) IIC_SCL0 to IIC_SCL2 I/O Clock I/O pins IIC_SDA0 to IIC_SDA2 I/O Data I/O pins Ethernet ETH0_TXCLK to ETH2_TXCLK I/O TX clock input pins (MII mode) TX clock output pins (RGMII mode) ETH0_TXD0 to ETH2_TXD0 Output TX data 0 pins (RGMII, RMII, and MII modes) ETH0_TXD1 to ETH2_TXD1 Output TX data 1 pins (RGMII, RMII, and MII modes) ETH0_TXD2 to ETH2_TXD2 Output TX data 2 pins (RGMII and MII modes) ETH0_TXD3 to ETH2_TXD3 Output TX data 3 pins (RGMII and MII modes) ETH0_TXEN to ETH2_TXEN Output TX data enable pins (RMII and MII modes) TX data enable/TX data error (TX_CTL) pins (RGMII mode) ETH0_TXER to ETH2_TXER Output TX data error pins (MII mode) ETH0_RXCLK to ETH2_RXCLK Input RX clock pins (RGMII, RMII, and MII modes) ETH0_RXD0 to ETH2_RXD0 Input RX data 0 pins (RGMII, RMII, and MII modes) ETH0_RXD1 to ETH2_RXD1 Input RX data 1 pins (RGMII, RMII, and MII modes) ETH0_RXD2 to ETH2_RXD2 Input RX data 2 pins (RGMII and MII modes) ETH0_RXD3 to ETH2_RXD3 Input RX data 3 pins (RGMII and MII modes) ETH0_RXDV to ETH2_RXDV Input RX data valid pins (MII mode) Carrier sense/RX data valid (CRS_DV) pins (RMII mode) RX data valid/RX error (RX_CTL) pins (RGMII mode) ETH0_RXER to ETH2_RXER Input RX data error pins (RMII and MII modes) ETH0_CRS to ETH2_CRS Input Carrier sense pins (MII mode) ETH0_COL to ETH2_COL Input Collision detection pins (MII mode) Ethernet MAC (GMAC) GMAC_PTPTRG0 Input PTP timer trigger external input 0 GMAC_PTPTRG1 Input PTP timer trigger external input 1 GMAC_MDC Output Management data clock output pin GMAC_MDIO I/O Management data I/O pin RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 17 of 127

Table 1.18 Pin functions (5 of 7) Classification Pin name I/O Description Ethernet switch (ETHSW) ETHSW_LPI0 Output Port 0 MAC status indicates that it is currently receiving low-power-idle sequences from the PHY ETHSW_LPI1 Output Port 1 MAC status indicates that it is currently receiving low-power-idle sequences from the PHY ETHSW_LPI2 Output Port 2 MAC status indicates that it is currently receiving low-power-idle sequences from the PHY ETHSW_PTPOUT0 to ETHSW_PTPOUT3 Output Ethernet switch timer pulse output pins ETHSW_TDMAOUT0 to ETHSW_TDMAOUT3 Output Ethernet switch TDMA timer output pins ETHSW_PHYLINK0 to ETHSW_PHYLINK2 Input Ethernet switch PHY link status input pins ETHSW_MDC Output Management data clock output pin ETHSW_MDIO I/O Management data I/O pin EtherCAT slave controller (ESC) ESC_LEDRUN Output Outputs the EtherCAT RUN LED signal ESC_IRQ Output Outputs the EtherCAT IRQ signal ESC_LEDSTER Output Outputs the EtherCAT Dual-color state LED signal ESC_LEDERR Output Outputs the EtherCAT error LED signal ESC_LINKACT0 to ESC_LINKACT2 Output Output the EtherCAT link/activity LED signal ESC_SYNC0, ESC_SYNC1 Output Output the EtherCAT SYNC signal ESC_LATCH0, ESC_LATCH1 Input Input the EtherCAT LATCH signal ESC_RESETOUT# Output Output the EtherCAT reset signal ESC_I2CCLK Output Outputs the EtherCAT EEPROM I2C clock signal ESC_I2CDATA I/O Inputs and outputs the EtherCAT EEPROM I2C data signal ESC_PHYLINK0 to ESC_PHYLINK2 Input Inputs the EtherCAT PHY link status signal. ESC_MDC Output Management data clock output pin ESC_MDIO I/O Management data I/O pin USB 2.0 host/function module VCC33_USB Input Power supply input pin for USB VCC18_USB Input Power supply input pin for USB VSS_USB Input Ground input pins for USB AVCC18_USB Input Analog power supply input pin for USB USB_RREF Input Reference current input pin for USB. Connect this pin to the VSS_USB pin with 1.8 kΩ (±1%). USB_DP I/O USB bus D+ data I/O pin USB_DM I/O USB bus D- data I/O pin USB_VBUSEN Output Outputs the VBUS power enable signal for USB USB_OVRCUR Input Inputs the overcurrent signal for USB USB_VBUSIN Input USB cable connection/disconnection detection input pin USB_EXICEN Output OTG power supply IC control pin USB_OTGID Input OTG ID pin RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 18 of 127

Table 1.18 Pin functions (6 of 7) Classification Pin name I/O Description CANFD module (CANFD) CANRX0, CANRX1 Input Receive data input pins CANTX0, CANTX1 Output Transmit data output pins CANRXDP0, CANRXDP1 Output Receive data phase output pins CANTXDP0, CANTXDP1 Output Transmit data phase output pins Serial peripheral interface (SPI) SPI_RSPCK0 to SPI_RSPCK3 I/O Clock I/O pins SPI_MOSI0 to SPI_MOSI3 I/O Master transmit data I/O pins SPI_MISO0 to SPI_MISO3 I/O Slave transmit data I/O pins SPI_SSL00 to SPI_SSL30 I/O Slave select signal I/O pins SPI_SSL01 to SPI_SSL31, SPI_SSL02 to SPI_SSL32, SPI_SSL13 to SPI_SSL33 Output Slave select signal output pins Expanded serial peripheral interface (xSPI) XSPI0_CKP, XSPI1_CKP, XSPI0_CKN Output Clock output pins XSPI0_CS0#, XSPI1_CS0#, XSPI0_CS1# Output Chip select output pins XSPI0_DS, XSPI1_DS I/O Read data strobe/write data mask input/output pin XSPI0_IO0 to XSPI0_IO7, XSPI1_IO0 to XSPI1_IO7 I/O Data0 to Data7 input/output pins XSPI0_RESET0#, XSPI0_RESET1# Output Master reset status output pins XSPI0_RSTO0#, XSPI0_RSTO1# Input Slave reset status input pins XSPI0_INT0#, XSPI0_INT1# Input Interrupt input pins XSPI0_ECS0#, XSPI0_ECS1# Input Error correction status input pins XSPI0_WP0#, XSPI0_WP1# Output Write protect output pins ΔΣ interface (DSMIF) MCLK0 to MCLK5 I/O Clock I/O pins MDAT0 to MDAT5 Input Data input pins 12-bit A/D converter (ADC12) AN000 to AN003, AN100 to AN107 Input Analog input pins for the A/D converter ADTRG0#, ADTRG1# Input External trigger input pins for the start of A/D conversion Serial host interface (SHOSTIF) HSPI_CK Input Clock input pin HSPI_CS# Input Chip select input pin HSPI_IO0 to HSPI_IO7 I/O Data0 to Data7 input/output pins HSPI_INT# Output Interrupt output pin RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 19 of 127

Table 1.18 Pin functions (7 of 7) Classification Pin name I/O Description Parallel host interface (PHOSTIF) HCKIO Input Bus clock input pin HA0 to HA20 Input Address input pins HD0 to HD15 I/O Data I/O pins HCS0# Input Chip select input pin supporting burst transfer HCS1# Input Chip select input pin supporting BSC ADMUX mode HRD# Input Strobe input pin indicating a read access HWAIT# Output Output pin indicating that the bus cycle is in wait state HWRSTB# Input Strobe input pin indicating a write access HWR0# Input Write strobe/byte enable input pin to HD7 to HD0 HWR1# Input Write strobe/byte enable input pin to HD15 to HD8 HERROUT# Output Outputs the bus access error interrupt signal HBS# Input Bus cycle input pin Mailbox and Semaphore (MBXSEM) MBX_HINT# Output Mailbox (Cortex-R52 to Host CPU) interrupt output pin Analog power supply VCC18_ADC0, VCC18_ADC1 Input Analog power supply input pin for the 12-bit A/D converter. Connect this pin to the 1.8 V power supply if the 12-bit A/D converter is not to be used. VREFH0, VREFH1 Input Reference voltage input pin for the 12-bit A/D converter. Connect this pin to the 1.8 V power supply if the 12-bit A/D converter is not to be used. I/O ports P00_0 to P24_2 I/O General-purpose input/output pins RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 20 of 127

1.6 FBGA 225 Pin Assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS P01_0 P00_2 P00_4 P24_0 P22_1 P22_0 P21_3 VSS AN106 AN104 AN103 AN101 VSS P01_5 P01_2 P00_3 P00_5 P24_1 P22_3 P21_7 P21_1 AN105 AN102 AN100 AN000 AN002 P19_0 P01_7 P01_3 P00_6 P00_0 P24_2 P22_2 P21_5 P21_2 VREFH1 VREFH0 AN001 AN003 AVCC18_ TSU P18_6 P02_1 P01_6 P01_1 P00_7 P00_1 P23_7 P21_6 P20_2 VSS VSS VSS P18_5 P18_2 P18_1 P02_3 TRST# P02_0 P01_4 VCC 1833_2 VCC33 P21_4 VCC33 VSS VCC18_ ADC0 P18_4 P18_3 P18_0 P17_7 P02_7 P02_5 P02_2 P02_4 P02_6 VDD VSS VDD P04_0 P04_1 P04_5 P04_4 P04_6 VDD VSS VSS VSS VDD P16_1 P15_6 P15_4 P16_2 P16_5 P04_7 P05_1 P05_3 P05_2 P05_0 VDD VSS VSS VSS VDD VCC 1833_3 P14_5 P14_4 P15_5 P15_7 P05_4 P05_5 P05_6 P06_3 VCC 1833_1 VDD VDD VDD VSS VDD P15_3 P14_2 P14_6 P15_1 P15_2 VSS P06_0 P06_1 P06_6 VCC33 VCC 1833_0 P09_7 P10_2 P10_3 P13_2 P15_0 P13_4 P14_0 P14_1 VSS P05_7 P06_2 P06_7 P07_3 P08_6 P09_4 P09_6 P10_1 P10_4 VCC33 P13_7 P13_5 P13_6 P14_3 P14_7 P06_4 P06_5 P07_1 P08_4 P08_7 P09_2 P09_5 P10_0 VCC18_ PLL1 VSS P12_4 P13_3 VSS_ USB VSS VSS_ USB A B C D E F H J K L M N P R P07_0 P07_2 P08_5 P09_0 MDX RES# VDD VSS VCC18_ PLL0 AVCC18_ USB VCC18_ USB VSS_ USB USB_ DM VSS_ USB USB_ RREF VSS P07_4 P09_1 P09_3 VSS EXT CLKIN EXTAL XTAL VSS AVCC18_ USB VCC33_ USB VSS_ USB USB_DP VSS_ USB VSS P03_5 BSCANP P03_0 P03_6 P03_7 VDD VSS VSS VDD VCC 1833_4 P17_0 P17_4 P17_3 P17_5 G VSS VDD P16_6 P16_3 P16_0 P16_7 P17_6 VDD VCC18_ ADC1 P20_3 AN107 P20_1 P20_4 A B C D E F H J K L M N P R G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 1.2 Pin arrangement (225-pin FBGA) (top view) Table 1.19 List of pins and pin functions (225-pin FBGA) (1 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF A2 VCC1833_2 — P01_0 CAS# MTIOC4C / GTIOC3A GMAC_MDIO / ETHSW_MDIO / ESC_MDIO / CTS2# MCLK1 — — — A3 VCC1833_2 — P00_2 RD# MTIC5V ETH2_TXEN / TXD2 / SDA2 / MOSI2 / USB_OVRCUR — — — — A4 VCC1833_2 — P00_4 WAIT# MTIOC3A / GTIOC0A ETH2_RXER MCLK0 IRQ13 — HWAIT# A5 VCC1833_2 — P24_0 D12 / CKE / DREQ MTIOC0B / GTETRGB ETH2_RXD1 / RXD1 / SCL1 / MISO1 MDAT4 — — HD12 A6 — TRACECTL P22_1 D8 GTETRGB / POE4# ESC_LINKACT2 / SS4# / CTS4# / RTS4# — — — HD8 A7 — TRACEDATA7 P22_0 D7 MTIOC7D / GTIOC17B DE5 MDAT3 IRQ15 — HD7 A8 — TRACEDATA2 P21_3 D2 MTIOC6C / GTIOC15A TXD5 / SDA5 / MOSI5 / SPI_SSL33 MCLK1 — — HD2 A9 — MDV3 P20_4 — — ETHSW_TDMAOUT3 / ETHSW_PTPOUT0 / ESC_LINKACT1 — — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 21 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (2 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF B1 VCC1833_2 — P01_5 WE0# / DQMLL — ETH2_TXD0 — — — — B2 VCC1833_2 — P01_2 CS2# MTIOC4B / GTIOC2B ETH2_TXD3 — IRQ2 — — B3 VCC1833_2 — P00_3 RD/WR# MTIC5W ETH2_REFCLK / RMII2_REFCLK / SS2# / CTS2# / RTS2# — IRQ1 — — B4 VCC1833_2 — P00_5 CS0# MTIOC3C / GTIOC0B ETHSW_PHYLINK2 / ETHSW_PHYLINK0 / ESC_PHYLINK2 / ESC_PHYLINK0 MDAT0 — — — B5 VCC1833_2 — P24_1 D13 / CAS# MTIOC0C / GTETRGC / POE8# ETH2_RXCLK MCLK5 — — HD13 B6 — — P22_3 D10 MTIOC8D / GTETRGSB RXD5 / SCL5 / MISO5 — — — HD10 B7 — TRACEDATA6 P21_7 D6 / DREQ MTIOC7C / GTIOC17A DE0 MCLK3 IRQ10 — HD6 B8 — TRACEDATA0 P21_1 D0 MTIOC6A / GTIOC14A / CMTW0_TIC0 ESC_SYNC0 / ESC_SYNC1 / SCK5 / SPI_SSL20 / IIC_SCL1 MCLK0 — — HSPI_INT # / HD0 B9 — MDV0 P20_1 — — ETHSW_TDMAOUT0 / ETHSW_PTPOUT3 / ESC_LINKACT0 — — — — B15 VCC1833_4 MDV4 P19_0 — — USB_VBUSEN — — — — C1 — TRACEDATA1 P01_7 A19 MTIOC1B / GTIOC9B ETHSW_LPI1 / SCK1 / SPI_RSPCK3 / CANRX0 — — ADTRG0# HA19 C2 VCC1833_2 — P01_3 AH# MTIOC4D / GTIOC3B ETH2_TXD2 — — — — C3 VCC1833_2 — P00_6 CS5# MTIOC3B / GTIOC1A ETH2_TXCLK — — — — C4 VCC1833_2 — P00_0 D15 — ETH2_RXD3 / SCK2 / DE2 — — — HD15 C5 VCC1833_2 — P24_2 D14 / RAS# MTIOC0D / GTETRGD ETH2_RXD2 / TXD1 / SDA1 / MOSI1 MDAT5 — — HD14 C6 — TRACECLK P22_2 D9 MTIOC8C / GTETRGSA SPI_SSL12 MCLK1 IRQ4 — HD9 C7 — TRACEDATA4 P21_5 D4 MTIOC7A / GTIOC16A / CMTW1_TOC1 CTS5# / SPI_MISO0 MCLK2 IRQ6 ADTRG1# HD4 C8 — TRACEDATA1 P21_2 D1 MTIOC6B / GTIOC14B / CMTW0_TIC1 ESC_SYNC0 / ESC_SYNC1 / RXD5 / SCL5 / MISO5 / SPI_MISO2 / IIC_SDA1 MDAT0 — — HD1 C15 VCC1833_4 TRACECLK P18_6 — MTIC5W XSPI1_IO7 / ETH1_COL / SCK4 / DE4 / SPI_MISO2 / IIC_SCL2 — IRQ11 ADTRG0# — D1 — — P02_1 A17 — ETHSW_PTPOUT1 / ESC_SYNC1 / ESC_SYNC0 / DE1 — — — HA17 RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 22 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (3 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF D2 — TRACEDATA0 P01_6 A20 MTIOC1A / GTIOC9A GMAC_PTPTRG1 / ESC_LATCH1 / ESC_LATCH0 / CTS1# / CANTXDP1 — — — HA20 D3 VCC1833_2 — P01_1 CKE MTIOC3D / GTIOC1B GMAC_MDC / ETHSW_MDC / ESC_MDC / DE2 MDAT1 — — — D4 VCC1833_2 — P00_7 RAS# MTIOC4A / GTIOC2A — — IRQ13 — — D5 VCC1833_2 — P00_1 A13 MTIC5U ETH2_RXDV / RXD2 / SCL2 / MISO2 — IRQ0 — — D6 VCC1833_2 — P23_7 D11 / BS# MTIOC0A / GTETRGA ETH2_RXD0 / SCK1 MCLK4 — — HD11 D7 — TRACEDATA5 P21_6 D5 / TEND MTIOC7B / GTIOC16B CTS0# MDAT2 IRQ9 — HD5 D8 — MDV1 P20_2 — — ETHSW_TDMAOUT1 / ETHSW_PTPOUT2 / ESC_LEDRUN / ESC_LEDSTER / DE3 — — — — D9 — MDV2 P20_3 — — ETHSW_TDMAOUT2 / ETHSW_PTPOUT1 / ESC_LEDERR — — — — D13 VCC1833_4 TRACECTL P18_5 RAS# MTIC5V XSPI1_IO6 / ETH2_COL / RXD4 / SCL4 / MISO4 / SPI_MOSI2 / CANRX0 — — — — D14 VCC1833_4 — P18_2 BS# MTIOC4B / MTIOC4D / GTIOC2B / GTIOC3B XSPI1_CS0# / ETH1_COL / SCK0 / IIC_SDA2 — — — — D15 VCC1833_4 — P18_1 WE1# / DQMLU MTIOC3D / GTIOC1B SS3# / CTS3# / RTS3# — IRQ10 ADTRG1# HSPI_IO7 / HWR1# E1 — — P02_3 A15 / AH# MTIOC2B / GTIOC10B / POE11# ETHSW_TDMAOUT1 / SS1# / CTS1# / RTS1# / SPI_SSL30 / CANRX1 — IRQ15 — HA15 E3 — TRACEDATA2 P02_0 A18 GTADSML0 ETHSW_LPI2 / RXD1 / SCL1 / MISO1 / SPI_MISO3 / CANTX1 / USB_OTGID — IRQ4 — HA18 E4 VCC1833_2 — P01_4 WE1# / DQMLU POE0# ETH2_TXD1 — IRQ3 — — E7 — TRACEDATA3 P21_4 D3 MTIOC6D / GTIOC15B ETHSW_PTPOUT1 / ESC_SYNC0 / ESC_SYNC1 / SS5# / CTS5# / RTS5# / SPI_SSL02 MDAT1 / MBX_HI NT# — — HD3 E12 VCC1833_4 — P18_4 CAS# MTIC5U XSPI1_IO5 / ETH1_CRS / TXD4 / SDA4 / MOSI4 / SPI_RSPCK2 / CANTX0 — IRQ1 — — E13 VCC1833_4 — P18_3 CKE MTIOC4D / MTIOC4B / GTIOC3B / GTIOC2B / CMTW1_TIC1 XSPI1_IO4 / ETH2_CRS / CANRXDP1 — IRQ0 — — E14 VCC1833_4 — P18_0 WE0# / DQMLL MTIOC4C / MTIOC4A / GTIOC3A / GTIOC2A TXD3 / SDA3 / MOSI3 — — — HSPI_IO6 / HWR0# RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 23 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (4 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF E15 VCC1833_4 — P17_7 RD# / DACK MTIOC4A / MTIOC4C / GTIOC2A / GTIOC3A XSPI1_CKP / RXD3 / SCL3 / MISO3 — — — HRD# F1 — TCK P02_7 — — TXD5 / SDA5 / MOSI5 — — — — F2 — TDI P02_5 WE1# / DQMLU — ETHSW_TDMAOUT3 / SCK5 / SPI_SSL31 — — — — F3 — — P02_2 A16 MTIOC2A / GTIOC10A / POE10# / RTCAT1HZ ETHSW_TDMAOUT0 / TXD1 / SDA1 / MOSI1 / SPI_MOSI3 / CANTX0 — IRQ14 — HA16 F4 — TDO P02_4 WE0# / DQMLL — DE1 / SPI_SSL33 — — — — F5 — TMS P02_6 — — RXD5 / SCL5 / MISO5 — — — — F12 VCC1833_4 MDD P17_0 — — XSPI1_IO1 / ESC_IRQ / SS0# / CTS0# / RTS0# — — — — F13 VCC1833_4 TRACECLK P17_4 DACK MTIOC3C / GTETRGB / GTIOC0A XSPI1_IO3 / CTS3# / SPI_SSL32 — — — — F14 VCC1833_4 TRACECTL P17_3 DREQ GTETRGA / POE0# XSPI1_IO2 / SPI_SSL31 — — ADTRG1# — F15 VCC1833_4 RSTOUT# P17_5 TEND MTIOC3A / GTETRGC / GTIOC0B G1 — — P03_5 A12 MTIOC3A / GTIOC4A ETH2_CRS / RXD2 / SCL2 / MISO2 MCLK2 IRQ5 — HA12 G3 — TRACEDATA3 P03_0 A14 / CS5# GTADSML1 SCK2 / SPI_SSL32 / CANTXDP1 — IRQ14 — HA14 G4 — TRACEDATA4 P03_6 A11 MTIOC3B / GTIOC4B ETH2_COL / TXD2 / SDA2 / MOSI2 / SPI_SSL13 MDAT2 IRQ8 — HA11 G5 — TRACEDATA5 P03_7 A10 MTIOC3C / GTIOC5A ETH2_TXER / SCK3 — IRQ9 — HA10 G11 VCC1833_4 — P16_6 CS0# MTIC5V RXD0 / SCL0 / MISO0 — IRQ8 — HSPI_IO5 / HCS0# G12 VCC1833_3 — P16_3 CS3# GTADSMP1 XSPI0_RSTO0# / ETH1_TXER / ETH1_CRS / SCK0 / SPI_SSL30 — IRQ7 — HSPI_IO3 G13 VCC1833_3 — P16_0 — — XSPI0_CS1# / ETH0_TXER / ETH2_REFCLK / TXD0 / SDA0 / MOSI0 / SPI_MOSI3 MCLK3 — — HSPI_CS G14 VCC1833_4 — P16_7 A13 MTIC5W XSPI1_IO0 / SCK0 — — — HA13 G15 VCC1833_4 — P17_6 RD/WR# MTIOC3B / GTIOC1A XSPI1_DS / SCK3 — — — HWRSTB H1 — TRACEDATA6 P04_0 A9 MTIOC3D / GTIOC5B RXD3 / SCL3 / MISO3 — — — HA9 H2 — — P04_1 CKIO — TXD3 / SDA3 / MOSI3 / SPI_MOSI0 / IIC_SDA2 — — — HCKIO H3 — MD0 P04_5 A7 — ETHSW_PTPOUT0 / ESC_SYNC0 / ESC_SYNC1 / DE3 — — — HA7 RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 24 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (5 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF H4 — TRACEDATA7 P04_4 A8 GTADSMP0 / POE10# CTS3# / SPI_RSPCK1 — IRQ10 — HA8 H5 — MD1 P04_6 A6 / DACK RTCAT1HZ ETH1_TXER — — — HA6 H11 VCC1833_3 — P16_1 CS2# CMTW0_TOC1 XSPI0_RESET0# / RXD0 / SCL0 / MISO0 / SPI_MISO3 MDAT3 — ADTRG0# HCS1# H12 VCC1833_3 — P15_6 D14 — XSPI0_IO7 / SPI_SSL12 MDAT2 — — — H13 VCC1833_3 — P15_4 D12 MTIOC8D XSPI0_IO5 MDAT1 — — — H14 VCC1833_3 — P16_2 — — XSPI0_RESET1# / CTS0# / SPI_RSPCK3 / USB_EXICEN — NMI — HSPI_IO2 HERROU H15 VCC1833_4 — P16_5 A15 MTIC5U TXD0 / SDA0 / MOSI0 — — — HSPI_IO4 J1 — MD2 P04_7 A5 — ETH0_TXER / ETH2_TXER / SPI_SSL21 — — — HA5 J2 — — P05_1 A3 MTIOC4B / GTIOC6B / CMTW0_TIC1 ETH1_COL / CTS5# / CANRXDP0 / USB_EXICEN MDAT3 IRQ13 — HA3 J3 — — P05_3 A1 MTIOC4D / GTETRGSB / GTIOC7B / POE11# / CMTW0_TIC0 ETH0_COL / SCK4 / IIC_SDA1 / CANTX0 / USB_EXICEN — IRQ15 — HA1 J4 — — P05_2 A2 / DREQ MTIOC4C / GTETRGSA / GTIOC7A / CMTW0_TOC0 ETH0_CRS / DE5 / IIC_SCL1 / CANRX0 / USB_VBUSEN — IRQ14 — HA2 J5 — — P05_0 A4 MTIOC4A / GTIOC6A / CMTW0_TOC0 ETH1_CRS / SS5# / CTS5# / RTS5# / CANTXDP0 / USB_VBUSEN MCLK3 IRQ12 — HA4 J12 VCC1833_3 — P14_5 CS3# POE8# XSPI0_CKN — — — HSPI_INT J13 VCC1833_3 — P14_4 BS# MTIOC0B XSPI0_DS / ESC_IRQ — — — HBS# J14 VCC1833_3 — P15_5 D13 — XSPI0_IO6 MCLK2 — — — J15 VCC1833_3 — P15_7 TEND — XSPI0_CS0# / CTS5# / SPI_SSL13 — — — — K1 VCC1833_1 — P05_4 A0 / DACK GTIOC14A ETHSW_LPI0 / RXD4 / SCL4 / MISO4 / SPI_SSL00 / CANTXDP0 / USB_OVRCUR — IRQ12 — HA0 K2 VCC1833_1 — P05_5 — GTIOC14B / CMTW0_TOC1 ETHSW_PHYLINK1 / ESC_PHYLINK1 / SPI_RSPCK2 — — — — K3 VCC1833_1 — P05_6 — GTIOC15A / CMTW1_TIC0 ETH1_RXER / SPI_SSL22 — IRQ12 — — K4 VCC1833_1 — P06_3 D3 GTIOC17B / CMTW1_TIC1 ETH1_TXD0 / DE4 / SPI_MISO1 / CANTXDP1 — — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 25 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (6 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF K11 VCC1833_3 — P15_3 D11 MTIOC8C XSPI0_IO4 MCLK1 — — — K12 VCC1833_3 — P14_2 — MTIOC8B / GTIOC8B XSPI0_ECS0# / ETH0_CRS / ETH2_CRS — IRQ6 — HSPI_CK K13 VCC1833_3 — P14_6 A21 — XSPI0_CKP — — — — K14 VCC1833_3 — P15_1 A24 / CAS# MTIOC0C XSPI0_IO2 / TXD5 / SDA5 / MOSI5 / SPI_SSL10 — — — — K15 VCC1833_3 — P15_2 A25 / RAS# MTIOC0D XSPI0_IO3 / SS5# / CTS5# / RTS5# / SPI_SSL11 — — — — L2 VCC1833_1 — P06_0 D0 GTIOC16A / CMTW1_TOC0 ETH1_TXD3 / SS4# / CTS4# / RTS4# / SPI_SSL23 / CANRX1 — — — — L3 VCC1833_1 — P06_1 D1 GTIOC16B ETH1_REFCLK / RMII1_REFCLK / CTS4# / SPI_SSL22 / CANTX1 — — — — L4 VCC1833_1 — P06_6 D6 GTIOC12A ETH1_RXD0 / SPI_SSL10 — — — — L9 VCC1833_0 — P10_3 — RTCAT1HZ ETH0_RXD2 — — — — L10 — TRACEDATA6 P13_2 D9 / A13 MTIOC0A / GTIOC10A / POE8# ETHSW_PTPOUT2 / ESC_I2CCLK / SS1# / CTS1# / RTS1# / SPI_MISO0 / IIC_SCL0 MCLK4 IRQ5 — — L11 VCC1833_3 — P15_0 A23 / CKE — XSPI0_IO1 / RXD5 / SCL5 / MISO5 / SPI_MOSI1 — — — — L12 — — P13_4 A0 MTIOC0D / GTIOC8B ESC_RESETOUT# — — — — L13 VCC1833_3 — P14_0 — MTCLKD XSPI0_INT0# / ETHSW_PTPOUT1 / ESC_SYNC1 / ESC_SYNC0 — — — — L14 VCC1833_3 — P14_1 — MTIOC8A / GTIOC8A XSPI0_INT1# / ETH1_COL / GMAC_PTPTRG1 / ESC_LATCH0 / ESC_LATCH1 — — — HSPI_IO0 M1 VCC1833_1 — P05_7 — GTIOC15B / CMTW1_TOC1 ETH1_TXD2 / TXD4 / SDA4 / MOSI4 / SPI_SSL23 — — — — M2 VCC1833_1 — P06_2 D2 GTIOC17A ETH1_TXD1 / CANRXDP1 — — — — M3 VCC1833_1 — P06_7 D7 GTIOC12B ETH1_RXD1 / SPI_SSL11 — — — — M5 VCC1833_0 — P08_6 — MTIOC6C ETH0_RXCLK — — — — M9 VCC1833_0 — P10_4 — — ETHSW_PHYLINK0 / ESC_PHYLINK0 — IRQ11 — — M11 VCC1833_3 — P13_7 — MTCLKC XSPI0_ECS1# / GMAC_PTPTRG1 / ESC_LATCH1 / ESC_LATCH0 MBX_HI NT# — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 26 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (7 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF M12 VCC1833_3 — P13_5 — MTCLKA XSPI0_WP1# / GMAC_PTPTRG0 / ESC_LATCH0 / ESC_LATCH1 / SPI_RSPCK1 / IIC_SCL2 — — — — M13 VCC1833_3 — P13_6 — MTCLKB XSPI0_WP0# / ETHSW_PTPOUT0 / ESC_SYNC0 / ESC_SYNC1 — — — — M14 VCC1833_3 — P14_3 — MTIOC0A XSPI0_RSTO1# / ETH0_COL / ETH2_COL — — — HSPI_IO1 M15 VCC1833_3 — P14_7 A22 / BS# — XSPI0_IO0 / SCK5 / SPI_MISO1 — — — — N1 VCC1833_1 — P06_4 D4 GTIOC11A ETH1_TXCLK / SPI_MOSI1 — — — — N2 VCC1833_1 — P06_5 D5 GTIOC11B ETH1_TXEN — — — — N3 VCC1833_1 — P07_1 — GTIOC13B ETH1_RXD3 — — — — N4 VCC1833_0 — P08_4 — MTIOC6A ETH0_RXD3 — — — — N5 VCC1833_0 — P08_7 — MTIOC6D GMAC_MDC / ETHSW_MDC / ESC_MDC — — — — N6 VCC1833_0 — P09_2 — MTIOC7C ETH0_RXER — IRQ0 — — N11 — TRACEDATA0 P12_4 D15 MTIOC8B / GTIOC8B ETH1_CRS / SPI_SSL01 MBX_HI NT# — — — N12 — TRACEDATA7 P13_3 D8 / RD# MTIOC0C / MTIOC0B / GTIOC10B / CMTW1_TOC0 ETHSW_PTPOUT3 / ESC_I2CDATA / CTS1# / SPI_RSPCK0 / IIC_SDA0 MDAT4 — — — P1 VCC1833_1 — P07_0 — GTIOC13A ETH1_RXD2 — — — — P3 VCC1833_0 — P08_5 — MTIOC6B ETH0_RXDV — — — — P4 VCC1833_0 — P09_0 — MTIOC7A GMAC_MDIO / ETHSW_MDIO / ESC_MDIO — — — — R3 VCC1833_0 — P09_1 — MTIOC7B ETH0_REFCLK / RMII0_REFCLK — — — — R4 VCC1833_0 — P09_3 — MTIOC7D ETH0_TXD3 — — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 27 of 127

Table 1.19 List of pins and pin functions (225-pin FBGA) (8 of 8) Pin number I/O power domain Power supply clock system control I/O port Bus, DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD, USB) Others (DSMIF, Mailbox) Interrupt ADC12 Host interface (SHOSTI PHOSTIF RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 28 of 127

1.7 FBGA 121 Pin Assignments

VSS P01_2 P00_5 P00_4 P24_2 P24_1 P24_0 P21_1 P20_4 VSS P01_5 P01_4 P00_6 P00_2 P00_0 P23_7 P21_3 P20_2 P18_6 P18_4 P02_5 P01_3 TRST# VCC 1833_2 P00_1 VCC33 P21_4 P20_3 P18_3 P17_5 P02_7 P02_4 P02_6 VDD VSS VDD VDD AVCC18 _TSU P17_0 P16_5 P04_6 P04_5 BSCANP VCC33 VSS VSS VSS VSS P16_3 P16_2 VSS P04_7 P05_5 VDD VDD VSS VSS VDD P06_1 P06_0 P06_6 P06_3 VSS VDD VCC33 VCC33 P15_0 P14_7 P15_1 P06_4 P06_2 P07_1 VCC33 RES# VSS VCC18_ PLL0 VSS P14_2 P14_3 P14_6 P06_5 P06_7 P07_3 P08_7 MDX VCC 1833_0 EXT CLKIN VCC18 _PLL1 P13_3 P13_5 P14_1 VSS P07_0 P07_2 P09_0 VSS EXTAL XTAL VSS P13_2 P13_4 VSS A B C D E F H J K L P05_6 P05_7 VCC 1833_1 VSS VDD VDD VDD VSS P16_0 VSS G VCC 1833_3 P15_2 P15_7 P16_6 VCC 1833_4 P18_2 P18_5 P20_1 P21_2 A B C D E F H J K L G 1 2 3 4 5 6 7 8 9 10 11 Figure 1.3 Pin arrangement (121-pin FBGA) (top view) Table 1.20 List of pins and pin functions (121-pin FBGA) (1 of 4) Pin number I/O power domain Power supply clock system control I/O port DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD) Others (DSMIF, Mailbox) Interrupt Host interface (SHOSTI A2 VCC1833_2 — P01_2 — MTIOC4B / GTIOC2B ETH2_TXD3 — IRQ2 — A3 VCC1833_2 — P00_5 — MTIOC3C / GTIOC0B ETHSW_PHYLINK2 / ETHSW_PHYLINK0 / ESC_PHYLINK0 MDAT0 — — A4 VCC1833_2 — P00_4 — MTIOC3A / GTIOC0A ETH2_RXER MCLK0 IRQ13 — A5 VCC1833_2 — P24_2 — MTIOC0D / GTETRGD ETH2_RXD2 / TXD1 / SDA1 / MOSI1 MDAT5 — — A6 VCC1833_2 — P24_1 — MTIOC0C / GTETRGC / POE8# ETH2_RXCLK MCLK5 — — A7 VCC1833_2 — P24_0 DREQ MTIOC0B / GTETRGB ETH2_RXD1 / RXD1 / SCL1 / MISO1 MDAT4 — — A8 — TRACEDATA0 P21_1 — MTIOC6A / GTIOC14A / CMTW0_TIC0 ESC_SYNC0 / ESC_SYNC1 / SCK5 / SPI_SSL20 / IIC_SCL1 MCLK0 — HSPI_INT A9 — TRACEDATA1 P21_2 — MTIOC6B / GTIOC14B / CMTW0_TIC1 ESC_SYNC0 / ESC_SYNC1 / RXD5 / SCL5 / MISO5 / SPI_MISO2 / IIC_SDA1 MDAT0 — — A10 — MDV3 P20_4 — — ETHSW_TDMAOUT3 / ETHSW_PTPOUT0 / ESC_LINKACT1 — — — B2 VCC1833_2 — P01_4 — POE0# ETH2_TXD1 — IRQ3 — B3 VCC1833_2 — P00_6 — MTIOC3B / GTIOC1A ETH2_TXCLK — — — B4 VCC1833_2 — P00_2 — MTIC5V ETH2_TXEN / TXD2 / SDA2 / MOSI2 — — — B5 VCC1833_2 — P00_0 — — ETH2_RXD3 / SCK2 / DE2 — — — B6 VCC1833_2 — P23_7 — MTIOC0A / GTETRGA ETH2_RXD0 / SCK1 MCLK4 — — B7 — TRACEDATA2 P21_3 — MTIOC6C / GTIOC15A TXD5 / SDA5 / MOSI5 MCLK1 — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 29 of 127

Table 1.20 List of pins and pin functions (121-pin FBGA) (2 of 4) Pin number I/O power domain Power supply clock system control I/O port DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD) Others (DSMIF, Mailbox) Interrupt Host interface (SHOSTI B8 — MDV1 P20_2 — — ETHSW_TDMAOUT1 / ETHSW_PTPOUT2 / ESC_LEDRUN / ESC_LEDSTER — — — B9 — MDV0 P20_1 — — ETHSW_TDMAOUT0 / ETHSW_PTPOUT3 / ESC_LINKACT0 — — — B10 VCC1833_4 TRACECLK P18_6 — MTIC5W ETH1_COL / SCK4 / DE4 / SPI_MISO2 / IIC_SCL2 — IRQ11 — B11 VCC1833_4 — P18_4 — MTIC5U ETH1_CRS / TXD4 / SDA4 / MOSI4 / SPI_RSPCK2 / CANTX0 — IRQ1 — C1 — TDI P02_5 — — ETHSW_TDMAOUT3 / SCK5 — — — C2 VCC1833_2 — P01_3 — MTIOC4D / GTIOC3B ETH2_TXD2 — — — C5 VCC1833_2 — P00_1 — MTIC5U ETH2_RXDV / RXD2 / SCL2 / MISO2 — IRQ0 — C7 — TRACEDATA3 P21_4 — MTIOC6D / GTIOC15B ETHSW_PTPOUT1 / ESC_SYNC0 / ESC_SYNC1 / SS5# / CTS5# / RTS5# MDAT1 / MBX_HIN — — C8 — MDV2 P20_3 — — ETHSW_TDMAOUT2 / ETHSW_PTPOUT1 / ESC_LEDERR — — — C9 VCC1833_4 TRACECTL P18_5 — MTIC5V ETH2_COL / RXD4 / SCL4 / MISO4 / SPI_MOSI2 / CANRX0 — — — C10 VCC1833_4 — P18_3 — MTIOC4D / MTIOC4B / GTIOC3B / GTIOC2B / CMTW1_TIC1 ETH2_CRS / CANRXDP1 — IRQ0 — C11 VCC1833_4 RSTOUT# P17_5 TEND# MTIOC3A / GTETRGC / GTIOC0B — — — — D1 — TCK P02_7 — — TXD5 / SDA5 / MOSI5 — — — D3 — TMS P02_6 — — RXD5 / SCL5 / MISO5 — — — D9 VCC1833_4 — P18_2 — MTIOC4B / MTIOC4D / GTIOC2B / GTIOC3B ETH1_COL / SCK0 / IIC_SDA2 — — — D10 VCC1833_4 MDD P17_0 — — ESC_IRQ / SS0# / CTS0# / RTS0# — — — D11 VCC1833_4 — P16_5 — MTIC5U TXD0 / SDA0 / MOSI0 — — — E1 — MD1 P04_6 DACK# RTCAT1HZ ETH1_TXER — — — E2 — MD0 P04_5 — — ETHSW_PTPOUT0 / ESC_SYNC0 / ESC_SYNC1 — — — E10 VCC1833_3 — P16_3 — GTADSMP1 XSPI0_RSTO0# / ETH1_TXER / ETH1_CRS / SCK0 — IRQ7 HSPI_IO3 E11 VCC1833_3 — P16_2 — — XSPI0_RESET1# / CTS0# — NMI HSPI_IO2 RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 30 of 127

Table 1.20 List of pins and pin functions (121-pin FBGA) (3 of 4) Pin number I/O power domain Power supply clock system control I/O port DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD) Others (DSMIF, Mailbox) Interrupt Host interface (SHOSTI F2 — MD2 P04_7 — — ETH2_TXER / SPI_SSL21 — — — F3 VCC1833_1 — P05_5 — GTIOC14B / CMTW0_TOC1 ETHSW_PHYLINK1 / ESC_PHYLINK1 / SPI_RSPCK2 — — — F9 VCC1833_4 — P16_6 — MTIC5V RXD0 / SCL0 / MISO0 — IRQ8 — F10 VCC1833_3 — P16_0 — — XSPI0_CS1# / ETH2_REFCLK / TXD0 / SDA0 / MOSI0 — — HSPI_CS G1 VCC1833_1 — P05_6 — GTIOC15A / CMTW1_TIC0 ETH1_RXER / SPI_SSL22 — IRQ12 — G2 VCC1833_1 — P05_7 — GTIOC15B / CMTW1_TOC1 ETH1_TXD2 / TXD4 / SDA4 / MOSI4 / SPI_SSL23 — — — G10 VCC1833_3 — P15_2 — MTIOC0D XSPI0_IO3 / SS5# / CTS5# / RTS5# / SPI_SSL11 — — — G11 VCC1833_3 — P15_7 TEND# — XSPI0_CS0# / CTS5# / SPI_SSL13 — — — H1 VCC1833_1 — P06_1 — GTIOC16B ETH1_REFCLK / RMII1_REFCLK / CTS4# / SPI_SSL22 / CANTX1 — — — H2 VCC1833_1 — P06_0 — GTIOC16A / CMTW1_TOC0 ETH1_TXD3 / SS4# / CTS4# / RTS4# / SPI_SSL23 / CANRX1 — — — H3 VCC1833_1 — P06_6 — GTIOC12A ETH1_RXD0 / SPI_SSL10 — — — H4 VCC1833_1 — P06_3 — GTIOC17B / CMTW1_TIC1 ETH1_TXD0 / DE4 / SPI_MISO1 / CANTXDP1 — — — H9 VCC1833_3 — P15_0 — — XSPI0_IO1 / RXD5 / SCL5 / MISO5 / SPI_MOSI1 — — — H10 VCC1833_3 — P14_7 — — XSPI0_IO0 / SCK5 / SPI_MISO1 — — — H11 VCC1833_3 — P15_1 — MTIOC0C XSPI0_IO2 / TXD5 / SDA5 / MOSI5 / SPI_SSL10 — — — J1 VCC1833_1 — P06_4 — GTIOC11A ETH1_TXCLK / SPI_MOSI1 — — — J2 VCC1833_1 — P06_2 — GTIOC17A ETH1_TXD1 / CANRXDP1 — — — J3 VCC1833_1 — P07_1 — GTIOC13B ETH1_RXD3 — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 31 of 127

Table 1.20 List of pins and pin functions (121-pin FBGA) (4 of 4) Pin number I/O power domain Power supply clock system control I/O port DMAC Timer (MTU3, POEG, GPT / POE3, CMTW, RTC) Communication (xSPI, GMAC, ETHSW, ESC, SCI, SPI, IIC, CANFD) Others (DSMIF, Mailbox) Interrupt Host interface (SHOSTI J9 VCC1833_3 — P14_2 — MTIOC8B / GTIOC8B XSPI0_ECS0 # / ETH2_CRS — IRQ6 HSPI_CK J10 VCC1833_3 — P14_3 — MTIOC0A XSPI0_RSTO1# / ETH2_COL — — HSPI_IO1 K1 VCC1833_1 — P06_5 — GTIOC11B ETH1_TXEN — — — K2 VCC1833_1 — P06_7 — GTIOC12B ETH1_RXD1 / SPI_SSL11 — — — K4 VCC1833_0 — P08_7 — MTIOC6D GMAC_MDC / ETHSW_MDC / ESC_MDC — — — K9 — — P13_3 — MTIOC0C / MTIOC0B / GTIOC10B / CMTW1_TOC0 ETHSW_PTPOUT3 / ESC_I2CDATA / CTS1# / IIC_SDA0 MDAT4 — — K10 VCC1833_3 — P13_5 — MTCLKA XSPI0_WP1# / GMAC_PTPTRG0 / ESC_LATCH0 / ESC_LATCH1 / SPI_RSPCK1 / IIC_SCL2 — — — K11 VCC1833_3 — P14_1 — MTIOC8A / GTIOC8A XSPI0_INT1# / ETH1_COL / GMAC_PTPTRG1 / ESC_LATCH0 / ESC_LATCH1 — — HSPI_IO0 L2 VCC1833_1 — P07_0 — GTIOC13A ETH1_RXD2 — — — L4 VCC1833_0 — P09_0 — MTIOC7A GMAC_MDIO / ETHSW_MDIO / ESC_MDIO — — — L9 — — P13_2 — MTIOC0A / GTIOC10A / POE8# ETHSW_PTPOUT2 / ESC_I2CCLK / SS1# / CTS1# / RTS1# / IIC_SCL0 MCLK4 IRQ5 — L10 — — P13_4 — MTIOC0D / GTIOC8B ESC_RESETOUT# — — — RZ/N2L Datasheet 1. Overview R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 32 of 127

1. Electrical Characteristics Electrical characteristics of this LSI is defined with the following conditions unless otherwise described. Conditions: VDD = 1.05 to 1.15 V VCC18 = VCC1833_n (1.8-V mode) = VCC18_PLL0 = VCC18_PLL1 = VCC18_USB = A VCC18_USB = VCC18_ADC0 = VCC18_ADC1 = A VCC18_TSU = VREFH0 = VREFH1= 1.70 to 1.95 V VCC33 = VCC1833_n (3.3-V mode) = VCC33_USB = 3.135 to 3.465 V VSS = VSS_USB = 0 V Tj = −40 to 125ºC

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings Parameter Symbol Value Unit Power supply voltage (3.3-V mode) VCC33, VCC1833_0, VCC1833_1, VCC1833_2, VCC1833_3, VCC1833_4 −0.3 to +3.8 V Power supply voltage (1.8-V mode) (VCC18) VCC1833_0 VCC1833_1, VCC1833_2, VCC1833_3, VCC1833_4 −0.3 to +2.5 V Power supply voltage VDD −0.3 to +1.5 V Input voltage Vin (3.3-V logic) −0.3 to VCC33 + 0.3 V Input voltage Vin (1.8-V logic) −0.3 to VCC18 + 0.3 V Analog power supply voltage VCC18_PLL0, VCC18_PLL1, VCC18_USB, AVCC18_USB, VCC18_ADC0, VCC18_ADC1, AVCC18_TSU*1 −0.3 to smaller value of VCC18*2 + 0.3 or 2.5 V VCC33_USB −0.3 to smaller value of VCC33 + 0.3 or 3.8 V Voltage difference between power supply pins VCC33-VCC18 -2.5 to + 2.1 V Analog input voltage VAN −0.3 to smaller value of VCC18_ADC0/1 + 0.3 or 2.5 V Reference voltage VREFH0, VREFH1 −0.3 to smaller value of VCC18_ADC0/1 + 0.3 or 2.5 V Crystal oscillator pins input voltage XTAL, EXTAL −0.3 to +1.5 V Operating temperature (Junction temperature) Tj −40 to +125 ºC Storage temperature Tstg −55 to +125 ºC Note 1. Connect Analog power supply pins to VCC18 when Analog block(s) are not used. Do not leave these pins open. Note 2. For convention, "VCC18" virtually represents any 1.8-V power supplies of the chip such as VCC1833_n in 1.8-V mode. Caution: Permanent damage to the LSI might result if absolute maximum ratings are exceeded. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 33 of 127

2.2 Power Supply

Table 2.2 Power supply Parameter Symbol Value Min. Typ. Max. Unit Power supply voltages VCC33 3.135 — 3.465 V VDD 1.05 1.1 1.15 V VSS — 0 — V Power supply voltages supporting multi voltage mode VCC1833_0, VCC1833_1, VCC1833_2, VCC1833_3, VCC1833_4 3.3-V mode 3.135 3.3 3.465 V 1.8-V mode (VCC18) 1.70 1.8 1.95 V Analog power supply voltages VCC18_PLL0 — VCC18 — V VCC18_PLL1 — VCC18 — V VCC33_USB — VCC33 — V VCC18_USB — VCC18 — V AVCC18_USB — VCC18 — V VCC18_ADC0 — VCC18 — V VCC18_ADC1 — VCC18 — V AVCC18_TSU — VCC18 — V VSS_USB — 0 — V

2.3 Power On/Off Sequence

Power on/off sequence and timing are shown in the figure and table below. VCC33) must be supplied. The power-up sequence must be completed within 100 ms. Reset signal (i.e. RES#) must be held to Low level during the power-up. A VCC). The power-down sequence must be completed within 100 ms. Rise and fall time of each power supply for the power-up and the power-down must be larger than 10 µs. Power supply voltages and reset signal must be applied with monotonic increase. Do not apply a negative voltage to power supply voltages. Stable clock must be supplied to EXTAL/XTAL or EXTCLKIN pin when reset signal (i.e. RES#) is driven high. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 34 of 127

1.1-V power supply 1.8-V power supply (1) Trisepwr (1) Trisepwr (2) Tdly18 (1) Trisepwr (3) Tdly33 3.3-V power supply (7) Tdly18d (8) Tdly11d OscillationXTAL / EXTAL RES# (5) Trisereset (4) Tdlyreset TRST# (9) Tdlytotal (10) Tdlytotald (6) Tdly33d (11) Tfallpwr (11) Tfallpwr (11) Tfallpwr 2.5 V Figure 2.1 Power on/off sequence Table 2.3 Power on/off sequence timing No. Symbol Description Value Min. Typ. Max. (1) Trisepwr Rising time of the power supply voltage 10 µs — 30 ms (2) Tdly18 Delay time from start of rising of the 1.1-V power supply voltage to completion of rising of the 1.8-V power supply voltage 0 — 100 ms (3) Tdly33 Delay time from completion of rising of the 1.8-V power supply voltage to completion of rising of the 3.3-V power supply voltage 0 — 100 ms (4) Tdlyreset Delay time from completion of rising of the 3.3-V power supply voltage to start of rising of RES# when XTAL/EXTAL is used. 10 ms — — Delay time from completion of rising of the 3.3-V power supply voltage to start of rising of RES# when EXTCLKIN is used. 1 ms — — (5) Trisereset Rising time of RES# — — 150 µs (6) Tdly33d Delay time from start of falling of RES# to start of falling of the 3.3-V power supply voltage 10 µs — — (7) Tdly18d Delay time from start of falling time of the 3.3-V power supply voltage to start of falling of the 1.8-V power supply voltage 0 — 100 ms (8) Tdly11d Delay time from start of falling of the 1.8-V power supply voltage to start of falling of the 1.1-V power supply voltage 0 — 100 ms (9) Tdlytotal Startup time of all power supply voltage — — 100 ms (10) Tdlytotald Shut down time of all power supply voltage — — 100 ms (11) Tfallpwr Falling time of the power supply voltage 10 µs — 30 ms RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 35 of 127

2.4 DC Characteristics

Table 2.4 DC Characteristics (3.3-V mode) Item Symbol Conditions Min. Typ. Max. Unit Input High-level voltage VIH33 3.3-V mode, Schmitt Trigger Control Disabled, Except P07_4 pin 2.0 — VCC33 + 0.3 V Input Low-level voltage VIL33 −0.3 — 0.8 V Positive trigger voltage VT33+ 3.3-V mode, Schmitt Trigger Control Enabled, Except P07_4 pin 0.9 — 2.1 V Negative trigger voltage VT33- 0.7 — 1.9 V Hysteresis voltage ΔVT33 0.2 — — V Input High-level voltage 2 VIH33_2 3.3-V mode, Schmitt Trigger Control Disabled, P07_4 pin ONLY VCC33 × 0.7 — VCC33 + 0.3 V Input Low-level voltage 2 VIL33_2 -0.3 — VCC33 × 0.3 V Positive trigger voltage 2 VT33+_2 3.3-V mode, Schmitt Trigger Control Enabled, P07_4 pin ONLY — — VCC33 × 0.72 V Negative trigger voltage 2 VT33-_2 VCC33 × 0.3 — — V Hysteresis voltage 2 ΔVT33_2 VCC33 × 0.1 — — V Output High-level voltage VOH33 Low, IOH = −2 mA VCC33 − 0.4 — — V VOH33 Middle, IOH = −4 mA VCC33 − 0.4 — — V VOH33 High, IOH = −8 mA VCC33 − 0.4 — — V VOH33 Ultra High, IOH = −12 mA VCC33 − 0.4 — — V Output Low-level voltage VOL33 Low, IOL = 2 mA — — 0.4 V VOL33 Middle, IOL = 4 mA — — 0.4 V VOL33 High, IOL = 8 mA — — 0.4 V VOL33 Ultra High, IOL = 12 mA — — 0.4 V Input leakage current |Iin| Vin = 0 V, Vin = VCC33 — — 10 µA Three-State leakage current (off state) |ITSI| Vin = 0 V, Vin = VCC33 — — 10 µA Input Pull-up resistors resistance Rpu Vin = 0 V 15 — 300 kΩ Input Pull-up resistors current Ipu Vin = 0 V -220 — -11 µA Input Pull-down resistors resistance Rpd Vin = VCC33 15 — 300 kΩ Input Pull-down resistors current Ipd Vin = VCC33 11 — 220 µA Input Capacitance Cin All input/output and input pins — — 10 pF Table 2.5 DC Characteristics (1.8-V mode) (1 of 2) Item Symbol Conditions Min. Typ. Max. Unit Input High-level voltage VIH18 1.8-V mode, Schmitt Trigger Control Disabled VCC18 × 0.65 — VCC18 + 0.3 V Input Low-level voltage VIL18 −0.3 — VCC18 × 0.35 V Positive trigger voltage VT18+ 1.8-V mode, Schmitt Trigger Control Enabled VCC18 × 0.4 — VCC18 × 0.7 V Negative trigger voltage VT18- VCC18 × 0.3 — VCC18 × 0.6 V Hysteresis voltage ΔVT18 VCC18 × 0.1 — — V Output High-level voltage VOH18 Low, IOH = −2 mA VCC18 − 0.45 — — V VOH18 Middle, IOH = −4 mA VCC18 − 0.45 — — V VOH18 High, IOH = −8 mA VCC18 − 0.45 — — V VOH18 Ultra High, IOH = −12 mA VCC18 − 0.45 — — V RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 36 of 127

Table 2.5 DC Characteristics (1.8-V mode) (2 of 2) Item Symbol Conditions Min. Typ. Max. Unit Output Low-level voltage VOL18 Low, IOL = 2 mA — — 0.45 V VOL18 Middle, IOL = 4 mA — — 0.45 V VOL18 High, IOL = 8 mA — — 0.45 V VOL18 Ultra High, IOL = 12 mA — — 0.45 V Input leakage current |Iin| Vin = 0 V, Vin = VCC18 — — 10 µA Three-State leakage current (off state) |ITSI| Vin = 0 V, Vin = VCC18 — — 10 µA Input Pull-up resistors resistance Rpu Vin = 0 V 15 — 300 kΩ Input Pull-up resistors current Ipu Vin = 0 V -120 — -6 µA Input Pull-down resistors resistance Rpd Vin = VCC18 15 — 300 kΩ Input Pull-down resistors current Ipd Vin = VCC18 6 — 120 µA Input Capacitance Cin All input/output and input pins — — 10 pF Table 2.6 USB2.0 USB_RREF Pin Item Symbol Conditions Min. Typ. Max. Unit Reference resistor*1 RREF — 1.8 (±1%) kΩ Note 1. The reference resistor connected to the USB_RREF pin is for external connection to this LSI. Table 2.7 USB2.0 Pull-Up/Pull-Down Resistors Item Symbol Conditions Min. Typ. Max. Unit USB_DP pull-up resistor (when the function controller is selected) RPU Idle 0.900 — 1.575 kΩ Transmission/reception 1.425 — 3.090 kΩ USB_DP/USB_DM pull-down resistors (when the host controller is selected) RPD — 14.25 — 24.80 kΩ Table 2.8 USB2.0 Host/Function-Related Pins (Low/Full Speed) Item Symbol Conditions Min. Typ. Max. Unit Input high level voltage VFSIH — 2.0 — — V Input low level voltage VFSIL — — — 0.8 V Differential input sensitivity VFSDI |(USB_DP) − (USB_DM)| 0.2 — — V Differential common mode range VFSCM — 0.8 — 2.5 V Output low level voltage VFSOL IFSOL = 2 mA 0.0 — 0.3 V Output high level voltage VFSOH IFSOH = −200 µA 2.8 — 3.6 V Output signal crossover voltage VFSCRS — 1.3 — 2.0 V Table 2.9 USB2.0 Host/Function-Related Pins (High Speed) (1 of 2) Item Symbol Conditions Min. Typ. Max. Unit Squelch detection threshold voltage (differential voltage) VHSSQ — 100 — 150 mV Disconnection detection threshold voltage (differential voltage) VHSDSC — 525 — 625 mV Common mode voltage range VHSCM — −50 — 500 mV Idle state VHSOI — −10.0 — 10.0 mV Output high level voltage VHSOH — 360 — 440 mV RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 37 of 127

Table 2.9 USB2.0 Host/Function-Related Pins (High Speed) (2 of 2) Item Symbol Conditions Min. Typ. Max. Unit Output low level voltage VHSOL — −10.0 — 10.0 mV Chirp J output voltage (differential) VCHIRPJ — 700 — 1100 mV Chirp K output voltage (differential) VCHIRPK — −900 — −500 mV Table 2.10 Supply Current Item Symbol Conditions Min. Typ. Max. Unit Normal operation Ivdd ICLK = 200 MHz, CPU0CLK = 400 MHz, Tj ≤ 110°C — — 310 mA IVCC33 *1 — 25 — mA IVCC1833_0 *1 — 9 — mA IVCC1833_1 *1 — 9 — mA IVCC1833_2 *1 — 9 — mA IVCC1833_3 *1 — 9 — mA IVCC1833_4 *1 — 9 — mA IVCC18_PLL0 — — — 6 mA IVCC18_PLL1 — — — 6 mA IVCC18_USB — — — 39 mA IVCC18_ADC0 — — — 3 mA IVCC18_ADC1 — — — 3 mA IVCC18_TSU — — 2 mA IVCC33_USB — — — 6 mA Low power consumption mode*2 Ivdd All modules inactive — 6 — mA IVCC33 — — 6 — mA IVCC1833_0 — — 2 — mA IVCC1833_1 — — 2 — mA IVCC1833_2 — — 2 — mA IVCC1833_3 — — 2 — mA IVCC1833_4 — — 2 — mA IVCC18_PLL0 — — 3.5 — mA IVCC18_PLL1 — — 0.1 — mA IVCC18_USB — — 0.5 — mA IVCC18_ADC0 — — 0.2 — mA IVCC18_ADC1 — — 0.2 — mA IVCC18_TSU — — 0.1 — mA IVCC33_USB — — 0.3 — mA Note: These values are reference values. The actual operating current greatly depends on the system (such as unsharpened waveforms due to I/O load and toggle frequency). Be sure to measure these current values in the system. Note 1. IO supply current (IVCC33, IVCC1833_n (n = 0 to 4)) should be 80 mA or less. (ΣIOH in Table 2.11) Note 2. All applicable modules are stopped or standby mode with the lowest clock frequency setting, no pull-up/down or operation for all I/O ports, and room temperature. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 38 of 127

Table 2.11 Permissible Output Currents Item Symbol Conditions Min. Typ. Max. Unit Permissible output low current (max. value per pin) IOL All output pins — — 12 mA Permissible output low current (total) ΣIOL Sum of all output pins — — 80 mA Permissible output high current (max. value per pin) IOH All output pins — — -12 mA Permissible output high current (total) ΣIOH Sum of all output pins — — -80 mA Note: All output current values shall be within the values in this table to ensure the reliability of this LSI. Table 2.12 Thermal Resistance value (Reference) Item Symbol Package Max. Unit Thermal Resistance Θja 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 30.1 °C/W 121 pin FBGA 10 × 10 mm, 0.8-mm pitch 30.5 °C/W Ψjt 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 0.42 °C/W 121 pin FBGA 10 × 10 mm, 0.8-mm pitch 0.42 °C/W Note: Package thermal resistance values above are based on EIA/JESD51-9 (2s2p) condition and reference only.

2.5 AC Characteristics

Table 2.13 Operating frequency Parameter Symbol Min. Max. Unit Operating frequency CPU clock (CPU0CLK) f 150 200 300 400 MHz System clock (ICLK) 150 200 Peripheral module clock H (PCLKH) 150 200 Peripheral module clock M (PCLKM) 75 100 Peripheral module clock L (PCLKL) 37.5 50 Peripheral module clock for ADC (PCLKADC) 18.75 25 Peripheral module clock for SCIn (PCLKSCIn, n = 0 to 5) 75 100 Peripheral module clock for SPIn (PCLKSPIn, n = 0 to 3) 75 100 External bus clock output (CKIO) 18.75 100 Ethernet PHY reference clock (ETHn_REFCLK, n = 0 to 2) 25 Ethernet PHY reference clock (RMIIn_REFCLK, n = 0 to 2) 50 AC Characteristics are defined in condition of the IO setting (DRCTLm register setting) show in Table 2.14. Table 2.14 IO setting (DRCTLm register setting) condition (1 of 2) Module Signal IO type Voltage DRCTLm register DRVn SRn SMTn Bus CKIO SDRAM and High drive — 3.3 V High Fast — Other than the above — 3.3 V Middle Fast — Other than the above Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable DMAC, MTU3, IIC, CANFD, DSMIF All signals Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 39 of 127

Table 2.14 IO setting (DRCTLm register setting) condition (2 of 2) Module Signal IO type Voltage DRCTLm register DRVn SRn SMTn GPT (n = 0 to 17) (m = 0, 1) GTIOCnA, GTIOCnB Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable GTADSMLm, GTADSMPm — 3.3 V Low Slow Disable SCI, SPI All signals — 3.3 V High Fast Disable xSPI XSPIn_CKP, XSPIn_CKN, XSPIn_IO[7:0], XSPIn_CSm#, XSPIn_DS — 1.8 V High Fast Disable — 3.3 V High Fast Enable Other than the above — — Low Slow Disable Ethernet Interface (n = 0 to 2) ETHn_TXCLK, ETHn_TXD[3:0] — 1.8 V/3.3 V High Fast Disable ETHn_TXER — 3.3 V Middle Fast — ETHn_RXCLK, ETHn_RXD[3:0] — 1.8 V/3.3 V — — Disable ETHn_RXER, ETHn_COL, ETHn_CRS — 3.3 V — — Disable ETHn_REFCLK, RMIIn_REFCLK — 3.3 V High Fast — Other than the above — — Low Slow Disable SHOSTIF HSPI_CK, HSPI_CS#, HSPI_IO[7:0] — 1.8 V/3.3 V High Fast Disable HSPI_INT# — 1.8 V/3.3 V Low Slow Disable PHOSTIF All signals Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable Debug Interface TRACECLK, TRACECTL, TRACEDATA[7:0], TDO, TMS — 3.3 V High Fast Disable Other than the above — — Low Slow Disable Other than the above — — Low Slow Disable

2.5.1 Clock Timing

2.5.1.1 CKIO Pin Output Timing

Table 2.15 CKIO pin output timing Parameter Symbol Conditions Min. Typ. Max. Unit CKIO pin output cycle time tCKcyc Figure 2.2 10 — 53.4 ns CKIO pin output high level pulse width tCKH tCKcyc / 2 − tCKr — — ns CKIO pin output low level pulse width tCKL tCKcyc / 2 − tCKf — — ns CKIO pin output rising time 1 tCKr CKIO: High drive output Setting — — 3.8 ns CKIO pin output falling time 1 tCKf — — 3.8 ns CKIO pin output rising time 2 tCKr CKIO: Normal output setting — — 9 ns CKIO pin output falling time 2 tCKf — — 9 ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 40 of 127

Figure 2.2 CKIO pin output timing

2.5.1.2 Ethernet PHY Reference Clock Output Timing

Conditions: C = 30 pF (ETHn_REFCLK) C = 20 pF (RMIIn_REFCLK) Table 2.16 Ethernet PHY reference clock output timing Parameter Symbol Conditions Min. Typ. Max. Unit ETHn_REFCLK cycle time tCK Figure 2.3 40 — — ns ETHn_REFCLK frequency — 25.00 ± 50 ppm MHz ETHn_REFCLK duty — 45 — 55 % ETHn_REFCLK rising/falling time tCKr / tCKf 0.5 — 4.0 ns RMIIn_REFCLK cycle time tCK 20 — — ns RMIIn_REFCLK frequency — 50.00 ± 50 ppm MHz RMIIn_REFCLK duty — 45 — 55 % RMIIn_REFCLK rising/falling time tCKr / tCKf 0.5 — 3.5 ns ETHn_REFCLK RMIIn_REFCLK output t CK 1/2 VCC1833_n t CKf t CKr V OH V OL 1/2 VCC1833_n V OL V OH Figure 2.3 Ethernet PHY reference clock output timing

2.5.1.3 EXTCLKIN External Clock Input

Table 2.17 EXTCLKIN clock timing Parameter Symbol Conditions Min. Typ. Max. Unit EXTCLKIN external clock frequency fEXTCLKIN — 25.00 ± 50 ppm MHz EtherCAT in use 25.00 ± 25 ppm MHz EXTCLKIN duty rEXTCLKIN — ±5% — EXTCLKIN rising time trEXTCLKIN — 0 — 5 ns EXTCLKIN falling time tfEXTCLKIN — 0 — 5 ns Note: When using crystal resonator (i.e. EXTA/XTAL clock is used), EXTCLKIN should be driven low. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 41 of 127

EXTCLKIN external clock input 1/2 × VCC33 1/2 × VCC33 f EXTCLKIN V IH33 V IH33 V IL33V IL33 f rEXTCLKIN f fEXTCLKIN Figure 2.4 EXTCLKIN external clock input timing

2.5.1.4 EXTAL/XTAL Clock Timing

Table 2.18 EXTAL/XTAL clock timing Parameter Symbol Conditions Min. Typ. Max. Unit EXTAL/XTAL clock frequency*1 fXTAL — 25.00 ± 50 ppm MHz EtherCAT in use 25.00 ± 25 ppm MHz Note: When using an external oscillator, be sure to leave XTAL open-circuit and make sure that EXTAL is driven low. Note 1. When using the EXTAL/XTAL clock (i.e. crystal resonator), ask the oscillator manufacturer to evaluate oscillation of the oscillator. For the oscillation stabilization time, see the evaluation result provided by the oscillator manufacturer. XTAL clock oscillator output 1/2 × VDD 1/2 × VDD f XTAL EXTAL clock oscillator input VSS VDD The swing voltage range of EXTAL/XTAL should be from VSS to VDD. Figure 2.5 EXTAL clock oscillator input and XTAL clock oscillator output timing

2.5.1.5 LOCO Clock Timing

Table 2.19 LOCO clock timing Parameter Symbol Conditions Min. Typ. Max. Unit LOCO clock cycle time tLcyc — 4.62 4.17 3.79 µs LOCO clock oscillation frequency tLOCO — 216 240 264 kHz LOCO clock oscillation stabilization wait time tLOCOWT — — — 40 µs LOCOCR.LCSTP Low-speed on-chip oscillator output LOCO clock t LOCOWT Figure 2.6 LOCO clock oscillation start timing RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 42 of 127

2.5.2 Reset, Interrtup, and Mode Timing

Table 2.20 Reset, interrupt, and mode timing Parameter Symbol Conditions Min.*1 Typ. Max. Unit RES# pulse width At power on tdlyreset Figure 2.7 10 — — ms Other than above tdlyreset2 1 — — ms RES# rising time trisereset — — 150 µs TRST# pulse width At power on tdlyreset 10 — — ms Other than above tdlyreset2 1 — — ms TRST# rising time trisereset — — 150 µs NMI pulse width tNMIW Figure 2.8 tIcyc × 2 — — ns IRQ pulse width tIRQW Figure 2.9 tIcyc × 2 — — ns Mode hold time (to RES#) At power on tMDH Figure 2.10 250 — — ns Note 1. tIcyc: ICLK cycle RES# TRST# t dlyreset , t dlyreset2 V IL33 V IL33 V IH33 t risereset Figure 2.7 Reset input timing NMI t NMIW Figure 2.8 NMI interrupt input timing IRQ0 to IRQ15 t IRQW Figure 2.9 IRQ interrupt input timing RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 43 of 127

RES# MD[2:0], MDV[4:0], MDD, MDW Valid Data 2.1 V Figure 2.10 Mode input timing

2.5.3 Bus Timing

Table 2.21 Bus timing (1 of 2) Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 15 pF (CKIO), 30 pF (others), Tjmin = -40℃ Parameter Symbol CKIO = 1/tCKcyc*1 (Max 66 MHz) Unit Reference FigureMin. Max. Address delay time 1 SDRAM*2 tAD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Address delay time 2 tAD2 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.18 Address setup time tAS 0 — ns Figure 2.11 to Figure 2.14, Figure 2.18 Chip enable setup time tCS 0 — ns Figure 2.11 to Figure 2.14, Figure 2.18 Address hold time tAH 0 — ns Figure 2.11 to Figure 2.14 BS delay time tBSD — 11 ns Figure 2.11 to Figure 2.32 CSn# delay time 1 SDRAM*2 tCSD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Read/write delay time 1 SDRAM*2 tRWD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Read strobe delay time tRSD 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.11 to Figure 2.18 Read data setup time 1*3 High-drive output tRDS1 1/2tCKcyc + 4 — ns Figure 2.11 to Figure 2.17 Normal output 1/2tCKcyc + 7 — ns Read data setup time 2*3 High-drive output tRDS2 6.6 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data setup time 3*3 High-drive output tRDS3 1/2tCKcyc + 4 — ns Figure 2.18 Normal output 1/2tCKcyc + 7 — ns Read data hold time 1 tRDH1 0 — ns Figure 2.11 to Figure 2.17 Read data hold time 2 tRDH2 2.5 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data hold time 3 tRDH3 0 — ns Figure 2.18 Write enable delay time 1 tWED1 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.11 to Figure 2.16 Write enable delay time 2 tWED2 — 11 ns Figure 2.17 Write data delay time 1 tWDD1 — 11 ns Figure 2.11 to Figure 2.17 RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 44 of 127

CS5#, CS3#, CS2#, CS0# RD/WR# t RSD RD# t RSD t RWD1 t CS D15 to D0 t RDS1 t RDH1 t AH t CSD1 t WED1 t AHt WED1 WE1#, WE0# t WDD1 t WDH1 t WDH4 D15 to D0 BS# t BSD t BSD Read Write Note 1. DACK is waveform when active-low is specified. Figure 2.11 SRAM interface basic bus cycle (no wait) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 47 of 127

CS5#, CS3#, CS2#, CS0# RD/WR# t RSD RD# t RSD t RWD1 t CS D15 to D0 t RDS1 t RDH1 t AH t CSD1 t WED1 t AHt WED1 WE1#, WE0# t WDD1 t WDH1 t WDH4 D15 to D0 BS# t BSD t BSD Read Write Tw t WTS t WTH WAIT# Note 1. DACK is waveform when active-low is specified. Figure 2.12 SRAM interface basic bus cycle (software wait 1) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 48 of 127

CS5#, CS3#, CS2#, CS0# RD/WR# t RSD RD# t RSD t RWD1 t CS D15 to D0 t RDS1 t RDH1 t AH t CSD1 t WED1 t AHt WED1 WE1#, WE0# t WDD1 t WDH1 t WDH4 D15 to D0 BS# t BSD t BSD Read Write Tw t WTS t WTH WAIT# t WTS t WTH TwX Note 1. DACK is waveform when active-low is specified. Figure 2.13 SRAM interface basic bus cycle (software wait 1, external wait 1 inserted) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 49 of 127

CS5#, CS3#, CS2#, CS0# RD/WR# t RSD RD# t RSD t RWD1 t CS D15 to D0 t RDS1 t RDH1 t AH t WED1 t AHt WED1 WE1#, WE0# t WDD1 t WDH1 t WDH4 D15 to D0 BS# t BSD t BSD Read Write Tw t WTS t WTH WAIT# Taw T1 T2Tw Taw t AD1 t AD1 t CSD1 t CSD1 t CSD1 t RWD1 t RWD1 t CS t AS t RSD t AHt RSD t RDS1 t RDH1 t WED1 t WED1 t AH t WDH1 t WDH4 t WDD1 t BSD t BSD t DACD t DACD t WTS t WTH Note 1. DACK is waveform when active-low is specified. Figure 2.14 SRAM interface basic bus cycle (software wait 1, external wait enabled (WM = 0), no idle cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 50 of 127

CS5# RD/WR# RD# D15 to D0 WE1#, WE0# D15 to D0 BS# Read Write WAIT# t WTH t WTH t WTS t WTS AH# DACK* Ta2 Ta3 T1 Tw TwX T2 t RWD1 t AHD t AHD t AHD t RDH1 t MAH t AVVH t RDS1 t WDH4 t MAD t AVVH t MAH t WDD1 t WDH1 Address Data DataAddress Note 1. DACK is waveform when active-low is specified. Figure 2.15 MPX-I/O interface bus cycle (address cycle 3, software wait 1, external wait 1 inserted) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 51 of 127

CS5#, CS3#, CS2#, CS0# WE1#, WE0# t RWD1 RD/WR# t WED1 D15 to D0 t RDS1 t CSD1 t RDH1 D15 to D0 t WDD1 t WDH1 BS# t BSD t BSD Read Write t WTS t WTH WAIT# t WTS t WTH TwX Tf t RWD1 RD# t RSD t RSD t RWD1 t RWD1 RD/WR# Note 1. DACK is waveform when active-low is specified. Figure 2.16 SRAM bus cycle with byte selection (SW = 1 cycle, HW = 1 cycle, asynchronous external wait 1 inserted, BAS = 0 (write cycle UB/LB control)) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 52 of 127

DACK* Th T2 A25 to A0 t AD1 t AD1 t CSD1 CS5#, CS3#, CS2#, CS0# WE1#, WE0# RD/WR# D15 to D0 t RDS1 t CSD1 t RDH1 D15 to D0 t WDD1 t WDH1 BS# t BSD t BSD Read Write t WTS t WTH WAIT# t WTS t WTH TwX Tf t RWD1 RD# t RSD t RSD t RWD1 t RWD1 RD/WR# t RWD1 t WED2 t WED2 Note 1. DACK is waveform when active-low is specified. Figure 2.17 SRAM bus cycle with byte selection (SW = 1 cycle, HW = 1 cycle, asynchronous external wait 1 inserted, BAS = 1 (write cycle WE control)) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 53 of 127

CS4#, CS0# RD/WR# t CS RD# WE1#, WE0# t CSD1 DACK WAIT# Tw t WTS t WTH t WTS t WTH TwX Twb t RWD1 D15 to D0 t RSD t RSD t BSD BS# T2B t AD2t AD2 t AS t RDH3 t RDS3t RDS3 t RDH3 t BSD Note 1. DACK is waveform when active-low is specified. Figure 2.18 Burst ROM read cycle (software wait 1, asynchronous external wait 1 inserted, burst wait 1, 2) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 54 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tcw Tde t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READA command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.19 Synchronous DRAM single-read bus cycle (with auto precharge, CAS latency 2, WTRCD = 0 cycles, WTRP = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 55 of 127

A12/A11* RD/WR# t CSD1 DACK Trw Tc1 Td1 t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READA command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tde Tap Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.20 Synchronous DRAM single-read bus cycle (with auto precharge, CAS latency 2, WTRCD = 1 cycle, WTRP = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 56 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 Tde t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READ command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tc3 Td4Td1 Td2 Td3 (1 to 4) t AD1 t AD1 t AD1 t AD1 READA command t RDH2t RDS2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.21 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (with auto precharge, CAS latency 2, WTRCD = 0 cycles, WTRP = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 57 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 Tde t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READ command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tc3 Td4Td1 Td2 Td3 (1 to 4) t AD1 t AD1 t AD1 t AD1 READA command t RDH2t RDS2 Trw Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.22 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (with auto precharge, CAS latency 2, WTRCD = 1 cycle, WTRP = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 58 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Trwl D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 WRITA command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t WDH2t WDD2 (High) CKE t RWD1 t RWD1 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.23 Synchronous DRAM single-write bus cycle (with auto precharge, TRWL = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 59 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Trwl D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 WRITA command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t WDH2t WDD2 (High) CKE t RWD1 t RWD1 Trw Trw Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.24 Synchronous DRAM single-write bus cycle (with auto precharge, WTRCD = 2 cycles, TRWL = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 60 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 WRIT command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 (High) CKE Tc3 Trwl t AD1 t AD1 t AD1 t AD1 WRITA command t WDH2t WDD2 t RWD1 t WDH2t WDD2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.25 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (with auto precharge, WTRCD = 0 cycles, TRWL = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 61 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 WRIT command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 (High) CKE Tc3 Trwl t AD1 t AD1 t AD1 t AD1 WRITA command t WDH2t WDD2 t RWD1 t WDH2t WDD2 Trw Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.26 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (with auto precharge, WTRCD = 1 cycle, TRWL = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 62 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 Tde t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READ command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tc3 Td4Td1 Td2 Td3 t AD1 t AD1 t AD1 t RDH2t RDS2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.27 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (bank active mode: ACT + READ command, CAS latency 2, WTRCD = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 63 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 Tde t RWD1 D15 to D0 t BSD BS# t BSD Column address t AD1 t AD1 t AD1 READ command CS3#, CS2# RAS# t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tc3 Td4Td1 Td2 Td3 t AD1 t AD1 t AD1 t RDH2t RDS2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.28 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (bank active mode: READ command, same row address, CAS latency 2, WTRCD = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 64 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 Tde t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 t AD1 READ command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 t RDH2t RDS2 (High) CKE Tc3 Td4Td1 Td2 Td3 t AD1 t AD1 t AD1 t RDH2t RDS2 TrwTp t AD1 t RWD1 t RASD1 t RASD1 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.29 Synchronous DRAM burst-read bus Cycle (read for 4 cycles) (bank active mode: PRE + ACT + READ command, different row address, CAS latency 2, WTRCD = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 65 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 WRIT command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 (High) CKE Tc3 t AD1 t AD1 t AD1 t AD1 t WDH2t WDD2 t RWD1 t WDH2t WDD2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.30 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (bank active mode: ACT + WRITE command, WTRCD = 0 cycles, TRWL = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 66 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 t RWD1 D15 to D0 t BSD BS# t BSD Column address t AD1 t AD1 t AD1 WRIT command CS3#, CS2# RAS# t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 (High) CKE Tc3 t AD1 t AD1 t AD1 t AD1 t WDH2t WDD2 t RWD1 t WDH2t WDD2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.31 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (bank active mode: WRITE command, same row address, WTRCD = 0 cycles, TRWL = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 67 of 127

A12/A11* RD/WR# t CSD1 DACK Tc1 Tc2 t RWD1 D15 to D0 t BSD BS# t BSD Row address Column address t AD1 t AD1 t AD1 WRIT command CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL t DQMD1 t DQMD1 (High) CKE Tc3 t AD1 t AD1 t AD1 t AD1 t WDH2t WDD2 t RWD1 t WDH2t WDD2 t RASD1 t RASD1 t RWD1 t AD1 TpwTp Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.32 Synchronous DRAM burst-write bus cycle (write for 4 cycles) (bank active mode: PRE + ACT + WRITE command, different row address, WTRCD = 0 cycles, TRWL = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 68 of 127

A12/A11* RD/WR# t CSD1 DACK Tpw Trr t RWD1 D15 to D0 BS# t AD1 t AD1 CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL (High) CKE Trc Trc t AD1 t RWD1 t CSD1t CSD1 t RASD1 t RASD1 (Hi-Z) Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.33 Synchronous DRAM auto-refresh timing (WTRP = 1 cycle, WTRC = 3 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 69 of 127

A12/A11* RD/WR# t CSD1 DACK Tpw Trr t RWD1 D15 to D0 BS# t AD1 t AD1 CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL CKE Trc Trc t AD1 t RWD1 t CSD1t CSD1 t RASD1 t RASD1 (Hi-Z) t CKED1 t CKED1 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.34 Synchronous DRAM self-refresh timing (WTRP = 1 cycle) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 70 of 127

A12/A11* RD/WR# t CSD1 DACK Tpw Trr t RWD1 D15 to D0 BS# t AD1 CS3#, CS2# RAS# t RASD1 t RASD1 t CASD1 CAS# t CASD1 DQMLU, DQMLL CKE Trc Trc t RWD1 t CSD1t CSD1 t RASD1 t RASD1 (Hi-Z) Trc TmwTrc Tde PALL REF REF MRS t AD1 t AD1t AD1 t CSD1 t CSD1 t CSD1 t CSD1 t RWD1 t RWD1 t RASD1 t RASD1 t RASD1 t RASD1 t CASD1 t CASD1 t CASD1 t CASD1 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.35 Synchronous DRAM mode register set timing (WTRP = 1 cycle)

2.5.4 DMAC Timing

Table 2.23 DMAC timing Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 15 pF (CKIO), 30 pF (others), Tjmin = -40℃ Parameter Symbol Min.*1 Max. Unit Reference figure DMAC DREQ pulse width tDRQW tPLcyc × 2 — ns Figure 2.36 DACK and TEND delay time tDACD 0 10 ns Figure 2.37 Note 1. tPLcyc: PCLKL cycle RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 71 of 127

Table 2.24 DMAC timing Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 12 pF (CKIO), 12 pF (others), Tjmin = -20℃ Parameter Symbol Min.*1 Max. Unit Reference figure DMAC DREQ pulse width tDRQW tPLcyc × 2 — ns Figure 2.36 DACK and TEND delay time tDACD -0.5 8 ns Figure 2.37 Note 1. tPLcyc: PCLKL cycle DREQ t DRQW Figure 2.36 DREQ input timing CKIO t DACD t DACD DACK TEND Figure 2.37 DACK and TEND output timing

2.5.5 On-Chip Peripheral Module Timing

2.5.5.1 I/O Port Timing

Table 2.25 I/O port timing Parameter Symbol Min. Max. Unit*1 Reference figure I/O port Input data pulse width tPRW 1.5 — tPLcyc Figure 2.38 Note 1. tPLcyc: PCLKL cycle PCLKL t PRW Port Figure 2.38 I/O port input timing

2.5.5.2 CMTW Timing

Table 2.26 CMTW timing Parameter Symbol Min. Max. Unit*1 Reference figure CMTW Input capture input pulse width Single-edge setting tCMTWICW 1.5 — tPLcyc Figure 2.39 Both-edge setting 2.5 — Note 1. tPLcyc: PCLKL cycle RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 72 of 127

Figure 2.39 CMTW input capture input timing

2.5.5.3 MTU3 Timing

Table 2.27 MTU3 timing Parameter Symbol Min. Max. Unit*1 Reference figure MTU3 Input capture input pulse width Single-edge setting tMTICW 2.5 — tPHcyc Figure 2.40 Both-edge setting 3.5 — Timer clock pulse width Single-edge setting tMTCKWH, tMTCKWL 2.5 — tPHcyc Figure 2.41 Both-edge setting 3.5 — Phase counting mode 3.5 — Note 1. tPHcyc: PCLKH cycle PCLKH t MTICW Input capture input Figure 2.40 MTU3 input capture input timing PCLKH t MTCKWH MTCLKA to MTCLKD t MTCKWL Figure 2.41 MTU3 clock input timing RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 73 of 127

2.5.5.4 POE3 Timing

Table 2.28 POE3 timing Parameter Symbol Min. Max. Unit*1 Reference figure POE3 POEn# input pulse width tPOEW 2.5 — tPHcyc Figure 2.42 Output disable time Transition of the POEn# signal level tPOEDI — 5 × PCLKH + 0.1 µs Figure 2.43 Simultaneous conduction of output pins tPOEDO — 3 × PCLKH + 0.1 µs Figure 2.44 Register setting tPOEDS — PCLKH + 0.1 µs Figure 2.45 Oscillation stop detection tPOEDOS — 74 µs Figure 2.46 Note 1. tPHcyc: PCLKH cycle PCLKH t POEW POEn# input Figure 2.42 POEn# input pulse timing POEn# input MTU PWM output pins t POEW t POEDI Output disabled Figure 2.43 Output disable time for POE in response to transition of the POEn# signal level MTU PWM output pins Simultaneous active-level outputs detected* Outputs disabled t POEDO Note 1. When the active level is set to low. Figure 2.44 Output disable time for POE in response to the simultaneous conduction of output pins RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 74 of 127

Figure 2.45 Output disable time for POE in response to the register setting MTU PWM output pins Oscillation stop detection signal (internal signal) Main clock Outputs disabled t POEDOS Figure 2.46 Output disable time for POE in response to the oscillation stop detection

2.5.5.5 GPT Timing

Table 2.29 GPT timing Parameter Symbol Min. Max. Unit*1 Reference figure GPT Input capture input pulse width Single-edge setting tGTICW 2.5 — tPHcyc Figure 2.47 Both-edge setting 3.5 — External trigger input pulse width Single-edge setting tGTEW 2.5 — tPHcyc Figure 2.48 Both-edge setting 3.5 — Note 1. tPHcyc: PCLKH cycle (LLPP channels), PCLKM cycle (Other channels) PCLKH, PCLKM t GTICW Input capture input Figure 2.47 GPT input capture input timing PCLKH t GTEW External trigger Figure 2.48 GPT external trigger input timing RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 75 of 127

2.5.5.6 POEG Timing

Table 2.30 POEG timing Parameter Symbol Min. Max. Unit*1 Reference figure POEG GTETRGn input pulse width (n = A to D) tPOEGW 2.5 — tPHcyc Figure 2.49 Output disable time Input level detection of the GTETRGn pin (via flag) tPOEGDI — 3 × PCLKH + 0.1 µs Figure 2.50 Detection of the output stopping signal from GPT (dead time error, simultaneous high output, or simultaneous low output) tPOEGDO — 0.1 µs Figure 2.51 Register setting tPOEGDS — PCLKH + 0.1 µs Figure 2.52 Oscillation stop detection tPOEGDOS — 74 µs Figure 2.53 Note 1. tPHcyc: PCLKH cycle (LLPP channels), PCLKL cycle (Other channels) PCLKL, PCLKH GTETRGn input (n = A to D) t POEGW Figure 2.49 POEG input timing Outputs disabled GPT PWM output pins POEGGn.PIDF flag (n = A to D) GTETRGn input (n = A to D) t POEGW t POEGDI Figure 2.50 Output disable time for POEG via detection flag in response to the input level detection of the GTETRGn pin Output stopping signal from GPT* GPT PWM output pins Outputs disabled t POEGDO (simultaneous high output flag) Figure 2.51 Output disable time for POEG in response to detection of the output stopping signal from GPT RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 76 of 127

POEGmGn.SSF bit (m = 0 to 2, n = A to D) GPT PWM output pins Outputs disabled t POEGDS Figure 2.52 Output disable time for POEG in response to the register setting GPT PWM output pins Oscillation stop detection signal (internal signal) Main clock Outputs disabled t POEGDOS Figure 2.53 Output disable time for POEG in response to the oscillation stop detection

2.5.5.7 A/D Converter Trigger Timing

Table 2.31 A/D converter trigger timing Parameter Symbol Min. Max. Unit*1 Reference figure A/D converter A/D converter trigger input pulse width ADTRG0#, ADTRG1# tTRGW 1.5 — tPADCcyc Figure 2.54 Note 1. tPADCcyc: PCLKADC cycle PCLKADC t TRGW ADTRG0# ADTRG1# Figure 2.54 A/D converter trigger input timing (ADTRG0#, ADTRG1#)

2.5.5.8 SCI Timing

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (except Simple I2C) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 77 of 127

Table 2.32 SCI timing (1 of 2) Parameter Symbol Min. Max. Unit Reference figure SCI (Asynchronous) Input clock cycle tScyc 4 — tPSCIcyc Figure 2.55 Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 3 ns Input clock fall time tSCKf — 3 ns Output clock cycle tScyc 6 — tPSCIcyc Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr — 3 ns Output clock fall time tSCKf — 3 ns SCI (Simple I2C, Standard mode) SDA input rise time tSr — 1000 ns Figure 2.56 SDA input fall time tSf — 300 ns SCL, SDA input spike pulse removal time tSP 0 2 × NFcyc*1 ns Data input setup time tSDAS 250 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF SCI (Simple I2C, Fast mode) SDA input rise time tSr — 300 ns Figure 2.56 SDA input fall time tSf — 300 ns SCL, SDA input spike pulse removal time tSP 0 2 × NFcyc*1 ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 78 of 127

CPOL = 0 input SCKn CPOL = 1 input MISOn output MOSIn input t LEAD t LAG MSB IN DATA LSB IN MSB IN MSB OUT (Last data) DATALSB OUT LSB OUT MSB OUT t OD t REL t OHt SA t Dr, t Dft SU t H t SSRt SSF Figure 2.62 SCI simple SPI mode timing for slave when CPHA = 1

2.5.5.9 IIC Timing

Conditions: VOL = 0.4 V , IOL = 4 mA RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 82 of 127

Table 2.33 IIC timing Parameter Symbol Min.*1 *2 Max.*1 *2 Unit Reference figure IIC (Standard-mode) SCL input cycle time tSCL 6(12) × tIICcyc + 1300 — ns Figure 2.63 SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rising time tsr — 1000 ns SCL, SDA input falling time tsf — 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 1000 — ns Stop condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF IIC (Fast-mode) SCL input cycle time tSCL 6(12) × tIICcyc + 600 — ns SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rising time tsr —*4 300 ns SCL, SDA input falling time tsf —*4 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load*3 Cb — 400 pF Note 1. tIICcyc: IIC internal reference clock (PCLKL) cycle Note 2. The value out of parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 00b while the digital filter is enabled by setting ICFER.NFE = 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by setting ICFER.NFE = 1. Note 3. Cb is the total capacitance of the bus lines. Note 4. The minimum values are not specified for tsr and tsf in Fast-mode. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 83 of 127

IIC_SCLn (n = 0 to 2) IIC_SDAn (n = 0 to 2) t STOS Test Conditions V IH = VCC33 × 0.7, V IL = VCC33 × 0.3, V OL = 0.4 V (I OL = 4 mA) t SP P Sr S P t SDAS t STAS t SDAH t Srt Sf t SCLL t SCL t SCLH t STAH t BUF Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 2.63 IIC bus interface input/output timing

2.5.5.10 CANFD Timing

Table 2.34 CANFD timing Parameter Symbol CAN CANFD Unit Reference figureMin. Max. Min. Max. CANFD Internal delay time tnode — 100 — 50 ns Figure 2.64 Transmission rate — — 1 — 8 Mbps Note: Internal delay time (t node) = Internal transmission delay time (toutput) + Internal reception delay time (tinput) CAN controller Internal transmission delay time (t output ) Internal reception delay time (t input ) CANTX1, CANTX0 pins CANRX1, CANRX0 pins Figure 2.64 CAN interface condition RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 84 of 127

2.5.5.11 SPI Timing

Table 2.35 SPI timing (1 of 2) Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF Parameter Symbol Min.*1 Max.*1 Unit*1 Reference figure RSPCK clock cycle Master tSPcyc 2 4096 tSPIcyc Figure 2.65 Slave 2 4096 RSPCK clock high level pulse width Master tSPCKWH (tSPcyc − tSPCKr − tSPCKf) / 2 − 2.5 — ns Slave 1 — tSPIcyc RSPCK clock low level pulse width Master tSPCKWL (tSPcyc − tSPCKr − tSPCKf) / 2 − 2.5 — ns Slave 1 — tSPIcyc RSPCK clock rising/falling time Output tSPCKr, tSPCKf — 3 ns Input — 1 ns Data input setup time Master tSU 5 — ns Figure 2.66 to Figure 2.72Slave 3 — Data input hold time Master tH 3 — ns Slave 3 — SSL setup time Master tLEAD N × tSPcyc − 3*2 N × tSPcyc + 3*2 ns Figure 2.66 to Figure 2.69 Slave 4 — tSPIcyc SSL hold time Master tLAG N × tSPcyc − 3*3 N × tSPcyc + 3*3 ns Slave 4 — tSPIcyc Continuous transmission delay Master tTD tSPcyc + 2 × tSPIcyc 8 × tSPcyc + 2 × tSPIcyc ns Slave tSPcyc + 5 × tSPIcyc — TI-SSP SS input setup time tTISS 3 — ns Figure 2.70 to Figure 2.72 TI-SSP SS input hold time tTISH 3 — ns TI-SSP next access time tTIND M*4 — tSPIcyc TI-SSP Master SS output delay tTISSOD -3 3 ns TI-SSP Master OE delay 1 tTIMOED1 — 2 ns TI-SSP Master OE delay 2 tTIMOED2 — 2 ns TI-SSP Slave OE delay 1 tTISOED1 — 12 ns TI-SSP Slave OE delay 2 tTISOED2 — 8 ns Data output delay time Master tOD — 3 tSPIcyc Figure 2.66 to Figure 2.72 Slave — 12 ns Data output hold time Master tOH -3 — ns Slave 3 — MOSI, MISO rising/falling time Output tDr, tDf — 3 ns Input — 1 µs SSL rising/falling time Output tSSLr, tSSLf — 3 ns Figure 2.66, Figure 2.67Input — 1 µs RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 85 of 127

Table 2.36 xSPI timing Parameter Symbol 1.8 V 3.3 V Unit Reference figureMin. Max. Min. Max. Cycle time SDR tPERIOD 7.5 — 13.3 — ns Figure 2.73 DDR 10.0 — 13.3 — ns Clock output slew rate tSRck 0.75/0.56*2 — 0.56 — V/ns Clock Duty cycle distortion tCKDCD 0.0 tPERIOD × 0.05 0.0 tPERIOD × 0.05 ns Clock Minimum Pulse width tCKMPW tPERIOD × 0.45 — tPERIOD × 0.45 — ns Differential clock crossing voltage VOX(AC) 0.4 × VCC18 0.6 × VCC18 — — V DS Duty cycle distortion tDSDCD 0.0 tPERIOD × 0.04 0.0 tPERIOD × 0.04 ns DS Minimum Pulse width tDSMPW tPERIOD × 0.41 — tPERIOD × 0.41 — ns Data input/output slew rate tSR 0.75/0.56*2 — 0.56 — V/ns Data input setup time (to CK) SDR tSU 2.0 — 2.4 — ns Figure 2.74 Data input hold time (to CK) tH 1.0 — 1.0 — ns Data output delay time tOD — 1.0*3 — 1.4*3 ns Data output hold time tOH -1.0 — -2.3 — ns Data output buffer off time tBOFF -1.0 — -2.3 — ns Data input setup time (to DS) DDR*1 tSU -0.8 — -0.8 — ns Figure 2.75, Figure 2.76 Data input hold time (to DS) tH tPERIOD × 0.41 - 0.8 — tPERIOD × 0.41 - 0.8 — ns Data output setup time (to CK) tSUO 1.0 — 1.0 — ns Data output hold time (to CK) tHO 1.0 — 1.0 — ns CS Low to Clock High tCSLCKH 6.0/8.0*2 *4 — 8.0*4 — ns Figure 2.74 to Figure 2.76Clock Low to CS High tCKLCSH 6.0/8.0*2 — 8.0 — ns CS High time tCSTD 1 16 1 16 tPERIOD DS Low to CS High tDSLCSH 6.0/8.0*2 — 10.6 — ns Figure 2.77 CS High to DS Tri-State tCSHDST 0.0 tPERIOD 0.0 tPERIOD ns CS Low to DS Low tCSLDSL 0.0 — 0.0 — ns DS Tri-State to CS Low tDSTCSL 0.0 — 0.0 — ns Note 1. The DS shift setting (WRAPCFG.DSSFTCSx[4:0]) is 01000b for xSPI200. Note 2. Specification at 133 MHz / Specification at 100 MHz Note 3. These are values when the OEN assertion is extended in the Output Enable Asserting extension bit (COMCFG.OEASTEX = 1). Note 4. These are the values when the CS assertion is extended in the CS asserting extension bit (LIOCFGCSn.CSASTEX = 1). RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 90 of 127

XSPIn_CS0# XSPIn_CS1# tHO tCSLCKH tSU tHtBOFF (XSPIn_CPN) XSPIn_CKP XSPIn_IOm tCSTD tCKLCSH Data output DS input Data input DS input tSUOtHO tSU tH XSPIn_DS tSUO Figure 2.75 DDR transmit/receive timing (4S-4D-4D, 8D-8D-8D) XSPIn_CS0# XSPIn_CS1# tHO tCSLCKH tBOFF (XSPIn_CPN) XSPIn_CKP XSPIn_IOm tCSTD tCKLCSH Data output DS input Data output DS output tHO XSPIn_DS tSUOtSUO tHOtSUO tHOtSUO Figure 2.76 DDR transmit/receive timing (HyperRAM write) CS# CK DS t CSLCKH t DSLCSH t CSHDST t DSTCSLt CSLDSL Figure 2.77 DS to CS signal timing

2.5.5.13 Delta-Sigma Interface Timing

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 92 of 127

Table 2.37 ΔΣ interface timing Parameter Symbol Min. Max. Unit Reference figure DSMIF Clock cycle Master tDScyc 40 200 ns Figure 2.78 Slave 40 200 Clock high level Master tDSCKWH 16 — ns Slave 16 — Clock low level Master tDSCKWL 16 — ns Slave 16 — Setup time Master tSU 15 — ns Figure 2.79, Figure 2.80 Slave 10 — Hold time Master tH 0 — ns Slave 10 — MCLKn (n = 0 to 5) t DScyc t DSCKWH t DSCKWL Figure 2.78 Clock input/output timing MCLKn (input or output) t SU n = 0 to 5 MDATn (input) t H Figure 2.79 Reception timing (MCLKn rising synchronous) MCLKn (input or output) t SU MDATn (input) t H Figure 2.80 Reception timing (MCLKn falling synchronous)

2.5.5.14 Ethernet Interface Timing

Conditions: VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 15 pF (RGMII) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 93 of 127

VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 25 pF (RMII) VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (MII) Table 2.38 Ethernet interface timing Parameter Symbol Min. Max. Unit Reference figure Ethernet (RGMII) ETHn_TXCLK, ETHn_RXCLK cycle time duration 1 Gbps tRGMIIck 7.2 8.8 ns Figure 2.81

100 Mbps 36 44

10 Mbps 360 440

ETHn_TXCLK, ETHn_RXCLK frequency

1 Gbps — 125 − 50 ppm 125 + 50 ppm MHz

100 Mbps 25 − 50 ppm 25 + 50 ppm

10 Mbps 2.5 − 50 ppm 2.5 + 50 ppm ETHn_TXCLK, ETHn_RXCLK duty clcle

1 Gbps — 45 55 %

100 Mbps

10 Mbps

ETHn_TXCLK, ETHn_TXD0 to ETHn_TXD3, ETHn_TXEN (TX_CTL), ETHn_RXCLK, ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV (RX_CTL) rise/fall time tRGMIIr, tRGMIIf — 0.75 ns ETHn_TXD0 to ETHn_TXD3, ETHn_TXEN (TX_CTL) to ETHn_TXCLK output skew tRGMIIos −0.5 0.5 ns ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV (RX_CTL) setup time tRGMIIs 1 — ns ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV (RX_CTL) hold time tRGMIIh 1 — ns Ethernet (RMII) ETHn_RXCLK cycle time tRMIIck 20 — ns Figure 2.82 ETHn_RXCLK frequency Typ. 50 MHz — 50 − 50 ppm 50 + 50 ppm MHz ETHn_RXCLK duty — 35 65 % ETHn_RXCLK rise/fall time tRMIIckr, tRMIIckf 0.5 3.5 ns ETHn_TXD0, ETHn_TXD1, ETHn_TXEN output delay time tRMIId 2.5 12 ns ETHn_RXD0, ETHn_RXD1, ETHn_RXER, ETHn_RXDV (CRS_DV) setup time tRMIIs 4 — ns ETHn_RXD0, ETHn_RXD1, ETHn_RXER, ETHn_RXDV (CRS_DV) hold time tRMIIh 2 — ns ETHn_TXD0, ETHn_TXD1, ETHn_TXEN, ETHn_RXD0, ETHn_RXD1, ETHn_RXER, ETHn_RXDV (CRS_DV) rise/fall time tRMIIr, tRMIIf 0.5 4 ns Ethernet (MII) ETHn_TXCLK, ETHn_RXCLK cycle time 100 Mbps tMIIck 40 — ns Figure 2.83

10 Mbps 400 —

ETHn_TXCLK, ETHn_RXCLK frequency

100 Mbps — 25 − 50 ppm 25 + 50 ppm MHz

10 Mbps 2.5 − 50 ppm 2.5 + 50 ppm ETHn_TXD0 to ETHn_TXD3, ETHn_TXEN, ETHn_TXER output delay time tMIId 1 20 ns ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV, ETHn_RXER setup time tMIIs 10 — ns ETHn_RXD0 to ETHn_RXD3, ETHn_RXDV, ETHn_RXER hold time tMIIh 10 — ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 94 of 127

Table 2.39 Ethernet interface timing (MAC to MAC connection mode) Parameter Symbol Min. Max. Unit Reference figure Ethernet (RGMII) ETH2_TXCLK, ETH2_RXCLK cycle time tMRGMIIck 7.2 8.8 ns Figure 2.84 ETH2_TXCLK, ETH2_RXCLK frequency Typ. 125 MHz — 125 − 50 ppm 125 + 50 ppm MHz ETH2_TXCLK, ETH2_RXCLK duty clcle — 45 55 % ETH2_TXCLK, ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN (TX_CTL), ETH2_RXCLK, ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV (RX_CTL) rise/fall time tMRGMIIr, tMRGMIIf — 0.75 ns ETH2_TXD0 to ETHn_TXD3, ETHn_TXEN (TX_CTL) output skew tMRGMIIos — 0.6 ns ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN (TX_CTL) output setup time tMRGMIIso 1.1 — ns ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN (TX_CTL) output hold time tMRGMIIho 1.1 — ns ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV (RX_CTL) input setup time tMRGMIIsi -0.7 — ns ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV (RX_CTL) input hold time tMRGMIIhi 2.9 — ns Ethernet (MII) ETH2_REFCLK cycle time tMMIIck 40 — ns Figure 2.85 ETH2_REFCLK frequency Typ. 25 MHz — 25 − 50 ppm 25 + 50 ppm MHz ETH2_TXD0 to ETH2_TXD3, ETH2_TXEN, ETH2_TXER output delay time tMMIId 11 25 ns ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV, ETH2_RXER setup time tMMIIs 10 — ns ETH2_RXD0 to ETH2_RXD3, ETH2_RXDV, ETH2_RXER hold time tMMIIh 0 — ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 95 of 127

ETH2_REFCLK ETH2_TXDm ETH2_TXEN ETH2_TXER tMMIIs tMMIIh ETH2_RXDm ETH2_RXDV ETH2_RXER tMMIId Figure 2.85 MII transmission and reception timing (MAC to MAC connection mode) (m = 0 to 3)

2.5.5.15 Serial Management Interface Timing

Conditions: VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 30 pF (1.8 V) VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (3.3 V) Table 2.40 Serial management interface timing Parameter Symbol Min. Max. Unit Reference figure MDIO MDC output cycle time GMAC_MDC, ETHSW_MDC TMDCck 80 — ns Figure 2.86 ESC_MDC 400 — ns MDIO output delay time (for MDC fall)*1 TMDIOd — 20 ns MDIO input setup time (for MDC rise) TMDIOs 18 — ns MDIO input hold time (for MDC rise) GMAC_MDC, ETHSW_MDC TMDIOh 0 — ns ESC_MDC 10 — ns Note 1. The output timing from ETHSW is based on the rising edge of MDC, and the output delay can be set in the register. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 98 of 127

GMAC_MDC ETHSW_MDC ESC_MDC (Output) t MDIOs t MDIOh t MDIOd GMAC_MDIO ETHSW_MDIO ESC_MDIO (Input) GMAC_MDIO ETHSW_MDIO ESC_MDIO (Output) Figure 2.86 Serial management interface timing

2.5.5.16 SHOSTIF Timing

Conditions: VOH = VCC18 × 0.5, VOL = VCC18 × 0.5, C = 30 pF (1.8 V) VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF (3.3 V) Table 2.41 SHOSTIF timing Parameter Symbol Min. Max. Unit Reference figure SHOSTIF Clock cycle time tSHck 25 — ns Figure 2.87 Clock high time tCH 0.45 0.55 tSHck Clock low time tCL 0.45 0.55 tSHck Clock rise slew rate tCRT 0.1 — V/ns Clock fall slew rate tCFT 0.1 — V/ns CS# high time tCS 2 — tSHck Figure 2.88, Figure 2.89 CS# active setup time tCSS 15 — ns CS# active hold time tCSH 15 — ns Data input setup time tSU 3 — ns Data input hold time tHD 10.5 — ns Clock low to output valid tV — 15.5 ns Data output hold time tHO 6 — ns Data output disable time tDIS — 18 ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 99 of 127

HSPI_CK input t SHck t CH t CL t CFT 30% 70% t CRT 70% 30% Figure 2.87 SHOSTIF clock timing HSPI_CS# input SCPOL = 1 HSPI_CK input MSB INHSPI_IO[n:0] I/O SCPOL = 0 tCSS DATA LSB IN tSU tHD MSB OUT tV tHO DATA LSB OUT tDIS tCSH tCS Input phase Output phase Standard SPI mode: n = 0 for input and n = 1 for output Dual SPI mode: n = 1 Quad SPI mode: n = 3 Octal SPI mode: n = 7 Figure 2.88 SHOSTIF timing (SCPH = 0) MSB IN tCSS DATA LSB IN tSU tHD MSB OUT tV tHO DATA LSB OUT tDIS tCSH tCS HSPI_CS# input SCPOL = 1 HSPI_CK input HSPI_IO[n:0] I/O SCPOL = 0 Standard SPI mode: n = 0 for input and n = 1 for output Dual SPI mode: n = 1 Quad SPI mode: n = 3 Octal SPI mode: n = 7 Input phase Output phase Figure 2.89 SHOSTIF timing (SCPH = 1)

2.5.5.17 PHOSTIF Timing

Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 30 pF RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 100 of 127

(1) Synchronous SRAM Interface Mode Table 2.42 PHOSTIF timing (Synchronous SRAM interface mode) No. Parameter Symbol Min. Max. Unit Reference figure 1 HCKIO input cycle tHCKIO 20.0 ― ns Figure 2.90 to Figure 2.94 2 HCKIO High-level width tHBHIGH 0.5 × tHCKIO - 2.1 0.5 × tHCKIO + 2.1 ns 3 HCKIO Low-level width tHBLOW 0.5 × tHCKIO - 2.1 0.5 × tHCKIO + 2.1 ns

4 Address and HCS0#/HCS1# input setup

time (to HCKIO ↑) tSKHA 4.0 ― ns

5 Address and HCS0#/HCS1# input hold

time (to HCKIO ↑) tHKHA 1.0 ― ns

6 HWR0#/HWR1# input setup time (to

HCKIO ↑) tSKHWR 4.0 ― ns

7 HWR0#/HWR1# input hold time (to HCKIO

tHKHWR 1.0 ― ns 8 HWRSTB# input setup time (to HCKIO ↑) tSKHWRSTB 4.0 ― ns 9 HWRSTB# input hold time (to HCKIO ↑) tHKHWRSTB 1.0 ― ns 10 HRD# input setup time (to HCKIO ↑) tSKHRD 4.0 ― ns 11 HRD# input hold time (to HCKIO ↑) tHKHRD 1.0 ― ns 12 Data input setup time (to HCKIO ↑) tSKIHD 4.0 ― ns 13 Data input hold time (to HCKIO ↑) tHKIHD 1.0 ― ns

14 Data and HWAIT# output delay time (to

HRD# ↓) tDKHDHR 1.0 ― ns

15 Data and HWAIT# output hold time (to

HRD# ↑) tHKOHD ― 11.0 ns

16 Data and HWAIT# output delay time (to

HCS0#/HCS1# ↓) tDKHD 1.0 ― ns

17 Data and HWAIT# output hold time (to

HCS0#/HCS1# ↑) tHKWTCS ― 11.0 ns

18 HWAIT# output delay time (to HWRSTB#,

HWR0#/HWR1# ↓) tDKHWT 1.0 ― ns

19 HWAIT# output hold time (to HWRSTB#,

HWR0#/HWR1# ↑) tHKWTWR ― 11.0 ns 20 HWAIT# output delay time (to HCKIO ↑) tDKHWTV 2.0 11.0 ns 21 Data output delay time (to HCKIO ↑) tDKHDV 2.0 11.0 ns

22 Data and HWAIT# valid data output hold

time (to HRD# ↑) tHKHWTHR 1.0 ― ns

23 HWR0#/HWR1#, HWRSTB# recovery time

(High-level width) tWHWR 40.0 ― ns 24 HRD# recovery time (High-level width) tWHRD 40.0 ― ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 101 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) <4> <5> HA20 to HA0 (input) <6> <7> HWR0#, HWR1# (input) <9> HWRSTB# (input) <8> <8> <9> <23> <23> HRD# (input) <13> HD15 to HD0 (I/O) <12> <20> <18> HWAIT# (output) <16> <20> <20> <19> <17> Figure 2.90 PHOSTIF write timing (Synchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 102 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) <4> <5> HA20 to HA0 (input) <6> <7> HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) <17> HD15 to HD0 (I/O) <20> <14> HWAIT# (output) <16> <20> <22> <15> <17> <10> <11> <24> <24> <16> <14> <21> <22> <15> Figure 2.91 PHOSTIF read timing (Synchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 103 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) <4> <5> HA20 to HA4 (input) <6> <7> HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) HD15 to HD0 (I/O) <20> <14> HWAIT# (output) <16> <20> <22> <15> <17> <10> <11> <24> <24> <16> <14> <21> <4> <5> HA3 to HA0 (input) Off Page On Page Off Page On Page <21> <21> <20> <21> <22> <15> <17> Figure 2.92 PHOSTIF page read timing (Synchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 104 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) <4> <5> HA20 to HA0 (input) <6> <7> HWR0#, HWR1# (input) <9> HWRSTB# (input) <8> <8> <9> <23> <23> HRD# (input) <13> HD15 to HD0 (I/O) <12> <18> HWAIT# (output) <16> <19> <17> Figure 2.93 PHOSTIF write timing (PHOSTIF register write) (Synchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 105 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) <4> <5> HA20 to HA0 (input) <6> <7> HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) <17> HD15 to HD0 (I/O) <14> HWAIT# (output) <16> <15> <17> <10> <11> <24> <24> <16> <14> <21> <22> <15> Figure 2.94 PHOSTIF read timing (PHOSTIF register read) (Synchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 106 of 127

(2) Asynchronous SRAM Interface Mode Table 2.43 PHOSTIF timing (Asynchronous SRAM interface mode) No. Parameter Symbol Min. Max. Unit Reference figure

1 Address, HCS0#/HCS1# input setup time (to HWRSTB#, HWR0#/

HWR1# ↓) tADDWRS 0 ― ns Figure 2.95 to Figure 2.98 2 HWR0#/HWR1# and HWRSTB# recovery time (High-level width) tWRW 20.0 ― ns

3 Data input setup time (to HWRSTB#, HWR0#/HWR1# ↓) tWRS 0 ― ns

4 Data input hold time (to HWRSTB#, HWR0#/HWR1# ↑) tWRH 0 ― ns

5 HWAIT# output delay time (to HCS0#/HCS1# ↓) tCLZ 1.0 ― ns 6 HWAIT# output delay time (to HWRSTB#, HWR0#/HWR1# ↓) tWAITD 1.0 ― ns

7 HWAIT# valid data output delay time (for HWRSTB#, HWR0#/HWR1#

tWRWAITF ― 39.2 ns

8 HWAIT# valid data output hold time (for HWRSTB#, HWR0#/HWR1# ↑) tWAITVH 0 ― ns

9 HWAIT# output hold time (to HWR0#/HWR1#, HWRSTB# ↑) tWAITH ― 11.0 ns 10 HWAIT# output hold time (to HCS0#/HCS1# ↑) tCHZ ― 11.0 ns

11 Address and HCS0#/HCS1# input setup time (to HRD# ↓) tADDRDS 0 ― ns

12 Address input hold time in page access (to HRD# ↑) tADDRDH 0 ― ns

13 HRD# recovery time (High-level width) tRDW 20.0 ― ns 14 Data and HWAIT# output delay time (to HRD# ↓) tRDLZ 1.0 ― ns 15 HWAIT# valid data output delay time (to HRD# ↓) tRDWAITF ― 39.2 ns

16 Data fixing time (to HWAIT# ↑) tWAITR 0 ― ns

17 Data and HWAIT# valid data output hold time (to HRD# ↑) tDATAOH 1.0 ― ns 18 Data and HWAIT# output hold time (to HRD# ↑) tRDHZ ― 11.0 ns 19 Data and HWAIT# output delay time in on-page access (to addresses) tPAGEOND 18.0 29.2 ns

20 Data and HWAIT# output delay time in off-page access (to addresses)

(when not crossing a 16-byte boundary) tPAGEOFD 18.0 29.2 ns (when crossing a 16-byte boundary) tPAGEOFD 18.0 29.2 ns 21 HWAIT# valid data output delay time (to HCS0#/HCS1# ↓) tWAITVD ― 39.2 ns 22 Data fixing time (to addresses) tADDFIX 18.0 ― ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 107 of 127

<1> HCS0#, HCS1# (input) <1> HA20 to HA0 (input) <1> HWR0#, HWR1# (input) HWRSTB# (input) <2> <2> HRD# (input) <4> HD15 to HD0 (I/O) <3> <6> HWAIT# (output) <5> <7> <8> <9> <10> Figure 2.95 PHOSTIF write timing (Asynchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 108 of 127

<11> HCS0#, HCS1# (input) <11> HA20 to HA0 (input) HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) <10> HD15 to HD0 (I/O) <16> <14> HWAIT# (output) <5> <15> <17> <18> <10> <13> <13> <14> <17> <18> <21> Figure 2.96 PHOSTIF read timing (Asynchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 109 of 127

<11> HCS0#, HCS1# (input) <11> <12> HA20 to HA4 (input) HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) HD15 to HD0 (I/O) <20> HWAIT# (output) <17> <18> <10> <13> <13> <14> <20> <11> HA3 to HA0 (input) Off Page On Page Off Page On Page <19> <16> <19> <17> <18> <10> <14> <5> <15> <21> <16> <19> <19> Figure 2.97 PHOSTIF page read timing (Asynchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 110 of 127

<11> HCS0#, HCS1# (input) <11> HA20 to HA0 (input) HWR0#, HWR1# (input) HWRSTB# (input) HRD# (input) <10> HD15 to HD0 (I/O) <14> HWAIT# (output) <5> <18> <10> <13> <13> <14> <17> <18> <22> Figure 2.98 PHOSTIF register read timing (Asynchronous SRAM interface mode) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 111 of 127

(3) Synchronous Burst SRAM Type Transfer Mode Table 2.44 PHOSTIF timing (Synchronous Burst SRAM Type transfer mode) No. Parameter Symbol Min. Max. Unit Reference figure 1 HCKIO input cycle tHCKIO 20.0 ― ns Figure 2.99 to Figure 2.102 2 HCKIO High-level width tHBHIGH 0.5 × tHCKIO - 2.1 0.5 × tHCKIO + 2.1 ns 3 HCKIO Low-level width tHBLOW 0.5 × tHCKIO - 2.1 0.5 × tHCKIO + 2.1 ns 4 Address and HCS0#/HCS1# input setup time (to HCKIO ↑) tSKPHA 4.0 ― ns 5 Address and HCS0#/HCS1# input hold time (to HCKIO ↑) tHKPCS 1.0 ― ns 6 Address and HCS0#/HCS1# input setup time (to HCKIO ↓) tSKNHA 4.0 ― ns 7 Address and HCS0#/HCS1# input hold time (to HCKIO ↓) tHKNHA 1.0 ― ns 8 HWR0#/HWR1# input setup time (to HCKIO ↑) tSKPHWR 4.0 ― ns 9 HWR0#/HWR1# input hold time (to HCKIO ↑) tHKPHWR 1.0 ― ns 10 HWR0#/HWR1# input setup time (to HCKIO ↓) tSKNHWR 4.0 ― ns 11 HWR0#/HWR1# input hold time (to HCKIO ↓) tHKNHWR 1.0 ― ns 12 HBS#, HWRSTB# input setup time (to CKIO ↑) tSKPHBCY 4.0 ― ns 13 HBS#, HWRSTB# input hold time (to CKIO ↑) tHKPHBCY 1.0 ― ns 14 HBS#, HWRSTB# input setup time (to CKIO ↓) tSKNHBCY 4.0 ― ns 15 HBS#, HWRSTB# input hold time (to CKIO ↓) tHKNHBCY 1.0 ― ns 16 HRD# input setup time (to CKIO ↑) tSKPHRD 4.0 ― ns 17 HRD# input hold time (to CKIO ↑) tHKPHRD 1.0 ― ns 18 HRD# input setup time (to CKIO ↓) tSKNHRD 4.0 ― ns 19 HRD# input hold time (to CKIO ↓) tHKNHRD 1.0 ― ns 20 Data input setup time (to CKIO ↑) tSKPHD 4.0 ― ns 21 Data input hold time (to CKIO ↑) tHKPHD 1.0 ― ns 22 Data input setup time (to CKIO ↓) tSKNHD 4.0 ― ns 23 Data input hold time (to CKIO ↓) tHKNHD 1.0 ― ns 24 Data output delay time (to HRD# ↓) tDKNHRD 1.0 ― ns 25 Data output hold time (to HRD# ↑) tHKPHRD ― 11.0 ns 26 Data output delay time (to HCKIO ↑) tDKPHD 2.0 11.0 ns 27 Data output delay time (to HCKIO ↓) tDKNHD 2.0 11.0 ns 28 HWAIT# output delay time (to HCKIO ↑) tDKPHWT 2.0 11.0 ns 29 HWAIT# output delay time (to HCKIO ↓) tDKNHWT 2.0 11.0 ns 30 Data output hold time (to HCS0#/HCS1# ↑) tHKPHCS ― 11.0 ns 31 HWRSTB# recovery time (High-level width) tWHWR 40.0 ― ns 32 HRD# recovery time (High-level width) tWHRD 40.0 ― ns RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 112 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) HA20 to HA0 (input) <10> HWR0#, HWR1# (input) HWRSTB# (input) Write strobe <31> HRD# (input) HD15 to HD0 (I/O) HWAIT# (output) HBS# (input) <9> HWRSTB# (input) Write status <8> <6> <4> <6> <7> <5> <7> <11> <12> <14> <13> <15> <12> <14> <13> <15> <12> <14> <13> <15> <25> <28> <29> <20> <22> <21> <23> IN Figure 2.99 PHOSTIF write timing (Synchronous Burst SRAM Type transfer mode, Address/Data separation) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 113 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) HA20 to HA0 (input) HWR0#, HWR1# (input) HRD# (input) HD15 to HD0 (I/O) HWAIT# (output) HBS# (input) HWRSTB# (input) <6> <4> <6> <7> <5> <7> <12> <14> <13> <15> <25> <28> <29> <27> <26> <30> <25> <16> <18> <17> <19> <24> <32> OUT Figure 2.100 PHOSTIF read timing (Synchronous Burst SRAM Type transfer mode, Address/Data separation) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 114 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) HA20 to HA0 (input) <10> HWR0#, HWR1# (input) HWRSTB# (input) Write strobe HRD# (input) HD15 to HD0 (I/O) HWAIT# (output) HBS# (input) <9> HWRSTB# (input) Write status <8> <6> <4> <6> <7> <5> <7> <11> <12> <14> <13> <15> <12> <14> <13> <15> <12> <14> <13> <15> <25> <28> <29> <20> <22> <21> <23> <4> <6> <5> <7> IN IN Figure 2.101 PHOSTIF write timing (Synchronous Burst SRAM Type transfer mode, Address/Data multiplexing) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 115 of 127

HCKIO (input) <1> <2> <3> <4> <5> HCS0#, HCS1# (input) HA20 to HA0 (input) HWR0#, HWR1# (input) HRD# (input) HD15 to HD0 (I/O) HWAIT# (output) HBS# (input) HWRSTB# (input) <6> <4> <6> <7> <5> <7> <12> <14> <13> <15> <25> <28> <29> <27> <26> <30> <25> <16> <18> <17> <19> <24> OUT <4> <6> <5> <7> IN Figure 2.102 PHOSTIF read timing (Synchronous Burst SRAM Type transfer mode, Address/Data multiplexing) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 116 of 127

2.6 USB Characteristics

Table 2.45 On-chip USB low-speed (host only) characteristics Parameter Symbol Min. Typ. Max. Unit Reference figure Rising time tLR 75 — 300 ns Figure 2.103, Figure 2.104 Falling time tLF 75 — 300 ns Rising/falling time ratio tLR/tLF 80 — 125 % USB_DP, USB_DM 10% 90% 90% 10% t LR t LF Figure 2.103 USB_DP, USB_DM output timing (low-speed/host only) 50 pF to 150 pF Observation point 50 pF to 150 pF USB_DP USB_DM 15 kΩ 15 kΩ Figure 2.104 Measurement circuit (low-speed/host only) Table 2.46 On-chip USB full-speed characteristics Parameter Symbol Min. Typ. Max. Unit Reference figure Rising time tFR 4 — 20 ns Figure 2.105, Figure 2.106 Falling time tFF 4 — 20 ns Rising/falling time ratio tFR/tFF 90 — 111.11 % USB_DP, USB_DM 10% 90% 90% 10% t FR t FF Figure 2.105 USB_DP, USB_DM output timing (full speed) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 117 of 127

2.7 A/D Conversion Characteristics

Table 2.48 12-Bit A/D (unit 0) conversion characteristics Parameter Min. Typ. Max. Unit Reference figure Resolution 12 bits — Analog input capacitance — — 13 pF — Channel-dedicated sample-and- hold circuits in use (AN000 to AN002) Conversion time*1 Permissible signal source impedance Max. = 1.0 kΩ 1.52 — — µs — Offset error — — ±13 LSB — Full-scale error — — ±13 LSB — Quantization error — ±0.5 — LSB — Absolute accuracy — — ±14 LSB — DNL differential non-linearity error — — ±3 LSB — INL integral non-linearity error — — ±4 LSB — Holding characteristics of sample- and-hold circuits — — 2.67 µs — Dynamic range 0.15 — VREFH0 - 0.15 V — Channel-dedicated sample-and- hold circuits not in use (AN000 to AN007) Conversion time*1 Permissible signal source impedance Max. = 1.0 kΩ 0.84 — — µs — Offset error — — ±11 LSB — Full-scale error — — ±11 LSB — Quantization error — ±0.5 — LSB — Absolute accuracy — — ±12 LSB — DNL differential non-linearity error — — ±3 LSB — INL integral non-linearity error — — ±4 LSB — Note: The specified values in the table apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the specified ranges. Note 1. The conversion time is the total of the sampling time and the comparison time. Table 2.49 12-Bit A/D (unit 1) conversion characteristics Parameter Min. Typ. Max. Unit Reference figure Resolution 12 bits — Conversion time*1 Permissible signal source impedance Max = 1.0 kΩ 0.84 — — µs — Analog input capacitance — — 13 pF — Offset error — — ±11 LSB — Full-scale error — — ±11 LSB — Quantization error — ±0.5 — LSB — Absolute accuracy — — ±12 LSB — DNL differential non-linearity error — — ±3 LSB — INL integral non-linearity error — — ±4 LSB — Note: The specified values in the table apply when there is no access to the external bus during A/D conversion. If access proceeds during A/D conversion, values may not fall within the specified ranges. RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 119 of 127

Note 1. The conversion time is the total of the sampling time and the comparison time. Analog signal source Ro Co Cin Rs Cs DUT ADC (equiv. circuit) Ro, Co: Signal source impedance Cin: Internal parasitic capacitance (package, I/O, etc.) Rs, Cs: ADC equivalent circuit impedance (With sample-and-hold circuits: Rs = 1.5 kΩ and Cs = 4 pF. Without sample-and-hold circuits: Rs = 0.75 kΩ and Cs = 3 pF. (Typical)) Figure 2.109 A/D converter equivalent circuit and peripheral configuration diagram

2.8 Temperature Sensor Characteristics

Table 2.50 Temperature sensor characteristics Parameter Min. Typ. Max. Unit Test Conditions Relative accuracy — ±1 — °C *1 Temperature slope — 0.0625 — °C/LSB — Output code (at 25°C) — 1545 (decimal) — — TSUSAD register Note 1. 2-point calibration (Tj = 25℃ and Tj = 85℃) and 8 times averaging.

2.9 Debug Interface Timing

Condition: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5 Table 2.51 Debug interface timing (1 of 2) Parameter Symbol Min. Max. Unit Reference figure TCK cycle time With an ICE connected tTCKcyc 30*1 — ns Figure 2.110 For use in BSCAN 80 — TCK high pulse width tTCKH 0.4 0.6 tTCKcyc TCK low pulse width tTCKL 0.4 0.6 tTCKcyc TDI setup time tTDIS 5 — ns Figure 2.111 Output load: 30 pFTDI hold time tTDIH 5 — ns TMS/SWDIO setup time tTMSS 5 — ns TMS/SWDIO hold time tTMSH 5 — ns SWDIO delay time tSWDO — 15 ns TDO delay time With an ICE connected tTDOD — 15 ns For use in BSCAN — 22 RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 120 of 127

Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. RZ/N2L Datasheet Appendix 1. Package Dimensions R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 123 of 127

INDEX AREAEDAB AA1cccCCdddCACEGJLNRBDFHKMP1 3 5 7 9 11 13 152 4 6 8 10 12 14E1D1eφeeeCABφfffCn X φb aaaC4X 外形図 Outline drawingRenesasコード PLBG0225GB-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-001635 1/1 Figure 1.1 225 pin FBGA RZ/N2L Datasheet Appendix 1. Package Dimensions R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 124 of 127

外形図 Outline drawingRenesasコード PLBG0121GF-Aルネサスエレクトロニクス株式会社Renesas Electronics CorporationRDK-G-001***1/1 D A aaaCcccC AA1dddCE1 D1e φeeeCABφfffCn X φb B C Figure 1.2 121 pin FBGA RZ/N2L Datasheet Appendix 1. Package Dimensions R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 125 of 127

Revision 1.00 — June 10, 2022

• Initial release Revision 1.10 — July 29, 2022 2. Electrical Characteristics:
• Corrected Table 2.21 Bus timing [Conditions: V OH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 15 pF (CKIO), 30 pF (others), Tjmin = -40℃].
• Corrected Table 2.22 Bus timing [Conditions: V OH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 12 pF (CKIO), 12 pF (others), Tjmin = -20℃]. RZ/N2L Datasheet Revision Histrory R01DS0397EJ0110 Rev.1.10 Jul 29, 2022 Page 126 of 127

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