MR2A16A ETC

Document overview

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Technical content

Features

  • Single 3.3-V power supply  Commercial temperature range (0°C to 70°C) Symmetrical high-speed read and write with fast access time (25 ns)  Flexible data bus control — 8 bit or 16 bit access  Equal address and chip-enable access times  Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss  All inputs and outputs are transistor-transistor logic (TTL) compatible  Fully static operation  Full nonvolatile operation with 10 years minimum data retention

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Figure 1. Block Diagram Figure 2. MR2A16A in 44-Pin TSOP Type II Package Table 1. Pin Functions

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. Table 2. Operating Modes

  1. H = high, L = low, X = don’t care

Table 3. Absolute Maximum Ratings

  1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation

could affect device reliability.

  1. All voltages are referenced to V
  2. Power dissipation capability depends on package characteristics and use environment.

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Table 4. Operating Conditions

  1. After power up or if V DD falls below VWI, a waiting period of 1 µs must be observed.

Memory is designed to prevent writing for all input pin conditions if V DD falls below minimum VWI. Table 5. dc Characteristics Table 6. Power Supply Characteristics

20 I DDR TBD TBD mA

25 I DDR TBD TBD mA

35 I DDR TBD TBD mA

20 I DDW TBD TBD mA

25 I DDW TBD TBD mA

35 I DDW TBD TBD mA

20 I SB1 TBD TBD mA

25 I SB1 TBD TBD mA

35 I SB1 TBD TBD mA

Figure 3. Output Load for ac Test Table 7. Capacitance

  1. (f = 1.0 MHz, dV = 3.0 V, T A = 25°C, periodically sampled rather than 100% tested)

Table 8. ac Measurement Conditions

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Table 9. Read Cycle Timing (See Notes 1 and 2)

  1. W is high for read cycle.
  2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention

conditions must be minimized or eliminated during read and write cycles.

  1. Addresses valid before or at the same time E goes low.
  2. This parameter is sampled and not 100% tested.
  3. Transition is measured ±200 mV from steady-state voltage.

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Table 10. Write Cycle Timing 1 (W Controlled; See Notes 1, 2, 3, and 4)

  1. A write occurs during the overlap of E low and W low.
  2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention

conditions must be minimized or eliminated during read and write cycles.

  1. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
  2. After W , E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns.
  3. This parameter is sampled and not 100% tested.
  4. Transition is measured ±200 mV from steady-state voltage.
  5. At any given voltage or temperature, t
  6. All write cycle timings are referenced from the last valid address to the first transition address.

Figure 6. Write Cycle 1 (W Controlled)

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Table 11. Write Cycle Timing 2 (E Controlled; See Notes 1,2,3, and 4)

  1. A write occurs during the overlap of E low and W low.
  2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention

conditions must be minimized or eliminated during read and write cycles.

  1. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
  2. After W , E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns.
  3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state.
  4. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state.
  5. All write cycle timings are referenced from the last valid address to the first transition address.

Figure 7. Write Cycle 2 (E Controlled)

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Table 12. Write Cycle Timing 3 (LB /UB Controlled; See Notes 1, 2, 3, 4, and 5)

  1. A write occurs during the overlap of E low and W low.
  2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention

conditions must be minimized or eliminated during read and write cycles.

  1. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
  2. After W , E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns.
  3. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them.
  4. All write cycle timings are referenced from the last valid address to the first transition address.

Figure 8. Write Cycle 3 (LB /UB Controlled)

MR2A16A/D, Rev. 0.1

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Ordering Information

(Order by Full Part Number) MR 2 A 16 A TS 25 C Freescale MRAM Memory Prefix Density Code (2 = 4 Mb, 4 = 16 Mb) Memory Type (A = Asynch, S = Sync) Timing Set Package Type (TS = TSOP) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) Commercial Device Numbers — MR2A16ATS25C Operating Temperature Range (C = 0 ° C to 70° C) MR2A16ATS35C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSIONS DO NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58. ÉÉÉÉÉ É ÉÉÉ É ÉÉÉÉÉ BM0.2 C B A C 44 23 12 2 1.05 EE 10.29 18.54 42X 44X 0.1 C SEATING PLANE 22X 11.96

1.20 MAX

0.15 0.60 0.45 ROTATED 90 CLOCKWISE VIEW D

40 PLACES

SECTION E–E /C0095 0.21 AM0.2 C 0.8 10.03 3 18.28 0.95 11.56 0.8 0.30 0.12 0.05 /C0095 /C00955 0.40

MR2A16A/D, Rev. 0.1 Freescale Semiconductor 15 This page is intentionally blank

Rev. 0.1, 7/2004 How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P .O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. Ltd.

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