MK2049-36

MK2049-36 RENESAS

Document overview

• Manufacturer or author: mamiller
• PDF pages: 9

Technical content

Features

• Packaged in 20 pin SOIC
• Pb (lead) free package
• 3.3 V + 5% operation
• Meets the TR62411, ETS300 011, and GR-1244 sp ecification for MTIE, Pull-in/Hold-in Range, Phase T ransients, and Jitter Generation for Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock or 10 to

50 MHz

• Locks to 8 kHz + 100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1/x0.5 or x1/x2 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, and OC3 su bmultiples
• See also the MK2049-34 and MK2049-45 Block Diagram VCXO-BASED PLL (MASTER CLOCK GENERATOR) EXTERNAL PULLABLE CRYSTAL FREQUENCY MULTIPLYING PLL INPUT REFERENCE CLOCK (TYPICALLY 8KHZ) CLOCK OUTPUT CLOCK OUTPUT / 2

8 KHZ (REGENERATED)4

3.3 VOLT COMMUNICATIONS CLOCK PLL VCXO AND SYNTHESIZER

IDT® 3.3 VOLT COMMUNICATIONS CLOCK PLL 2 MK2049-36 REV G 051310 Pin Assignment 20 pin (300) mil SOIC Pin Descriptions FS1 FS0 RES VDD CAP2 FCAP VDD GND CAP1 VDD GND GND CLK ICLK CLK/2 FS3 8k FS2 Pin Number Pin Name Pin Type Pin Description 1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 3. Internal pull-up resistor. 2 X2 XO Crystal connection. Connect to a MHz crystal as shown in table on page 3. 3 X1 XI Crystal connection. Connect to a MHz crystal as shown in table on page 3. 4 VDD Power Power supply. Connect to +3.3 V. 5 FCAP - Filter capacitor. Connect a 1000 pF ceramic capacitor to ground. 6 VDD Power Power supply. Connect to +3.3 V.

7 GND Power Connect to ground

8 CLK Output Clock output determined by st atus of FS3:0 per tables on page 3. 9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of CLK. 10 8k Output Recovered 8 kHz clock output. 11 FS2 Input Frequency select 2. Determines CLK input/outputs per tables on page 3. Internal pull-up resistor. 12 FS3 Input Frequency select 3. Determines CLK input/outputs per tables on page 3. Internal pull-up resistor. 13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock. 14 GND Power Connect to ground. 15 VDD Power Power Supply. Connect to +3.3 V.

16 CAP1 Loop

Connect the loop filter ceramic capacitors and resistor between this pin and CAP2. 17 GND Power Connect to ground.

18 CAP2 Loop Connect the loop filter ceramic capacitors and resistor between this pin and

IDT® 3.3 VOLT COMMUNICATIONS CLOCK PLL 3 MK2049-36 REV G 051310 Output Decoding Table - External Mode (MHz) Output Decoding Table - Buffer Mode (MHz) 0 = connect directly to ground, 1 = connect directly to VDD or leave open. Crystal is connected to pins 2 and 3; clock input is applied to pin 13. Operating Modes The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock to generate various output clocks, there are important differences in their input and crystal requirements. External Mode The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable. Buffer Mode Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs. 19 RES - Connect a 10-200k Ω resistor to ground. Contact IDTfor recommended value for your application. 20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 3. Internal pull-up resistor. ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal Used (MHz) N 8 k H z 00001 . 5 4 43 . 0 8 88 k H z1 2 . 3 5 2 1 5 4 4 8 k H z 00012 . 0 4 84 . 0 9 68 k H z1 2 . 2 8 8 1 5 3 6 8 k H z 0010 2 2 . 3 6 8 4 4 . 7 3 6 8 k H z1 1 . 1 8 4 1 3 9 8 8 k H z 0011 1 7 . 1 8 4 3 4 . 3 6 8 8 k H z1 1 . 4 5 6 1 4 3 2 8 k H z 01007 7 . 7 6 1 5 5 . 5 2 8 k H z 1 9 . 4 4 2 4 3 0 8 k H z 0101 1 6 . 3 8 4 3 2 . 7 6 8 8 k H z1 6 . 3 8 4 2 0 4 8 8 k H z 0110 1 4 . 3 5 2 2 8 . 7 0 4 8 k H z1 4 . 3 5 2 1 7 9 4 8 k H z 0111T E S TT E S TT E S TT E S T T E S T 8 k H z 1000 1 8 . 5 2 8 3 7 . 0 5 6 8 k H z1 8 . 5 2 8 2 3 1 6 8 k H z 1001 1 2 . 3 5 2 2 4 . 7 0 4 8 k H z2 4 . 7 0 4 3 0 8 8 8 k H z 1010 7 . 6 8 1 5 . 3 68 k H z 1 5 . 3 6 1 9 2 0 8 k H z 1011T E S TT E S TT E S TT E S T 1 3 4 4 8 k H z 1100 1 2 . 2 8 8 2 4 . 5 7 6 8 k H z2 4 . 5 7 6 3 0 7 2 8 k H z 1101 1 6 . 3 8 4 3 2 . 7 6 8 8 k H z1 2 . 2 8 8 1 5 3 6 Pin Number Pin Name Pin Type Pin Description ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N 2 2 - 3 6 1110 I C L K / 2 I C L K N / A I C L K / 2 3 1 1 - 1 8 1111 2 * I C L K 4 * I C L K N / A I C L K3

still have the output clock remain frequency-locked. from the MK2049. Y ou may also refer to application note MAN05 for additional suggestions on layout of the crystal selection. given board layout, using the procedure found in application note MAN05 on the IDT web site. of additional external components is described in the following sections. Cutout in ground and power plane. Route all traces away from this area. Figure 2. Typical MK2049-34 Layout

IDT® 3.3 VOLT COMMUNICATIONS CLOCK PLL 5 MK2049-36 REV G 051310 Loop Filter Information on how to configure the external loop filter (connected between pins CAP1 and CAP2) can be found on our web site at www.idt.com/?app=calculators&source=support_menu. Crystal Operation The MK2049-36 operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the layout guidelines shown on the previous page should be closely followed. The frequency of oscillation of a quartz crystal is determined by its cut an d by the load capacitors connected to it. The MK2049 has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use short traces between the MK2049 and the crystal. For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of approved crystals, please refer to application note MAN05 on the IDT web site. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2049-36. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 175 ° C Soldering Temperature 250 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V

IDT® 3.3 VOLT COMMUNICATIONS CLOCK PLL 6 MK2049-36 REV G 051310 Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Note 1: For loop timing modes and buffer modes, see tables on page 3 for required input clock frequencies Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.3 3.45 V Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -8 mA 2.4 V Output Low Voltage V OL IOL = 8 mA 0.4 V Operating Supply Current I DD No Load, VDD=3.3 V 7 mA Short Circuit Current I OS Each Output ±50 mA Input Capacitance C IN FS3:0 5 pF Internal Pull-up Resistor R PU 350 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency External Mode, Note 1 ICLK 8k H z Input Clock Pulse Width t pi 10 ns Propagation Delay ICLK to 8 kHz 7 ns Delay, CLK/2 after CLK 1 ns Output Clock Rise Time t OR 0.8 to 2.0 V 2 ns Output Fall Time t OF 2.0 to 0.8 V 2 ns Output Clock Duty Cycle, High Time at VDD/2, except 8 kHz 40 60 % Actual mean frequency error versus target Any clock selection 0 0 ppm

IDT® 3.3 VOLT COMMUNICATIONS CLOCK PLL 7 MK2049-36 REV G 051310 Package Outline and Package Dimensions (20-pin SOIC, 300 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK2049-36SILF MK2049-36SILF Tubes 20-pin SOIC -40 to +85 ° C MK2049-36SILFTR MK2049-36SILF Tape and Reel 20-pin SOIC -40 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0 . 1 80 . 3 2. 0 0 7. 0 1 3 D 12.60 13.00 .496 .512 E 7 . 4 07 . 6 0. 2 9 1. 2 9 9 e 1.27 BASIC 0.050 BASIC H 10.00 10.65 .394 .419 h 0 . 2 50 . 7 5. 0 1 0. 0 2 9 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com MK2049-36

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.