MEJ02C2016_M5M5J167KT

MEJ02C2016_M5M5J167KT HITACHI

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs Outline: 52PTG-A N C : No Connection A0 ~ A18 DQ1 ~ DQ16 OE# BC1# Address input Data input / output Chip select input 1 Write control input Output enable input Lower By te (DQ1 ~ 8) Pin Function Vcc GND Power supply Ground supply BC2# Upper B y te (DQ9 ~ 16) A16 DQ1 GND OE# BYTE# DQ9 DQ2 DQ10 DQ3 NC GND DQ11 DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15 DQ8 DQ16/A-1 A18 A17 A11 A10 A15 A13 A12 A14 A19 VCC S1# BC1# NC NC NC NC BC2# 10.49mm 30mA (10MHz) 5mA (1MHz) Operating temperature Part name Power Supply Access time max. Stand-by c urrent Ratings (max.) Active (3.3V, Ty p.) Icc1 70ºC 25ºC * Ty pical 40ºC25ºC 40ºC 40 16 102.4 2.0 NC S1# Chip select input 2 A19 Address input M5M5J167KT -70HI 70ns The M5M5J167KT is a f amily of low v oltage 16Mbit static RAMs organized as 1048576-words b y 16-bit / 2097152-words b y 8-bit, f abricated b y Mitsubishi's high-per f ormance 0.18µm CMOS technolog y. The M5M5J167KT is suitable f or memor y applications where a simple inter f acing , batter y operating and batter y backup are the important design objecti v es. The M5M5J167KT is made b y stacked-micro-package technology and two chips o f 8Mbits SRAMs are assembled in one package. By using this package technolog y , small package size can be achiev ed f or highdensit y SRAM. The M5M5J167KT is packaged in a 52pin- µTSOP with the outline of 10.79mm x 10.49mm, and pin pitch o f 0.40mm. It gi v es the best solution f or a compaction o f m ounting area as well as f lexibilit y of wiring pattern o f printed circuit boards. The operating temperature range is -40 ~ +85°C

DESCRIPTION

• Single 2.7~3.6V power supply - Small stand-b y current: 0.2µA (2.0V, t y p.) - No clocks, No re f resh - Data retention suppl y v oltage =2.0~3.6V - All inputs and outputs are TTL compatible. - Easy memor y expansion b y S1#, S2, BC1# and BC2# - Common Data I/O - Three-state outputs: OR-tie capability - OE pre v ents data contention in the I/O bus - By te f unction (x8 mode) a v ailable by By te# & A-1. - Process technolog y: 0.18µm CMOS - Package: 52pin 10.79mm x 10.49mm µTSOP [0.4mm pin pitch]

FEATURES

• Typical parameter indicates the value for the center of distribution, and not 100% tested. current PIN CONFIGURATION 85ºC BYTE# By te (x8 mode) enable input

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs 2 2 FUNCTION The M5M5J167KT is organized as 1048576-words b y 16- bit / 2097152-words b y 8-bit. These de v ices operate on a single +2.7~3.6V power suppl y, and are directl y TTL compatible to both input and output. Its f ully static circuit needs no clocks and no re f resh, and makes it use f ul. The operation mode are determined b y a combination of the de v ice control inputs BC1# , BC2# , S1#, S2 , W#, OE# and BY TE#. Each mode is summarized in the f unction table. The address select A19 can select either one 8MSRAM chip or another 8MSRAM chip. A write operation is executed whene v er the low le v el W# ov erlaps with the low le v el BC1# and/or BC2# and the low lev el S1# and the high le v el S2. The address (A-1~A19 : By te mode, A0~A19 : Word mode) must be set up be f ore the write c yc le and must be stable during the entire c y cle. A read operation is executed b y s etting W# at a high lev el and OE# at a low le v el while BC1# and/or BC2# and S1#and S2 are in an acti v e state (S1#=L, S2=H). When setting BYTE# at a low le v el, the f unction will be in the x8 mede, which is, DQ1-8 are a v ailable and DQ9-16 are not a v ailable. In the x8 mode, A-1 is used as the additional address. During the acti v e f unction f or x8 mode, BC1# BC2# must be low le v el. When setting BC1# and BC2# at a high le v el or S1# at a high lev el or S2 at a low le v el, the chips are in a non- selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memor y expansion by BC1#, BC2# and S1#, S2. The power suppl y c urrent is reduced as low as 0.2µA (25°C, t y pical), and the memor y data can be held at +2.0V power suppl y, enabling batter y back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE Note1 : "H" and "L" in this table mean V IH and V IL, respecti v ely . Note2 : " X" in this table should be "H" or "L". S1# S2 BYTE# BC1# BC2# W# OE# Mode DQ1~8 DQ9~15 DQ16 Icc H H X X X X X Non selection High-Z High-Z High-Z Standby X L X X X X X Non selection High-Z High-Z High-Z Standby X X H H H X X Non selection High-Z High-Z High-Z Standby L H H L H L X Write Din High-Z High-Z Active L H H L H H L Read Dout High-Z High-Z Active L H H H L L X Write High-Z Din Din Active L H H H L H L Read High-Z Dout Dout Active L H H L L L X Write Din Din Din Active L H H L L H L Read Dout Dout Dout Active L H L L L L X Write Din High-Z A-1 Active L H L L L H L Read Dout High-Z A-1 Active

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs OE# A18 524288WORDS X

16 BITS

8 BITS

S1# BC2# BC1# A19 8MS(1) 8MS(2) BLOCK DIAGRAM x8/x16 Switching circuit BYTE#

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs pF VI=GND, V I=25mVrms, f =1MHz VO=GND,V O=25mVrms, f =1MHz CI CO DC ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC Vcc=2.7V ~3.6V,unless otherwise noted) Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested. CAPACITANCE (Ta=-40~+85ºC Vcc=2.7V ~3.6V,unless otherwise noted) Symbol Parameter Conditions Limits MaxTypMin Units Input capacitance Output capacitance Symbol Parameter Limits Conditions Units µA mA mA V Icc1 Icc2 Icc4 VIH VIL IO Icc3 VOH IOH= - 0.5mA VOL IOL= 2.0mA II VI =0 ~ Vcc BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc Vcc+0.2V 0.6 2.2 - 0.2 * 2.4 2.0 0.4 50 30 MaxTypMin f = 10MHz f = 1MHz f = 10MHz f = 1MHz 50 30 155 High-lev el input v oltage Input leakage current Activ e suppl y c urrent ( AC,MOS le v el ) ( AC,TTL le v el ) Activ e suppl y c urrent Stand b y s upply current ( AC,MOS le v el ) ( AC,TTL le v el ) Other inputs= 0 ~ Vcc Note 3: Direction for current flowing into IC is indicated as positive (no mark) BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V other inputs < 0.2V or > Vcc-0.2V Output - open (duty 100%) BC1# and BC2#=V IL , S1#=V IL ,S2=V IH other pins =V IH or VIL BC1# and BC2# =VIH or S1# =VIH or S2=VIL µA 40 ~ +70°C ~ +40°C 2.0 ~ +25°C - 2.4 (1)S1# > Vcc - 0.2V and S2 > Vcc - 0.2V, other inputs = 0 ~ Vcc S2 < 0.2V,(2) other inputs = 0 ~ Vcc BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V (3) other inputs = 0 ~ Vcc A19 > Vcc - 0.2V or < 0.2V A19 =VIH or VIL Low-lev el input v oltage High-level output voltage Low-lev el output v oltage Output leakage current Stand b y s upply current Output - open (duty 100%) ABSOLUTE MAXIMUM RATINGS Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature V mW Conditions Ta = 25°C 700 - 65 ~ +150 Ratings Vcc VI VO Pd Ta Tstg - 0.3 * ~ +4.6 0 ~ Vcc Symbol Parameter Units -40 ~ +85 With respect to GND With respect to GND With respect to GND * -3.0V in case o f AC (Pulse width 30ns) ºC ºC * -1.0V in case of AC (Pulse width 30ns) 80 ~ +85°C - - BYTE# > Vcc - 0.2V or < 0.2V, BYTE# > Vcc - 0.2V or < 0.2V, BYTE# > Vcc - 0.2V or < 0.2V, BYTE# > Vcc - 0.2V or < 0.2V,

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs AC ELECTRICAL CHARACTERISTICS (Ta=-40~+85ºC, Vcc=2.7V ~3.6V,unless otherwise noted) Input rise time and f all time Ref erence le v el Output loads 2.7~3.6V VIH=2.7V, V IL=0.2V Transition is measured ±200mV from steady state voltage.(for ten,tdis) 5ns Fig.1,CL=30pF CL=5pF (for ten,tdi s) (1) TEST CONDITIONS Supply v oltage Input pulse 1TTL CL DQ tCR ns ta(S1) ta(OE) tdis(S1) tdis(OE) ten(S1) ten(OE) tV(A) ta(A) ns ns ns ns ns ns ns ns ta(BC1) ta(BC2) tdis(BC1) tdis(BC2) ten(BC1) ten(BC2) ns ns ns ns ns ns ta(S2) ns70 ten(S2) 10 ns tdis(S2) ns25 70HI tsu(A-WH) tCW tw(W) tsu(A) tsu(S1) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ns ns ns ns ns ns ns ns ns ns ns ns ns ns tsu(BC1) tsu(BC2) tsu(S2) ns Symbol Parameter MaxMin Units (2) READ CYCLE (3) WRITE CYCLE MaxMin Limits UnitsSymbol Parameter VOH=VOL=1.5V 70HI Limits Fig.1 Output load Including scope and jig capacitance Read c y cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time a ft er S2 low Output disable time a ft er S1# high Output disable time a ft er BC1# high Output disable time a ft er BC2# high Output disable time a ft er OE# high Output enable time a f ter S1# low Output enable time a f ter S2 high Output enable time a f ter BC1# low Output enable time a f ter BC2# low Output enable time a f ter OE# low Data v alid time a fter address Write c y cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write reco v ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs BC1#, BC2# Read cycle ta(A) ta(BC1) tv (A) tdis (BC1) or tdis (BC2) ta (OE) ten (OE) tdis (OE) tCR ten (S1) W# = "H" le v el OE# (Note5) (Note5) (Note5) (Note5) VALID DATA ta(S1) tdis (S1) S1# (Note5) (Note5) ta(BC2)or ten (BC2) ten (BC1) ta(S2) tdis (S2) (Note5) (Note5) ten (S2) A0~19 (Word Mode) A-1~19 (Byte Mode) DQ1~16 (Word Mode) DQ1~8 (Byte Mode) (5) TIMING DIAGRAMS (4) Byte# function tsu (BYTE) trec (BYTE) ms Symbol Parameter Test conditions Limits Min Typ Max Units / BYTE set up time / BYTE reco v ery time 5 ms5 tsu (BYTE) trec (BYTE) BYTE# S1# BYTE#

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs Note 5: Hatching indicates the state is "don't care". Note 6: A Write occurs during S1# low, S2 high o v erlaps BC1# and/or BC2# low and W# low. Note 8: Don't appl y inv erted phase signal externall y when DQ pin is in output mode. Note 7: When the f alling edge o f W# is simultaneousl y or prior to the f alling edge o f BC1# and/or BC2# or the f alling edge o f S1# or rising edge o f S2, the outputs are maintained in the high impedance state. th (D)tsu (D) tsu (BC1) or tsu (BC2) trec (W)tsu (A) tCW Write cycle (BC# control mode) (Note5)(Note5) (Note6) (Note7) (Note5)(Note5) S1# BC1#, BC2# (Note5)(Note5) (Note5) (Note5) tsu (S2) ten (W) th (D)tsu (D) tsu (BC1) or tsu(BC2) ten(OE) tdis (OE) tw (W) trec (W)tsu (A) tdis (W) tCW OE# Write cycle( W# control mode ) (Note5) (Note5) tsu (A-WH) S1# (Note5) (Note5) tsu (S1) BC1#, BC2# DATA IN STABLE DATA IN STABLE A0~19 (Word Mode) A-1~19 (Byte Mode) A0~19 (Word Mode) A-1~19 (Byte Mode) DQ1~16 (Word Mode) DQ1~8 (Byte Mode) DQ1~16 (Word Mode) DQ1~8 (Byte Mode)

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs th (D)tsu (D) tsu (S1) trec (W)tsu (A) tCW S1# Write cycle (S1# control mode) (Note5)(Note5) (Note6) (Note 7) (Note5)(Note5) BC1#, BC2# (Note5)(Note5) th (D)tsu (D) tsu (S2) trec (W)tsu (A) tCW S1# Write cycle (S2 control mode) (Note5)(Note5) (Note6) (Note 7) (Note5)(Note5) BC1#, BC2# DATA IN STABLE DATA IN STABLE A0~19 (Word Mode) A-1~19 (Byte Mode) A0~19 (Word Mode) A-1~19 (Byte Mode) DQ1~16 (Word Mode) DQ1~8 (Byte Mode) DQ1~16 (Word Mode) DQ1~8 (Byte Mode) (Note5)(Note5)

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs tsu (PD) trec (PD) ns ms 2.2V tsu (PD) 2.7V 2.7V trec (PD) Vcc V2.0Vcc (PD) VI (S1#) Icc (PD) 2.0 BC1# POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC, Vcc=2.7V ~3.6V,unless otherwise noted) Symbol Parameter Test conditions Limits Min Typ Max Units Power down supply voltage Chip select input S1# Power down supply c urrent (2) TIMING REQUIREMENTS Symbol Parameter Test conditions Limits Units Power down set up time Power down reco v ery t ime (3) TIMING DIAGRAM note10: On the BC# control mode, the le v el of S1# and S2 must be f ixed at S1#, S2, A19 > Vcc-0.2V or S2 <0.2V VI (BC) Byte control input BC1# & BC2# V BC1# , BC2# > Vcc - 0.2V BC2# tsu (PD) 2.7V 2.7V trec (PD) Vcc S1# note11: On the S1# control mode, the le v el of S2 must be f ixed at S2 > Vcc-0.2V or S2 <0.2V S1# > Vcc - 0.2V VI (S2) 0.2 0.2V tsu (PD) 2.7V 2.7V trec (PD) Vcc S2 control mode µA (1) S1# > Vcc - 0.2V, BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc S2 < 0.2V , BYTE# > Vcc - 0.2V or < 0.2V(2) other inputs = 0 ~ Vcc BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V (3) other inputs = 0 ~ Vcc Vcc=2.0V 2.2V 2.2V 2.2V 2.0 V S2 < 0.2V 0.2V Note 9: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested. 30 ~ +70°C ~ +40°C 0.2 ~ +25°C - 0.4 3.0 6.0 Chip select input S2 Min Typ Max BC# control mode S1# control mode 60 ~ +85°C - -BYTE# > Vcc - 0.2V or < 0.2V

Jan.10,2003 Ver. 2.1 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products betterand more reliable, but there isalways the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, progr ams, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.