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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 33
Technical content
Datasheet sections
- 2.1 Motherboard-down topology
- 2.2 Adaptor topology
- 3.1 Ball grid array diagram
- 3.2 Signal mapping sorted by ball (pin) number
- 4.1 Pin list
- 4.2 Bootstrap configuration
- 4.3 RESETN connection
- 5.1 Package drawing
- 5.2 LFBGA 7 x 7 dimensions
- 5.3 Marking field template and descriptors
- 5.4 Classification reflow profile
- 6.1 Absolute maximum ratings
- 6.2 Power Connections
- 6.3 DC characteristics
- 6.4 AC characteristics
- 6.4.1 DisplayPort receiver
- 6.4.2 HDMI transmitter I/O specifications
- 6.4.3 I2C interface timing
- 6.4.4 SPI interface timing
MegaChips’ Proprietary Information Page 1 of 33 MegaChips’ Proprietary Information MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon. MCDP28x0 DisplayPort1.2a to HDMI2.0 Level Shifter/Protocol Converter [LSPCON] Datasheet Rev B
C28x0-DAT-01p MegaChips’ Proprietary Information Page 2 of 33
Features
- DisplayPort® (DP) ver. 1.2a receiver – Link rate HBR2/HBR/RBR – 1, 2, or 4 lanes configuration – AUX CH 1 Mbps, HPD out – Supports eDP ASSR scrambler operation
- HDMI ver. 2.0 transmitter – Max data rate up to 6.0 Gbps/ch – Deep color up to 16 bits per color – 3D video timings, CEC, HPD in – Supports High Dynamic Range (HDR) – Supports scrambling for the higher data rate
- Level shifter operation (up to 3.4Gbps/ch) – AC-coupled HDMI1.4b to DC-coupled HDMI1.4b – PHY analog repeater (re-driver or re-timer) – 3.3 V DDC/AUX CH signaling support with auto detect – 3.3 V DDC to 5V DDC buffering – I2C-over-AUX to 5V DDC translation – DP HPD_OUT matched to HDMI HPD_IN
- Protocol converter operation (up to 6.0 Gbps/ch) – DP SST-to-HDMI format conversion – Video and audio forwarding – Pixel encoding format conversion from YCbCr444 to YCbCr420 – Horizontal expansion of VESA CVT to CEA-861 timings – Meta data handing
- Level shifter – Protocol converter mode switching – Via sideband communication (AUX CH/ DDC)
- Max video resolution and color depth – 4Kp60Hz, RGB/YCbCr444, 8bpc – 4Kp60Hz, YCbCr420, up to 16bpc – 4Kp30Hz, RGB/YCbCr444, up to 16bpc
- YCbCr420 support – YCbCr444-to-420 conversion, up to 16 bpc – YCbCr420 pass through, up to 16 bpc
- Stereoscopic 3D forwarding – Conversion from frame sequential over DP to stacked top-bottom 3D over HDMI – All other 3D formats forwarded as is
- Audio forwarding – 2-ch, 768 kHz 24bps HBR audio – Up to 8-ch, 192 kHz, 24bps LPCM audio, AC3, DTS
- Secure communication – Intel secure communication protocol compliant with LSPCON spec
- HDCP content protection – Embedded HDCP keys – HDCP2.2 transmitter – HDCP1.x repeater
- Metadata handling – HDMI TX DVI/HDMI mode setting (DPCD register) – YCbCr444-420 conversion (DPCD register) – IEC60958 BYTE3 channel status overwrite – CEA861F INFOFRAME generation – CEA861-3 HDR and Mastering InfoFrame
- SCDC read request handling – Polling enabled for HDMI sinks not supporting read request
- AUX to I2C bridge for EDID/MCCS pass through
- CEC tunneling over AUX CH
- Device configuration options – SPI flash for firmware binary image storage required – AUX CH, I2C host interface (optional)
- EMI reduction support – Spread spectrum for DP input – Scrambler for DP input and HDMI2.0a output
- Low power operation – 412 mW in protocol converter mode – 100 mW in Level shifter mode – 0.1 mW in connected standby mode
- ESD specification – +/-6.5 KV HBM, 500 V CDM
- Package – 64 LFBGA (7 x 7 mm)
- Power supply voltages – 3.3 V I/O; 1.2 V core
C28x0-DAT-01p MegaChips’ Proprietary Information – Strictly Confidential Page 3 of 33
Applications
- PC notebook/ tablet motherboard
- DP/USB Type-C docking station, dongle
Figure 1. MCDP28x0 internal block diagram
C28x0-DAT-01p MegaChips’ Proprietary Information Page 7 of 33 1. Description The MCDP28x0 is a power-optimized DisplayPort1.2a-to-HDMI 2.0 converter device targeted for desktop/mobile PC motherboard-down applications and for DP or USB type-C adaptor (dongle, docking station) applications. This device functions as a level shifter as well as an active protocol converter. In level shifter mode, the device functions as a PHY repeater with optional jitter removal capability. This operating mode provides a low-power means of using an AC-coupled TMDS signal from a dual mode DP (DP++) source to be repeated to the HDMI output. The maximum TMDS character clock frequency in this mode is limited to 340 Mchar/s (per HDMI1.4b specification). In Protocol Converter (PCON) mode, MCDP28x0 functions as a DP branch device receiving AC coupled DisplayPort stream and converting it to HDMI output. The maximum TMDS character clock frequency supported in this mode is up to 600 Mchar/s (as per the HDMI2.0a specification). The MCDP28x0 operates with two power supply voltages: 1.2 V and 3.3 V. It consumes:
- 100 mW in PHY analog repeater mode
- 412 mW in protocol converter mode
- 0.1 mW in connected standby mode (1.2 V power rail disabled) The MCDP28x0 has a DisplayPort1.2a dual-mode receiver and HDMI 2.0a transmitter. The upstream main link can receive DP input at HBR2 rate over 4 lanes and AC-coupled TMDS signal up to 340Mchar/s. It supports DP SST stream on its main link and Manchester-coded AUX signaling or native 3.3 I2C signaling as the side band channel with the DP++ source. The downstream HDMI TX port is HDMI 2.0 specification compliant. The MCDP28x0 is capable of supporting Ultra High-Definition video formats, resolutions as high as 4096 x 2160@60 Hz. It supports RGB/YCbCr video color formats with a color depth of 16 bpc (or 48 bits per pixel) as long as it fits within the DP1.2 and HDMI2.0a link rate. In addition, this device also supports pixel encoding conversion from YCbCr444 to YCbCr420 and YcbCr420 pass-through from a DP input to an HDMI output. High Dynamic Range (HDR) with deep color up to 12bpc at 4Kp60Hz is supported through the conversion of YCbCr444 CVT timing over DP link with horizontal expansion to YCbCr420 CEA timing on the HDMI TX output. This device offers secure reception and transmission of high bandwidth digital audio and video content with HDCP 1.x content protection for the upstream DP interface and HDCP2.2 for the downstream HDMI interface. It also operates as an HDCP1.x repeater between the source and the sink. In addition, it conforms to the secure communication protocol specified in the Intel “LSPCON Security Requirements
C28x0-DAT-01p MegaChips’ Proprietary Information Page 8 of 33 Architecture Specification” document. The MCDP28x0 comes with embedded HDCP keys that are stored in encrypted form. The MCDP28x0 uses an external crystal of 27 MHz as a reference clock for its operation and it has a reset input which provides the chip reset during system power up. The device has an on-chip microcontroller with SPI, UART, and I2C interfaces for system level communication and debug. It requires an external SPI flash memory for storing device configuration firmware. The firmware update is done through the DP AUX channel or through UART interface. An 8 Mbit SPI flash memory is recommended for storing the firmware with a backup option as fail-safe during in-system-programming.
- Mobile PC motherboard application. This is referred as motherboard-down topology and the part number that supports this topology is MCDP2800.
- Accessory application (dongle, docking station etc.). This is referred as adaptor topology and the part number for this topology is MCDP2850.
2.1 Motherboard-down topology
Gbps. The analog repeater mode saves the active power consumption during low frequency oeprtation. protected content over the HDMI output. Figure 2. MCDP2800 motherboard-down use case
2.2 Adaptor topology
function allowed in this topology. topology due to longer traces and multiple connectors in the path. Figure 3. MCDP2850 adaptor (dongle) use case
- BGA footprint and pin lists
3.1 Ball grid array diagram
the top looking down using the PCB footprint. Figure 4. MCDP28x0 BGA diagram
3.2 Signal mapping sorted by ball (pin) number
Table 1. Pin list
Table 1. Pin list (continued)
4.1 Pin list
Table 2. DisplayPort receiver pins
C28x0-DAT-01p MegaChips’ Proprietary Information Page 15 of 33 Table 3. HDMI output pins Ω resistor. Also functions as DDC_SCL. Ω resistor. Also functions as DDC_SDA. VDD12_RX (1.2 V analog power supply). INPUT use weak pull-down when not used.
Description
H1 HDMITX_CLKN O 3.3 V HDMI transmitter CLOCK_N to TX connector H2 HDMITX_CLKP O 3.3 V HDMI transmitter CLOCK_P to TX connector H3 HDMITX_CH0N O 3.3 V HDMI transmitt er DATA0_N to TX connector H4 HDMITX_CH0P O 3.3 V HDMI transmitter DATA0_P to TX connector H5 HDMITX_CH1N O 3.3 V HDMI transmitt er DATA1_N to TX connector H6 HDMITX_CH1P O 3.3 V HDMI transmitter DATA1_P to TX connector H7 HDMITX_CH2N O 3.3 V HDMI transmitt er DATA2_N to TX connector H8 HDMITX_CH2P O 3.3 V HDMI transmitter DATA2_P to TX connector Pin Assignment I/O VDD Domain Description
C28x0-DAT-01p MegaChips’ Proprietary Information Page 16 of 33 Table 4. System interface pins tolerant. Open drain, external 2.2 K pull up to +5 V. tolerant. Open drain, external 2.2 K pull up to +5 V. Ohm recommended) as per HDMI1.4b spec.
3.3 V logic level, 5 V tolerant input from HDMI
connector. To be externally pulled down via resistor.
1.2 V power control signal to control
Figure 4. Reset State definition
C28x0-DAT-01p MegaChips’ Proprietary Information Page 17 of 33 D8 TEST IO 3.3 V NA Test select. Tie to GND for mission mode E6 I2C_SDA IO 3.3 V Input, Internal PU Host I2C interface data line. External pull-up required for I2C operation. Leave NC when not used. F6 I2C_SCL I 3.3 V Input, Internal PU Host I2C interface clock line. External pull-up required for I2C operation. Leave NC when not used. C3 GPIO1 IO 3.3 V Input, Internal PU General purpose input/output. Applicable for CONFIG2 if needed. Default POR state is INPUT; use weak pull-down when not used. C1 SPI_CSN O 3.3 V Input, Internal PU Serial peripheral interface chip select C2 SPI_DI I 3.3 V Input, Internal PD Serial peripheral interface data input D1 SPI_DO O 3.3 V Input, Internal PD Serial peripheral interface data output D2 SPI_CLK O 3.3 V Input, Internal PD Serial peripheral interface clock E2 SPI_WP O 3.3 V Input, Internal PD Serial peripheral interface write protect D7 UART_TX O 3.3 V Input, Internal PU Universal asynchronous serial Tx output. Leave NC when not used. Pin Assignment I/O VDD Domain Reset State Description
Table 5. Power and ground pins
4.2 Bootstrap configuration
be adhered to for the normal function of the device. Table 6. Bootstrap configuration
4.3 RESETN connection
open-drain output is not available, the series resistor shown in the figure below is required. Figure 5. RESETN Connection to MCDP28x0 32 K of OCM memory map. OCM boots from IROM. 0: Select external CLK on XTAL pin (used in ATE).
5.1 Package drawing
Figure 6. MCDP28x0 package drawing
5.2 LFBGA 7 x 7 dimensions
Figure 7. MCDP28x0 package dimensions
5.3 Marking field template and descriptors
The MCDP28x0 marking template is shown below. (1) - LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Thin profile: 1.00mm < A 1.20mm / Fine pitch: e < 1.00mm pitch.
(2) – The typical ball diameter before mounting is 0.40mm. (3) – LFBGA with 0.40mm pitch is not yet registered into JEDEC Publications. (4) - The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. (5) - The tolerance of position that controls the location of the balls within the matrix with respect to each other. as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. The axis of each ball must lie simultaneously in both tolerance zones. ink or metallized markings, or other feature of package body or integral heatslug. corner. Exact shape of each corner is optional.
Figure 8. Marking template Field descriptors are shown below.
5.4 Classification reflow profile
APN-06) for reflow diagram and details.
- Marked ES for Engineering Samples, used for development purposes.
- Electrical specifications
6.1 Absolute maximum ratings
Table 8. Absolute maximum ratings Note (1): All voltages are measured with respect to GND. Note (2): Absolute maximum voltage ranges are for transient voltage excursions. recommended. Refer to the MCDP28x0 Layout Guideline appnote.
C28x0-DAT-01p MegaChips’ Proprietary Information Page 24 of 33
6.2 Power Connections
VDD33_RX 249ohm/1% 0.1uF 0.1uF VDD12_TX VDD12_RX VDD33_TX VDD12_OSC VDD12_PLL TCLK XTAL 0.1uF 22pF 22pF GND VDD33_IO VDD12_DIG pF 0.1uF 0.1uF 0.1uF From 3.3V regulator 0.1uF CEXT 2.2uF 0.1uF VDD12ON 0.01uF V_ON V_OUT GND V_IN 1.2V REGULATOR E3VDD33_IO G4VDD33_TX 0.1uF uF VDD33_RX VDD12_RXB4 B3, B6, D4, D5, E4, E5, G3, G6, D8 VDD12_DIG VDD12_TX G5 0.1uF 0.1uF VDD33_AUX FB= FERRITE BEAD 120Ohms@100MHz FB FB FB FB FB FB FB
6.3 DC characteristics
Table 9. DC characteristics Table 10. IO DC characteristics
6.4 AC characteristics
Table 11. Maximum speed of operation
6.4.1 DisplayPort receiver
Table 12. DisplayPort receiver characteristics
6.4.2 HDMI transmitte r I/O specifications
Table 13. HDMI transmitter I/O specifications Table 14. HDMI transmitter AC characteristics
6.4.3 I2C interface timing
Table 15. I2C interface timing SP= Repeated stop conditions. Figure 9. I2C timing
6.4.4 SPI interface timing
Table 16. SPI interface timing, VDD = 3.3 V
Table 17. Order codes application. Mass production parts. Delivered in trays. MCDP2850-BB 64 LFBGA (7 x 7 x 1.4 mm) for dongle application. MCDP2850-BBT 64 LFBGA (7 x 7 x 1.4 mm) for dongle application. application. Mass production parts. Delivered in trays. MCDP2850-BC 64 LFBGA (7 x 7 x 1.4 mm) for dongle application. MCDP2850-BCT 64 LFBGA (7 x 7 x 1.4 mm) for dongle application.
Table 18. Document revision history 09-Mar-2016 A Initial version.
C28x0-DAT-01p MegaChips’ Proprietary Information Page 33 of 33 Notice Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor products The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the semiconductor product and do not guarantee operability in equipment in which the product is actually used. The names of companies and trademarks stated in this document are registered trademarks of the relevant companies. MegaChips Co. provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property rights and other such rights belonging to third parties or/and MegaChips Co. in the use of products and of technical information including information on the overview of operations and the circuit diagrams that are described in this document. The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation shall be valid in Japan domestic. In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips Co. in advance. All information contained in this document is subject to change without notice. Copyright ©2016 MegaChips Corporation All rights reserved MegaChips Corporation Head Quarters 1-1-1 Miyahara, Yodogawa-ku Osaka 532-0003, Japan TEL: +81-6-6399-2884 MegaChips Corporation Taiwan Branch RM. B 2F, Worldwide House, No.129, Min Sheng E. Rd., Sec. 3, Taipei 105, Taiwan TEL: +886-2-2547-1297 MegaChips Corporation Tokyo Office 17-6 Ichiban-cho, Chiyoda-ku, Tokyo 102-0082, Japan TEL: +81-3-3512-5080 MegaChips Corporation Tainan Office RM. 2, 8F, No.24, Da Qiao 2 Rd., Yong Kang Dist., Tainan 710, Taiwan TEL: +886-6-302-2898 MegaChips Corporation Makuhari Office 1-3 Nakase Mihama-ku Chiba 261-8501, Japan TEL: +81-43-296-7414 MegaChips Corporation Zhunan Office No.118, Chung-Hua Rd., Chu-Nan, Miao-Li 350, Taiwan TEL: +886-37-666-156 MegaChips Corporation San Jose Office 2033 Gateway Place, Suite 400, San Jose, CA 95110 U.S.A. TEL: +1-408-570-0555 MegaChips Corporation Shenzhen Office Room 6307, Office Tower, Shun Hing Square, 5002 Shen Nan Dong Road, Luohu District, Shenzhen 518000, P. R. China TEL: +86-755-3664-6990 MegaChips Corporation India Branch 17th Floor, Concorde Block UB City, Vittal Mallya Road, Bangalore 560-001, India TEL: +91-80-4041-3999