ML12009 LANSDALE

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www.lansdale.comPage 1 of 14 Issue A ML12009 ML12011 MECL PLL Components Dual Modulus Prescaler Legacy Device: Motorola MC12009, MC12011 These devices are two–modulus prescalers which will divide by 5 and 6, 8 and 9, respectively. A MECL–to–MTTL translator is provided to interface directly with the Motorola MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source.

  • ML12009 480 MHz (÷5/6), ML12011 550 MHz (÷8/9)
  • MECL to MTTL Translator on Chip
  • MECL and MTTL Enable Inputs
  • 5.0 or –5.2 V Operation*
  • Buffered Clock Input — Series Input RC T yp, 20 Ω and 4.0 pF
  • VBB Reference V oltage
  • 310 mW (T yp) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 (MTTL V CC), Pin 16 (V CC), and ground Pin 8 (VEE). When using –5.2 V supply, ground Pin 1 (V CCO), Pin 6 (MTTL VCC), and Pin 16 (VCC) and apply –5.2 V to Pin 8 (VEE). If the translator is not required, Pin 6 may be left open to conserve DC power drain. P DIP 16 = EP PLASTIC PACKAGE CASE 648 SO 16 = -5P PLASTIC PACKAGE CASE 751B CROSS REFERENCE/ORDERING INFORMATION MOTOROLA P DIP 16 MC12009P ML12009EP SOIC 16 MC12009D ML12009-5P P DIP 16 MC12011P ML12011EP SO 16W MC12011D ML12011-5P LANSDALEPACKAGE Note: Lansdale lead free ( Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.11 6 (Top View) VCCO Q Q MTTL VCC MTTL Output VEE VCC E5 MECL PIN CONNECTIONS Clock VBB E2 MECL E1 MECL E3 MECL E4 MECL ( – ) ( + ) MAXIMUM RATINGS Characteristic Symbol Rating Unit (Ratings above which device life may be impaired) Power Supply Voltage (VCC = 0) VEE –8.0 Vdc Input Voltage (VCC = 0) Vin 0 to VEE Vdc Output Source Current Continuous Surge IO 100 mAdc Storage Temperature Range Tstg –65 to 175 °C (Recommended Maximum Ratings above which performance may be degraded) Operating Temperature Range ML12009, ML12011 TA –30 to 85 °C DC Fan–Out (Note 1) (Gates and Flip–Flops) n 70 — NOTES: 1. AC fan–out is limited by desired system performance.

www.lansdale.comPage 4 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.) Test Limits Pin Under –30°C 25°C 85°C Characteristic Symbol Under Test Min Max Min Max Min Max Unit Power Supply Drain Current ICC1 8 –88 –80 –80 mAdc ICC2 6 5.2 5.2 5.2 mAdc Input Current IinH1 15 375 375 375 375 250 250 250 250 250 250 250 250 µAdc IinH2 4 1.7 1.7 6.0 6.0 2.0 2.0 6.0 6.0 2.0 2.0 6.4 6.4 mAdc IinH4 9 100 100 100 100 100 100 µAdc Leakage Current IinL1 15 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 µAdc IinL2 9 –1.6 –1.6 –1.6 –1.6 –1.6 –1.6 mAdc Reference Voltage VBB 14 –1.360 –1.160 Vdc Logic ‘1’ Output Voltage VOH1 (Note 1) –1.100 –1.100 –0.890 –0.890 –1.000 –1.000 –0.810 –0.810 –0.930 –0.930 –0.700 –0.700 Vdc Logic ‘0’ Output Voltage VOL1 (Note 1) –1.990 –1.990 –1.675 –1.675 –1.950 –1.950 –1.650 –1.650 –1.925 –1.925 –1.615 –1.615 Vdc VOL2 7 –4.26 –4.40 –4.48 Logic ‘1’ Threshold Voltage VOHA (Note 2) –1.120 –1.120 –1.020 –1.020 –0.950 –0.950 Vdc Logic ‘0’ Threshold Voltage VOLA (Note 3) –1.655 –1.655 –1.630 –1.630 –1.595 –1.595 Vdc Short Circuit Current IOS 7 –65 –20 –65 –20 –65 –20 mAdc NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. VIHmax VILmin Clock Input

www.lansdale.comPage 5 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIH VILH Pin Under TEST VOLTAGE APPLIED TO PINS LISTED BELOW Characteristic Symbol Under Test VIHmax VILmin VIHAmin VILAmax VIH VIL Gnd Power Supply Drain Current ICC1 8 1,16 ICC2 6 4 5 6 Input Current IinH1 15 1,16 1,16 1,16 1,16 IinH2 4 IinH3 5 4 5 6 IinH4 9 1,16 1,16 Leakage Current IinL1 15 1,16 1,16 1,16 1,16 IinL2 9 1,16 1,16 Reference Voltage VBB 14 1,16 Logic ‘1’ Output Voltage VOH1 (Note 1) 11,12,13 11,12,13 9,10 9,10 1,16 1,16 VOH2 7 5 4 6 Logic ‘0’ Output Voltage VOL1 (Note 1) 11,12,13 11,12,13 9,10 9,10 1,16 1,16 VOL2 7 4 5 6 Logic ‘1’ Threshold Voltage VOHA (Note 2) 11,12,13 11,12,13 1,16 1,16 Logic ‘0’ Threshold Voltage VOLA (Note 3) 11,12,13 11,12,13 1,16 1,16 Short Circuit Current IOS 7 5 4 7 6 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. VIHmax VILmin Clock Input

www.lansdale.comPage 6 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts mA @ Test Temperature VIHT VILT VEE IL IOL IOH Pin Under TEST VOLTAGE APPLIED TO PINS LISTED BELOW Characteristic Symbol Under Test VIHT VILT VEE IL IOL IOH Gnd Power Supply Drain Current ICC1 8 8 1,16 ICC2 6 8 6 Input Current IinH1 15 9,10 9,10 9,10 1,16 1,16 1,16 1,16 IinH2 4 IinH3 5 8 6 IinH4 9 1,16 1,16 Leakage Current IinL1 15 8,15 8,11 8,12 8,13 1,16 1,16 1,16 1,16 IinL2 9 1,16 1,16 Reference Voltage VBB 14 8 14 1,16 Logic ‘1’ Output Voltage VOH1 (Note 1) 1,16 1,16 VOH2 7 8 7 6 Logic ‘0’ Output Voltage VOL1 (Note 1) 1,16 1,16 VOL2 7 8 7 6 Logic ‘1’ Threshold Voltage VOHA (Note 2) 9,10 9,10 1,16 1,16 Logic ‘0’ Threshold Voltage VOLA (Note 2) 9,10 9,10 1,16 1,16 Short Circuit Current IOS 7 8 6 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. VIHmax VILmin Clock Input

www.lansdale.comPage 7 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.) Test Limits Pin Under –30°C 25°C 85°C Characteristic Symbol Under Test Min Max Min Max Min Max Unit Power Supply Drain Current ICC1 8 –88 –80 –80 mAdc ICC2 6 5.2 5.2 5.2 mAdc Input Current IinH1 15 375 375 375 375 250 250 250 250 250 250 250 250 µAdc IinH2 4 1.7 1.7 6.0 6.0 2.0 2.0 6.0 6.0 2.0 2.0 6.4 6.4 mAdc IinH4 9 100 100 100 100 100 100 µAdc Leakage Current IinL1 15 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 µAdc IinL2 9 –1.6 –1.6 –1.6 –1.6 –1.6 –1.6 mAdc Reference Voltage VBB 14 3.67 3.87 Vdc Logic ‘1’ Output Voltage VOH1 (Note 1) 3.900 3.900 4.110 4.110 4.000 4.000 4.190 4.190 4.070 4.070 4.300 4.300 Vdc VOH2 7 2.4 2.6 2.8 Logic ‘0’ Output Voltage VOL1 (Note 1) 3.070 3.070 3.385 3.385 3.110 3.110 3.410 3.410 3.135 3.135 3.445 3.445 Vdc VOL2 7 0.94 0.80 0.72 Logic ‘1’ Threshold Voltage VOHA (Note 2) 3.880 3.880 3.980 3.980 4.050 4.050 Vdc Logic ‘0’ Threshold Voltage VOLA (Note 3) 3.405 3.405 3.430 3.430 3.465 3.465 Vdc Short Circuit Current IOS 7 –65 –20 –65 –20 –65 –20 mAdc NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. VIHmax VILmin Clock Input

www.lansdale.comPage 8 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIH VILH Pin Under TEST VOLTAGE APPLIED TO PINS LISTED BELOW (V ) Characteristic Symbol Under Test VIHmax VILmin VIHAmin VILAmax VIH VIL (VEE) Gnd Power Supply Drain Current ICC1 8 8 ICC2 6 4 5 8 Input Current IinH1 15 IinH2 4 IinH3 5 4 5 8 IinH4 9 Leakage Current IinL1 15 8,15 8,11 8,12 8,13 IinL2 9 Reference Voltage VBB 14 8 Logic ‘1’ Output Voltage VOH1 (Note 1) 11,12,13 11,12,13 9,10 9,10 VOH2 7 5 4 8 Logic ‘0’ Output Voltage VOL1 (Note 1) 11,12,13 11,12,13 9,10 9,10 VOL2 7 4 5 8 Logic ‘1’ Threshold Voltage VOHA (Note 2) 11,12,13 11,12,13 Logic ‘0’ Threshold Voltage VOLA (Note 3) 11,12,13 11,12,13 Short Circuit Current IOS 7 5 4 7 8 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. VIHmax VILmin Clock Input

www.lansdale.comPage 9 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts mA @ Test Temperature VIHT VILT VCC IL IOL IOH Pin Under TEST VOLTAGE APPLIED TO PINS LISTED BELOW (V ) Characteristic Symbol Under Test VIHT VILT VCC IL IOL IOH (VEE) Gnd Power Supply Drain Current ICC1 8 1,16 8 ICC2 6 6 8 Input Current IinH1 15 9,10 9,10 9,10 1,16 1,16 1,16 1,16 IinH2 4 IinH3 5 6 8 IinH4 9 1,16 1,16 Leakage Current IinL1 15 1,16 1,16 1,16 1,16 8,15 8,11 8,12 8,13 IinL2 9 1,16 1,16 Reference Voltage VBB 14 1,16 14 8 Logic ‘1’ Output Voltage VOH1 (Note 1) 1,16 1,16 VOH2 7 6 7 8 Logic ‘0’ Output Voltage VOL1 (Note 1) 1,16 1,16 VOL2 7 6 7 8 Logic ‘1’ Threshold Voltage VOHA (Note 2) 9,10 9,10 1,16 1,16 Logic ‘0’ Threshold Voltage VOLA (Note 3) 9,10 9,10 1,16 1,16 Short Circuit Current IOS 7 6 8 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. VIHmax VILmin Clock Input

Figure 5. AC Test Circuit All Pulse Generators are EH 137 or equiv. All input and output cables to the scope are equal lengths of 50 Ω coaxial cable. The 1950 Ω resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe. CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance. Unused output connected to a 50 Ω resistor to ground.

100 Vin

Figure 6. Maximum Frequency Test Circuit

5 Cycles 4 Cycles

Figure 7. State Diagram oscillator of two–way radios. In their basic form, these devices will divide by 5/6 or 8/9. division configurations may be obtained.

www.lansdale.comPage 14 of 14 Issue A LANSDALE Semiconductor, Inc.ML12009, ML12011 SO 16 = -5P PLASTIC PACKAGE (ML12009-5P, ML12011-5P) CASE 751B–05 (SO–16) ISSUE J OUTLINE DIMENSIONS P DIP 16 = EP PLASTIC PACKAGE (ML12009EP, ML12011EP) CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45 G

8 PLP–B–

–A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.