LTC1983-3 LINER
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Technical content
®1983-3 and LTC1983-5 are inverting charge pump DC/DC converters that produce negative regulated outputs. The parts require only three tiny external capaci- tors and can provide up to 100mA of output current. The devices can operate in open loop mode (creating a –VIN supply) or regulated output mode depending on the input supply voltage and the output current. The LTC1983-3/LTC1983-5 have many useful features for portable applications including very low quiescent current (25µA typical) and a zero current shutdown mode pro- grammed through the SHDN pin. The LTC1983-3/LTC1983-5 are over-temperature and short-circuit protected. The parts are available in a 6-pin low profile (1mm) ThinSOT package. I –3V Generation in Single-Supply Systems I Portable Equipment I LCD Bias Supplies I GaAs FET Bias Supplies I Fixed Output Voltages: –3V, –5V or Low Noise VIN to –VIN Inverted Output I ±4% Output Voltage Accuracy I Low Quiesient Current: 25µA I 100mA Output Current Capability I 3V to 5.5V Operating Voltage Range (LTC1983-3) I 2.3V to 5.5V Operating Voltage Range (LTC1983-5) I Internal 900kHz Oscillator I “Zero Current” Shutdown I Short-Circuit and Over-Temperature Protected I Low Profile (1mm) ThinSOT 100mA Regulated Charge-Pump Inverters in ThinSOT , LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. VIN SHDN VOUT GND LTC1983-3 VIN 3V TO 5.5V VOUT = –3V IOUT = UP TO 100mA COUT 10µF CIN 10µF CFLY 1µF OFF ON CFLY: TAIYO YUDEN LMK212BJ105 CIN, COUT: TAIYO YUDEN JMK316BJ106ML 1983-3 TA01 VOUT vs IOUT IOUT (mA) VOUT (V) –3.3 –3.2 –3.1 –3.0 –2.9 –2.8 –2.7
1983 TA02
VIN = 5V VIN = 3.3V DESCRIPTIO U
FEATURES
U TYPICAL APPLICATIO U –3V at 100mA DC/DC Converter
Operating Temperature Range (Note 2) ...–40°C to 85°C ORDER PART NUMBER S6 PART MARKING TJMAX = 125°C, θJA = 256°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. LTPC LTYB LTC1983ES6-3 LTC1983ES6-5 ABSOLUTE AXI U RATI GS W W W U PACKAGE/ORDER I FOR ATIO U U W (Note 1)
ELECTRICAL CHARACTERISTICS
Burst Mode is a registered trademark of Linear Technology Corporation. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. The G denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, CFLY = 1µF, COUT = 10µF unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage (Regulated Output Mode) (LTC1983-3) G 3.0 5.5 V VIN Min Startup Voltage 2.3 V VOUT (LTC1983-3) VIN ≥ 3.3V, IOUT ≤ 25mA G –2.88 –3.12 V VIN ≥ 5V, IOUT ≤ 100mA G –2.88 –3.12 V VOUT (LTC1983-5) VIN ≥ 5V, VIN –5V ≥ IOUT • ROUT G – 4.8 –5.2 V VIN Operating Current VIN ≤ 5.5V, IOUT = 0µA, SHDN = VIN G µA VIN Operating Current (Open-Loop Mode) (LTC1983-5) VIN = 3.3V 2.5 mA VIN = 4.75V mA VIN Shutdown Current SHDN = 0V, VIN ≤ 5.5V G 0.1 µA Output Ripple 3.3 ≤ VIN ≤ 5.5 mVP-P Open-Loop Output Impedance (LTC1983-3): ROUT VIN = 3.3V, VOUT = –3V Ω Open-Loop Output Impedance (LTC1983-5): ROUT VIN = 3.3V, IOUT ≈ 50mA Ω VIN = 5V, IOUT ≈ 60mA 8.5 Ω Oscillator Frequency (Non-Burst Mode ® Operation) 900 kHz SHDN Input High G 1.1 V SHDN Input Low G 0.3 V SHDN Input Current VSHDN = 5.5V G 2.2 µA VCC 1 VOUT 2 C+ 3
6 SHDN
5 GND
4 C– TOP VIEW S6 PACKAGE 6-LEAD PLASTIC SOT-23 Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.
vs IOUT (LTC1983-5) Efficiency vs IOUT (LTC1983-5) TYPICAL PERFOR A CE CHARACTERISTICS U W Efficiency vs IOUT IOUT (mA) EFFICIENCY (%) 100
1983 G01
VIN = 2.3V VIN = 3.3V VIN = 5V TA = 25°C VIN (V) 2.35 ROUT (Ω) 4.35 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 3.35 5.35 ROUT IOUT = 25mA TA = 25°C IOUT (mA) ROUT (Ω) 100
1983 G03
VIN = 2.3V VIN = 3.3V VIN = 5V TA = 25°C IOUT (mA) 0.01 100
1983 GO4
0.1 100 EFFICIENCY (%) VIN = 5V VIN = 3.3V VOUT = –3V TA = 25°C OUTPUT CURRENT (mA) –2.1 –2.3 –2.5 –2.7 –2.9 –3.1 –3.3 –3.5 100
1983 G05
VOUT (V) 120°C –40°C, 0°C, 40°C 80°C OUTPUT CURRENT (mA) 2.7 VOUT (–V) 2.8 2.9 3.0 3.1 3.3
1983 G06
3.2 –40°C 0°C 40°C 80°C VIN = 5V –3VOUT vs IOUT Over Temperature –3VOUT vs IOUT Over Temperature (VIN = 5V) Open-Loop Current vs Temperature (LTC1983-5) TEMPERATURE (°C) –40 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5
1983 G07
IIN (mA) VIN = 5V Burst Mode Current vs Temperature (LTC1983-3) TEMPERATURE (°C) –40 IIN (µA)
1983 G08
VIN = 5V Open-Loop Input Current vs VIN (LTC1983-5) VIN (V) 2.3 1.5 IIN (mA) 2.0 2.5 3.0 3.5 4.5 2.8 3.3 3.3 4.3
1983 G09
4.8 4.0 TA = 25°C
TYPICAL PERFOR A CE CHARACTERISTICS U W Burst Mode Input Current vs VIN (LTC1983-3) VIN (V) 3.1 26.5 INPUT CURRENT (µA) 27.0 28.0 28.5 29.0 4.1 5.1 5.5 31.0
1983 G10
27.5 3.6 4.6 29.5 30.0 30.5 TA = 25°C TEMPERATURE (°C) –50 ROUT (Ω) 150
1983 G11
VIN = 5V VIN = 3V IOUT = 10mA TEMPERATURE (°C) –50 VTHRESHOLD (V) 0.1 0.3 0.4 0.5 1.0 0.7
1983 G12
0.2 0.8 0.9 0.6 100 150 ROUT vs Temperature (IOUT = 10mA) SHDN Pin Threshold Voltage vs Temperature SHDN Pin Input Current vs Temperature ROUT vs CFLY (VIN = 5V) TEMPERATURE (°C) –50 2.0 2.5 3.5 100
1983 G13
1.5 1.0 150 0.5 3.0 ISHDN CFLY (µF) 0.01 1400 VIN = 5V TA = 25°C 1200 1000 800 600 400 200
1983 G14
0.1 ROUT (Ω) VOUT Start-Up into 100mA Resistive Load VOUT Ripple at 100mA Load VOUT Ripple at 30mA Load VOUT Load Step Reponse from IOUT = 0 to IOUT = 100mA VOUT VIN VOUT 20mV 50µs/DIV
1983 G15
1µs/DIV
1983 G16
2.5µs/DIV
1983 G17
100µs/DIV
1983 G18
U U U PI FU CTIO S VIN (Pin 1): Charge Pump Input Voltage. May be between 2.3V and 5.5V. VIN should be bypassed with a ≥4.7µF low ESR capacitor as close as possible to the pin for best performance. VOUT (Pin 2): Regulated Output Voltage for the IC. VOUT should be bypassed with a ≥4.7µF low ESR capacitor as close as possible to the pin for best performance. C+ (Pin 3): Charge Pump Flying Capacitor Positive Termi- nal. This node is switched between VIN and GND (It is connected to VCC during shutdown). C– (Pin 4): Charge Pump Flying Capacitor Negative Termi- nal. This node is switched between GND and VOUT (It is connected to GND during shutdown). GND (Pin 5): Signal and Power Ground for the 6-Pin SOT-23 package. This pin should be tied to a ground plane for best performance. SHDN (Pin 6): Shutdown. Grounding this pin shuts down the IC. Tie to VIN to enable. This pin should not be pulled above the VIN voltage or below GND. BLOCK DIAGRA W CONTROL LOGIC CLOCK2 CLOCK1 S1A S2A S1B S2B VREF CHARGE PUMP SHDN VIN CIN 10µF CFLY 1µF COUT 10µF LTC1983-X VOUT COMP1 1µA 1983 BD
The LTC1983-3/LTC1983-5 use a switched capacitor charge pump to invert a positive input voltage to a regu- lated –3V ±4% (LTC1983-3) or –5 ±4% (LTC1983-5) output voltage. Regulation is achieved by sensing the output voltage through an internal resistor divider and enabling the charge pump when the output voltage droops above the upper trip point of COMP1. When the charge pump is enabled, a 2-phase, nonoverlapping clock con- trols the charge pump switches. Clock 1 closes the S1 switches which enables the flying capacitor to charge up to the VIN voltage. Clock 2 closes the S2 switches that invert the VIN voltage and connect the bottom plate of CFLY to the output capacitor at VOUT. This sequence of charging and discharging continues at a free-running frequency of 900kHz (typ) until the output voltage has been pumped down to the lower trip point of COMP1 and the charge pump is disabled. When the charge pump is disabled, the LTC1983 draws only 25µA (typ) from VIN which provides high efficiency at low load conditions. In shutdown mode, all circuitry is turned off and the part draws less than 1µA from the VIN supply. VOUT is also disconnected from VIN and CFLY. The SHDN pin has a threshold of approximately 0.7V. The part enters shut- down when a low is applied to the SHDN pin . The SHDN pin should not be floated; it must be driven with a logic high or low. Open-Loop Operation The LTC1983-3/LTC1983-5 inverting charge pumps regu- late at –3V/–5V respectively, unless the input voltage is too low or the output current is too high. The equations for output voltage regulation are as follows: VIN –5.06V > IOUT • ROUT (LTC1983-5) VIN –3.06V > IOUT • ROUT (LTC1983-3) If this condition is not met, then the part will run in open loop mode and act as a low output impedance inverter for which the output voltage will be: VOUT = –[VIN –(IOUT • ROUT)] For all ROUT values, check the corresponding curves in the Typical Performance Characteristics section (Note: CFLY = 1µF for all ROUT curves). The ROUT value will be different for different flying caps, as shown in the follow- ing equation: R R curve f C OUT OUT OSC FLY Ω+ )– . 1 11 Short-Circuit/Thermal Protection During short-circuit conditions, the LTC1983 will draw several hundred milliamps from VIN causing a rise in the junction temperature. On-chip thermal shutdown cir- cuitry disables the charge pump once the junction tem- perature exceeds ≈155°C, and reenables the charge pump once the junction temperature falls back to ≈145°C. The LTC1983 will cycle in and out of thermal shutdown indefinitely without latchup or damage until the VOUT short is removed. Capacitor Selection For best performance, it is recommended that low ESR capacitors be used for both CIN and COUT to reduce noise and ripple. The CIN and COUT capacitors should be either ceramic or tantalum and should be 4.7µF or greater. Aluminum electrolytic are not recommended because of their high equivalent series resistance (ESR). If the source impedance is very low, CIN may not be needed. Increasing the size of COUT to 10µF or greater will reduce output voltage ripple. The flying capacitor and COUT should also have low equivalent series inductance (ESL). The board layout is critical as well for inductance for the same reason (the suggested board layout should be used). A ceramic capacitor is recommended for the flying capaci- tor with a value in the range of 0.1µF to 4.7µF. Note that a large value flying cap (>1µF) will increase output ripple unless COUT is also increased. For very low load applica- tions, C1 may be reduced to 0.01µF to 0.047µF. This will reduce output ripple at the expense of efficiency and maximum output current. (Refer to Block Diagram)
is also present mainly due to ESR of the output capacitor. results in higher ripple due to higher output voltage dV/dt. There are several ways to reduce the output voltage ripple. cally found with higher value (larger case size) capacitors. on VOUT to reduce both the low and high frequency ripple. frequency voltage spikes (see Figure 1). reduce the maximum IOUT capability as well as efficiency. Figure 1. Output Ripple Reduction Techniques
1983 F01
of this situation is in USB applications. and the part draws only leakage current from the output. verified for each different board design. be forced high as in normal operation. signal is used on the SHDN pin (e.g., 50Hz to 100Hz). Figure 2. Ultralow Quiescent Current Regulated Supply
1983 F02
problem in the low IQ mode, it is necessary to switch the part in and out of shutdown at the minimum allowable frequency (refer to Figure 3) for a given output load. General Layout Considerations Due to the high switching frequency and high transient currents produced by the LTC1983, careful board layout is a must. A clean board layout using a ground plane and short connections to all capacitors will improve perfor- mance and ensure proper regulation under all conditions (refer to Figures 4a and 4b). You will not get advertised performance with careless layout. Figure 3 OUTPUT CURRENT (µA) 100 1000 MAXIMUM SHDN OFF TIME (ms) 1000
1983 F03b
SHDN ON PULSE WIDTH = 200µs COUT = 10µF Figure 4a. Recommended Component Placement for a Single Layer Board Figure 4b. Recommended Component Placement for a Double Layer Board
1 VIN
2 VOUT
C– 4 COUT CFLY VIN: 2.3V TO 5.5V VOUT
1983 F04a
C– 4 CIN COUT CFLY VOUT
1983 F04b
(Refer to Block Diagram)
U VIN SHDN VOUT GND LTC1983-5 VIN 2.5V TO 5.5V VOUT –VIN 10µF 10µF CERAMIC 1µF CERAMIC OFF ON
1983 TA04
2.5V VOUT –2.5V 1µF CERAMIC 4.7µF CERAMIC 0.47µF CERAMIC OFF ON
1983 TA03
2.5V to –2.5V DC/DC Converter 100mA Inverting DC/DC Converter
U Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6-Lead Plastic SOT-23 (Reference LTC DWG # 05-08-1636) 1.50 – 1.75 (NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
6 PLCS (NOTE 3)
DATUM ‘A’ 0.09 – 0.20 (NOTE 3) S6 TSOT-23 0801
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF PIN ONE ID NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 3.254 0.754 0.854 ±0.127 RECOMMENDED SOLDER PAD LAYOUT
1.9 BSC
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 G FAX: (408) 434-0507 G www.linear.com LINEAR TECHNOLOGY CORPORATION 2002 LT/TP 0302 2K • PRINTED IN USA RELATED PARTS PART NUMBER
DESCRIPTION
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1983 TA05
VBOOST = 2VIN –2(VD)