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LT1715_1 LINER

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Technical content

DESCRIPTION

4ns, 150MHz Dual Comparator with Independent Input/Output Supplies The L T®1715 is an UltraFast™ dual comparator optimized for low voltage operation. Separate supplies allow independent analog input ranges and output logic levels with no loss of performance. The input voltage range extends from 100mV below V EE to 1.2V below VCC. Internal hysteresis makes the L T1715 easy to use even with slow moving input signals. The rail-to-rail outputs directly interface toTTL and CMOS. The symmetric output drive results in similar rise and fall times that can be harnessed for analog applications or for easy translation to other single supply logic levels. The L T1715 is available in the 10-pin MSOP package. The pinout of the L T1715 minimizes parasitic effects by placing the most sensitive inputs away from the outputs, shielded by the power rails. For a dual/quad single supply comparator with simi- lar propagation delay, see the L T1720/L T1721. For a single comparator with similar propagation delay, see the L T1719. 100MHz Dual Differential Line Receiver L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation.

FEATURES

APPLICATIONS

n UltraFast: 4ns at 20mV Overdriven n 150MHz Toggle Frequency n Separate Input and Output Power Supplies n Low Power: 4.6mA per Comparator at 3V n Pinout Optimized for High Speed Use n Output Optimized for 3V and 5V Supplies n TTL/CMOS Compatible Rail-to-Rail Output n Input Voltage Range Extends 100mV Below Negative Rail n Internal Hysteresis with Speciﬁ ed Limits n Speciﬁ ed for –40°C to 125°C Temperature Range n Available in the 10-pin MSOP Package n High Speed Differential Line Receivers n Level T ranslators n Window Comparators n Crystal Oscillator Circuits n Threshold Detectors/Discriminators n High Speed Sampling Circuits n Delay Lines Line Receiver Response to 100MHz Clock, 50MHz Data Both with 25mVP-P Inputs

1715 TA01

–5V 5V 3V IN B 5ns/DIV

1715 TA02

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Supply Voltage Operating Temperature Range (Note 2) Speciﬁ ed Temperature Range (Note 3) (Note 1) +IN A –IN A –IN B +IN B V EE V CC +VS OUT A OUT B GND TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP A B TJMAX = 150°C, θJA = 120°C/W (NOTE 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC – VEE Input Supply Voltage l 2.7 12 V +VS Output Supply Voltage l 2.7 6 V VCMR Input Voltage Range (Note 5) l VEE – 0.1 V CC – 1.2 V VTRIP+ Input T rip Points (Note 6) L T1715C, L T1715I L T1715H l l –1.5 –1.8 5.5 mV mV VTRIP– Input T rip Points (Note 6) L T1715C, L T1715I L T1715H l l –5.5 1.5 1.8 mV mV ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE L T1715CMS#PBF L T1715CMS#TRPBF L TVQ 10-Lead Plastic MSOP 0°C to 70°C L T1715IMS#PBF L T1715IMS#TRPBF L TVV 10-Lead Plastic MSOP –40°C to 85°C L T1715HMS#PBF L T1715HMS#TRPBF L TVV 10-Lead Plastic MSOP –40°C to 125°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V , VEE = –5V , +VS = 5V , VCM = 1V , COUT = 10pF , VOVERDRIVE = 20mV , unless otherwise speciﬁ ed.

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 5V , VEE = –5V , +VS = 5V , VCM = 1V , COUT = 10pF , VOVERDRIVE = 20mV , unless otherwise speciﬁ ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOS Input Offset Voltage (Note 6) L T1715C, L T1715I L T1715H l l 0.4 2.5 3.5 mV mV mV V HYST Input Hysteresis Voltage (Note 6) L T1715C, L T1715I L T1715H l l 3.5 6 mV mV VOS/ΔT Input Offset Voltage Drift l 10 μV/°C IB Input Bias Current L T1715C, L T1715I L T1715H l l –2.5 0 μA μA IOS Input Offset Current L T1715C, L T1715I L T1715H l l 0.2 0.6 μA μA CMRR Common Mode Rejection Ratio (Note 7) L T1715C, L T1715I L T1715H l l 70 dB dB PSRR Power Supply Rejection Ratio (Note 8) l 65 80 dB AV Voltage Gain (Note 9) ∞ VOH Output High Voltage I SOURCE = 4mA, VIN = VTRIP+ + 20mV l +VS – 0.4 V VOL Output Low Voltage I SINK = 10mA, VIN = VTRIP– – 20mV l 0.4 V fMAX Maximum Toggle Frequency (Note 10) 150 MHz tPD20 Propagation Delay V OVERDRIVE = 20mV (Note 11), VCC = 5V , VEE = –5V L T1715C, L T1715I L T1715H l l 2.8 2.8 2.8 ns ns ns V OVERDRIVE = 20mV , VCC = 5V , VEE = 0V 4.4 ns VOVERDRIVE = 20mV , VCC = 3V , VEE = 0V L T1715C, L T1715I L T1715H l l 4.8 6.5 7.5 ns ns ns t PD5 Propagation Delay V OVERDRIVE = 5mV , VEE = 0V (Notes 11, 12) l ns ns tSKEW Propagation Delay Skew (Note 13) Between t PD+/tPD–, VEE = 0V l 0.5 1.5 ns ΔtPD Differential Propagation Delay (Note 14) Between Channels l 0.3 1 ns tr Output Rise Time 10% to 90% 2 ns tf Output Fall Time 90% to 10% 2 ns tJITTER Output Timing Jitter V IN = 1.2VP-P (6dBm), ZIN = 50 t PD+ f = 20MHz (Note 15) t PD– psRMS psRMS ICC Positive Input Stage Supply Current (per Comparator) +VS = VCC = 5V , VEE = –5V L T1715C, L T1715I L T1715H l l 2.2 mA mA +VS = VCC = 3V , VEE = 0V L T1715C, L T1715I L T1715H l l 0.9 1.6 1.8 mA mA IEE Negative Input Stage Supply Current (per Comparator) +VS = VCC = 5V , VEE = –5V L T1715C, L T1715I L T1715H l l –4.8 –5.3 –2.9 mA mA +VS = VCC = 3V , VEE = 0V L T1715C, L T1715I L T1715H l l –3.8 –4.3 –2.4 mA mA IS Positive Output Stage Supply Current (per Comparator) +VS = VCC = 5V , VEE = –5V L T1715C, L T1715I L T1715H l l 4.6 7.5 mA mA VS = VCC = 3V , VEE = 0V L T1715C, L T1715I L T1715H l l 3.7 6 6.5 mA mA

ELECTRICAL CHARACTERISTICS

Input Offset and T rip Voltages vs Supply Voltage Input Offset and T rip Voltages vs Temperature Input Common Mode Limits vs Temperature SUPPL Y VOL TAGE, VCC = +VS (V) 2.5 VOS AND TRIP POINT VOLTAGE (mV) 4.0 5.0

1715 G01

VTRIP– TA = 25°C VCM = 1V VEE = GND TEMPERATURE (°C) VOS AND TRIP POINT VOLTAGE (mV) –20 20 60 100

1715 G02

140–40–60 0 40 80 120 VTRIP+ VOS VTRIP– +VS = VCC = 5V VCM = 1V VEE = –5V TEMPERATURE (°C) –50 3.6 3.8 4.2 25 75

1715 G03

–4.8 –5.0 –25 0 50 100 125 –5.2 –5.4 4.0 COMMON MODE INPUT VOLTAGE (V) +VS = VCC = 5V VEE = –5V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L T1715C is guaranteed functional over the operating range of –40°C to 85°C. Note 3: The L T1715C is guaranteed to meet speciﬁ ed performance from 0°C to 70°C. The L T1715°C is designed, characterized and expected to meet speciﬁ ed performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The L T1715I is guaranteed to meet speciﬁ ed performance from –40°C to 85°C. The L T1715H is guaranteed to meet speciﬁ ed performance from –40°C to 125°C. Note 4: Thermal resistances vary depending upon the amount of PC board metal attached to Pin 5 of the device. θ JA is speciﬁ ed for a 2500mm2 3/32" FR-4 board covered with 2oz copper on both sides and with 100mm2 of copper attached to Pin 5. Thermal performance can be improved beyond the given speciﬁ cation by using a 4-layer board or by attaching more metal area to Pin 5. Note 5: If one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. Note 6: The L T1715 comparator includes internal hysteresis. The trip points are the input voltage needed to change the output state in each direction. The offset voltage is deﬁ ned as the average of V TRIP+ and VTRIP–, while the hysteresis voltage is the difference of these two. Note 7: The common mode rejection ratio is measured with VCC = 5V , VEE = –5V and is deﬁ ned as the change in offset voltage measured from VCM = –5.1V to VCM = 3.8V , divided by 8.9V . Note 8: The power supply rejection ratio is measured with VCM = 1V and is deﬁ ned as the worst of: the change in offset voltage from VCC = +VS = 2.7V to VCC = +VS = 6V (with VEE = 0V) divided by 3.3V or the change in offset voltage from VEE = 0V to VEE = –6V (with VCC = +VS = 6V) divided by 6V . Note 9: Because of internal hysteresis, there is no small-signal region in which to measure gain. Proper operation of internal circuity is ensured by measuring V OH and VOL with only 20mV of overdrive. Note 10: Maximum toggle rate is deﬁ ned as the highest frequency at which a 100mV sinusoidal input results in an error free output toggling to greater than 4V when high and to less than 1V when low on a 5V output supply. Note 11: Propagation delay measurements made with 100mV steps. Overdrive is measured relative to V TRIP±. Note 12: tPD cannot be measured in automatic handling equipment with low values of overdrive. The L T1715 is 100% tested with a 100mV step and 20mV overdrive. Correlation tests have shown that t PD limits can be guaranteed with this test. Note 13: Propagation Delay Skew is deﬁ ned as: t SKEW = |tPDLH – tPDHL| Note 14: Differential propagation delay is deﬁ ned as the larger of the two: ΔtPDLH = |tPDLHA – tPDLHB| ΔtPDHL = |tPDHLA – tPDHLB| Note 15: Package inductances combined with asynchronous activity on the other channel can increase the output jitter . See Channel Interactions in Applications Information. Speciﬁ cation above is with one channel active only. TYPICAL PERFORMANCE CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS Propagation Delay vs Overdrive Propagation Delay vs Temperature Propagation Delay vs Supply Voltage Input Current vs Differential Input Voltage Quiescent Supply Current vs Temperature Quiescent Supply Current vs Supply Voltage Output Low Voltage vs Load Current Output High Voltage vs Load Current Supply Current vs Toggle Frequency DIFFERENTIAL INPUT VOLTAGE (V) INPUT BIAS (μA) 1234

1715 G04

–4 –3 –2 –1 0 5 TA = 25°C VCC = +VS = 5V VEE = –5V TEMPERATURE (°C) –50 SUPPLY CURRENT PER COMPARATOR (mA)

1715 G05

–25 0 50 I S ICC IEE 75 100 125 VCC = +VS = 5V VEE = –5V SUPPLY VOLTAGE, VCC = +VS (V) SUPPLY CURRENT PER COMPARATOR (mA) 2 4 5

1715 G06

TA = 25°C VEE = GND IS, OUTPUT HIGH IS, OUTPUT LOW IEE, OUTPUT LOW IEE, OUTPUT HIGH OUTPUT SINK CURRENT (mA) OUTPUT VOLTAGE (V) 0.3 0.4 0.5

1715 G07

0.2 0.1 4 8 12 20 125°C –55°C 25°C VCC = +VS = 5V, UNLESS OTHERWISE NOTED V IN = –10mV 125°C +VS = 2.7V OUTPUT SOURCE CURRENT (mA) OUTPUT VOLTAGE RELATIVE TO +VS (V) –0.3 –0.2 –0.1

1715 G08

–0.4 –0.5 –0.6 4 8 12 20 –55°C 125°C +VS = 2.7V VCC = +VS = 5V, UNLESS OTHERWISE NOTED V IN = 10mV 125°C 25°C TOGGLE FREQUENCY (MHz) TOTAL SUPPLY CURRENT PER COMPARATOR (mA) 50 100 125 225

1715 G09

TA = 25°C VIN = ±50mV SINUSOID +VS = VCC = 5V VEE = GND CLOAD = 20pF CLOAD = 10pF CLOAD = 0pF INCOMPLETE OUTPUT TOGGLING VALID TOGGLING OVERDRIVE (mV) PROPAGATION DELAY (ns) 30 50

1715 G10

TA = 25°C VSTEP = 100mV CLOAD = 10pF VCC = +VS = 3V VEE = 0V VCC = +VS = 5V VEE = –5V tPDLH TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 7.5

1715 G11

6.0 5.0 –25 0 50 4.5 4.0 3.5 3.0 8.0 7.0 6.5 5.5 75 100 125 tPDLH VSTEP = 100mV CLOAD = 10pF OVERDRIVE = 5mV VCC = +VS = 3V VEE = 0V OVERDRIVE = 20mV VCC = +VS = 5V VEE = –5V 2.5 4.0 3.5 PROPAGATION DELAY (ns) 5.5 5.0 tPDLH tPDLH tPDHL tPDHL 4.5 4.0 5.0

1715 G12

TA = 25°C VSTEP = 100mV OVERDRIVE = 20mV C LOAD = 10pF VEE = GND VEE = –5V SUPPLY VOLTAGE, +VS = VCC OR V+ (V)

+IN A (Pin 1): Noninverting Input of Comparator A. –IN A (Pin 2): Inverting Input of Comparator A. –IN B (Pin 3): Inverting Input of Comparator B. +IN B (Pin 4): Noninverting Input of Comparator B. VEE (Pin 5): Negative Supply Voltage for Input Stage and Substrate. GND (Pin 6): Ground for Output Stage. OUT B (Pin 7): Output of Comparator B. OUT A (Pin 8): Output of Comparator A. +VS (Pin 9): Positive Supply Voltage for Output Stage. VCC (Pin 10): Positive Supply Voltage for Input Stage. PIN FUNCTIONS Maximum Toggle Rate vs Load Capacitance Propagation Delay vs Load Capacitance Response to 150MHz 25mVP-P Sine Wave Driving 10pF OUTPUT CAPACITANCE (pF) TOGGLE FREQUENCY (MHz) 250 225 200 175 150 125 100

1715 G16

10 20 30 50 3551 5 2 5 4 5 TA = 25°C VIN = ±50mV SINUSOID +VS = VCC = 5V VEE = GND OUTPUT LOAD CAPACITANCE (pF) PROPAGATION DELAY (ns) 30 50

1715 G17

TA = 25°C VSTEP = 100mV OVERDRIVE = 20mV S = VCC = 5V VEE = –5V RISING EDGE (tPDLH) FALLING EDGE PDHL) 2.5ns/DIV

1715 G18

VCC = 5V VEE = –5V +VS = 5V VCM = 0V TYPICAL PERFORMANCE CHARACTERISTICS Maximum Toggle Rate vs Input Amplitude Maximum Toggle Rate vs Temperature Maximum Toggle Rate vs Supply Voltage INPUT SINUSOID AMPLITUDE (mV) TOGGLE FREQUENCY (MHz) 100 120 140 160 10 100

1715 G13

180 TA = 25°C

+VS = VCC = 5V VEE = GND CLOAD = 10pF TEMPERATURE (°C) –50 TOGGLE FREQUENCY (MHz) 110 130 150 250 190 0 50 75

1715 G14

–25 25 100 125 TA = 25°C VIN = ±50mV SINUSOID +VS = VCC = 5V VEE = –5V CLOAD = 10pF RLOAD = 500Ω +VS = VCC SUPPLY VOLTAGE (V) TOGGLE FREQUENCY (MHz) 150 175 200

1715 G15

225 TOGGLING FROM

1V TO +VS – 1V TA = 25°C VIN = ±50mV SINUSOID VEE = GND CLOAD = 10pF TOGGLING FROM 20% TO 80% OF +VS

±VTRIP Test Circuit DUT 1/2 L T1715 BANDWIDTH-LIMITED TRIANGLE WAVE ~ 1kHz, VCM ±7.5V LTC203 1/2 LT1112 50Ω 100k 100k 2.4k 10nF 1μF 0.15μF 1/2 LT1638 1/2 LT1638 100k 100k 200k 10k 10k 1000 × VHYST 1000 × VTRIP+ 1000 × VTRIP– 1000 × VOS 0.1μF 50Ω 50k VCM VCC 1/2 LT1112

1715 TC01

10nF 1μF NOTES: LT1638, LT1112, LTC203s ARE POWERED FROM ±15V. 200kΩ PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN DUT IS NOT POWERED 15 3 214 10 6 711 LTC203 2 14 153 7 11 106

Response Time Test Circuit –3V –100mV –5V PULSE IN0V 50Ω 1N5711 400Ω 130Ω 25Ω 50Ω +Vs – VCM VCC – VCM VEE – VCM –VCM 50k DUT 1/2 LT1715 25Ω 0.1μF

1715 TC02

10× SCOPE PROBE (CIN ≈ 10pF) 0.01μF 0.01μF 750Ω 2N3866 V1* *V1 = –1000 • (OVERDRIVE + VTRIP+) NOTE: RISING EDGE TEST SHOWN. FOR FALLING EDGE, REVERSE LT1719 INPUTS

S and VCC together as well as GND and VEE. EE pin must be equal to or less than ground. false output inversion to at least –400mV common mode. currents will also increase. Figure 1. Variety of Power Supply Conﬁ gurations

1715 F01

Figure 2. Typical Topside Metal for Multilayer PCB Layouts

1715 F02

recovery from this state will take as long as 1μs. receiver , additional external protection may be required. limit the voltage rise caused by an ESD pulse. inputs away from the outputs, shielded by the power rails. should be run between the inputs and the output. and the disturbance down substantially. capacitors in the 0805 case.

plane or power distribution traces. frequency of the high frequency signal. bond inductance, and it cannot be entirely prevented. will effectively minimize it. sive current drain by the L T1715. CC and VEE supplies as the L T1715. Figure 4. 100MHz Jitter with Both Channels DrivenFigure 3. Clean 100MHz Toggling

1715 F03

1715 F04

Figure 6. Additional External Hysteresis easier to use than many other similar speed comparators. dependence of the hysteresis voltage. Figure 6. Resistor R3 adds a portion of the output to the with light loads, and to within 400mV with heavy loads. the internal 4mV hysteresis. Figure 5. Hysteresis I/O Characteristics

1715 F05

plications where Emitter-Coupled Logic (ECL) is deployed. the all-NPNTTL gate with its so-called totem-pole output. facing the L T1715 to ECL running off the same supply rail. forward bias the L T1715’s internal ESD clamp diode. this with the minimum additional power dissipation. additional power dissipation. Figure 7. Model for Additional Hysteresis Calculations

1715 F07

Of course, if the V EE of the L T1715 is the same as the ECL negative supply, the GND pin can be tied to it as well and +V S grounded. Then the output stage has the same powerrails as the ECL and the circuits of Figure 8b can be used. For all the dividers shown, the output impedance is about 110Ω. This makes these fast, less than a nanosecond,with most layouts. Avoid the temptation to use speed up capaci- tors. Not only can they foul up the operation of the ECL gate because of overshoots, they can damage the ECL inputs, particularly during power-up of separate supply conﬁ gurations. The level translator designs assume one gate load. Multiple gates can have signiﬁ cant I IH loading, and the transmis- sion line routing and termination issues also make this case difﬁ cult. APPLICATIONS INFORMATION Figure 8 5V180Ω DO NOT USE FOR LT1715 LEVEL TRANSLATION. SEE TEXT270Ω 820Ω 10KH/E +VS 10KH/E 100K/E +VS 5V OR 5.2V 4.5V 510Ω 620Ω 180Ω 180Ω 750Ω 510Ω (a) STANDARD TTL TO PECL TRANSLATOR (b) LT1715 OUTPUT TO PECL TRANSLATOR LSTTL 1/2 LT1715 VEE VCC VEE VCC VECL R3R4 10KH/E 100K/E VECL 5V OR 5.2V 4.5V 300Ω 330Ω 180Ω 180Ω OMIT 1500Ω (c) 3V LT1715 OUTPUT TO PECL TRANSLATOR 1/2 LT1715 R4 560Ω 1000Ω VECL +VSVCC VEE

1715 F08

–5.2V 560Ω 270Ω +VS 270Ω 510Ω 330Ω 300Ω (d) LT1715 OUTPUT TO STANDARD ECL TRANSLATOR 1/2 LT1715 1200Ω 330Ω 100K/E –4.5V 680Ω 330Ω 270Ω 390Ω 300Ω 270Ω 1500Ω 430Ω

noise margin due to the ±5% resistor selections shown. The block diagram of the L T1715 is shown in Figure 9. utilize low voltage swings for high speed at low power. nected common emitter for rail-to-rail output operation. described earlier , or analog loads. Figure 9. L T1715 Block Diagram

1715 F09

The bias conditions and signal swings in the output stage are designed to turn their respective output transistors off faster than on. This helps minimize the surge of current from +V S to ground that occurs at transitions, to minimize the frequency-dependent increase in power consumption. The frequency dependence of the supply current is shown in the Typical Performance Characteristics. Speed Limits The L T1715 comparator is intended for high speed ap- plications, where it is important to understand a few limitations. These limitations can roughly be divided into three categories: input speed limits, output speed limits, and internal speed limits. There are no signiﬁcant input speed limits except the shunt capacitance of the input nodes. If the 2pF typical input nodes are driven, the L T1715 will respond. The output speed is constrained by three mechanisms, the ﬁ rst of which is the slew currents available from the output transistors. To maintain low power quiescent operation, the L T1715 output transistors are sized to deliver 35mA to 60mA typical slew currents. This is sufﬁcient to drive small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow dramatically with heavy capacitive loads. Because the propagation delay (t PD) deﬁnition ends at the time the output voltage is halfway between the supplies, the ﬁxed slew current makes the L T1715 faster at 3V than 5V with large capacitive loads and sufﬁ cient input overdrive. Another manifestation of this output speed limit is skew, the difference between t PD+ and tPD–. The slew currents of the L T1715 vary with the process variations of the PNP and NPN transistors, for rising edges and falling edges respectively. The typical 0.5ns skew can have either polar- ity, rising edge or falling edge faster . Again, the skew will increase dramatically with heavy capacitive loads. A ﬁ nal limit to output speed is the turn-on and turn-off time of the output devices. Each device has substantial base charge that requires one nanosecond or more of active charging or discharging by the bias current of the Darlington driver stage. When toggle rates are high enough that insufﬁ cient time is allowed for this turn-on or turn-off, glitches may occur leading to dropout or runt pulses. Furthermore, power consumption may increase nonlinearly if devices are not turned off before the oppos- ing cycle. However , once the toggle frequency increases or decreases, the part will easily leave this undesired operating mode no worse for the wear provided there is adequate heat sinking toprevent thermal overload. At frequencies well beyond the maximum toggle rate, the part will toggle with limited output swing and well controlled power consumption. The internal speed limits manifest themselves as disper- sion. All comparators have some degree of dispersion, deﬁned as a change in propagation delay versus input overdrive. The propagation delay of the L T1715 will vary with overdrive, from a typical of 4ns at 20mV overdrive to 6ns at 5mV overdrive (typical). The L T1715’s primary source of dispersion is the hysteresis stage. As a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive avail- able. Only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis path and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. The L T1715 is several hundred picoseconds faster when V EE = –5V , relative to single supply operation. This is due to the internal speed limit; the gain stage operates between V EE and +VS, and it is faster with higher reverse voltage bias due to reduced silicon junction capacitances. In many applications, as shown in the following examples, there is plenty of input overdrive. Even in applications pro- viding low levels of overdrive, the L T1715 is fast enough that the absolute dispersion of 2ns (= 6 – 4) is often small enough to ignore.

The gain and hysteresis stage of the L T1715 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. This internal “self-latch” can be usefully exploited in many applications because it occurs early in the signal chain, in a low power , fully differential stage. It is therefore highly immune to disturbances from other parts of the circuit, such as the output, or on the supply lines. Once a high speed signal trips the hysteresis, the output will respond, after some propagation delay, without regard to these external inﬂuences that can cause trouble in nonhysteretic comparators. TRIP Test Circuit The input trip points test circuit uses a 1kHz triangle wave to repeatedly trip the comparator being tested. The L T1715 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. Because the triangle wave is attenuated 1000:1 and fed to the L T1715’s differential input, the sampled voltages are therefore 1000 times the input trip voltages. The hysteresis and offset are computed from the trip points as shown.

–IN +IN VEE 1715 SS OUTPUT +VS GND VCC 150Ω 150Ω

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 10-Lead Plastic MSOP (Reference L TC DWG # 05-08-1661) PACKAGE DESCRIPTION MSOP (MS) 0307 REV E 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8910 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6 ° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2001 LT 1008 REV A • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS L T1016 UltraFast Precision Comparator Industry Standard 10ns Comparator L T1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of L T1016 L T1394 7ns, UltraFast, Single Supply Comparator 6mA Single Supply Comparator L T1711/L T1712 4.5ns, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators UltraFast Rail-to-Rail Input and Output Comparator L T1713/L T1714 7ns, Low Power , 3V/5V/±5V Single/Dual Rail-to-Rail Comparators Rail-to-Rail Input and Output Comparator L T1719 4.5ns Single Supply 3V/5V Comparator Single Comparator Similar to the L T1715 L T1720/L T1721 Dual/Quad 4.5ns, Single Supply 3V/5V Comparator Dual/Quad Comparator Similar to the L T1715 High Performance Sine Wave to Square Wave Converter Propagation delay of comparators is typically speciﬁ ed fora 100mV step with some fraction of that for overdrive. But in many signal processing applications, such as in com- munications, the goal is to convert a sine wave, such as a carrier , to a square wave for use as a timing clock. The desired behavior is for the output timing to be dependent on the input timing only. No phase shift should occur as a function of the input amplitude, which would result in AM to FM conversion. The circuit of Figure 12a is a simple L T1715-based sine wave to square wave converter . The ±5V supplies on the input allow very large swing inputs, while the 3V logic supply keeps the output swing small to minimize crosstalk. Figure 12b shows the time delay vs input amplitude with a 10MHz sine wave. The L T1715 delay changes just 0.65ns over the 26dB amplitude range; 2.33° at 10MHz. The delay is particularly ﬂ at yielding excellent AM rejection from 0dBm to 15dBm. If a 2:1 transformer is used to drive the input differentially, this exceptionally ﬂ at zone spans –5dBm to 10dBm, a common range for RF signal levels. Similar delay performance is achieved with input fre- quencies as high as 50MHz. There is, however, some additional encroachment into the central ﬂ at zone by both the small amplitude and large amplitude variations. With small input signals, the hysteresis and dispersion make the L T1715 act like a comparator with a 12mV hysteresis span. In other words, a 12mV P-P sine wave at 10MHz will barely toggle the L T1715, with 90° of phase lagor 25ns additional delay. Above 5V P-P at 10MHz, the L T1715 delay starts to decrease due to internal capacitive feed-forward in the input stage. Unlike some comparators, the L T1715 will not falsely an- ticipate a change in input polarity, but the feed-forward is enough to make a transition propagate through the L T1715 faster once the input polarity does change. Figure 12a. L T1715-Based Sine Wave to Square Wave Converter Figure 12b. Time Delay vs Sine Wave Input Amplitude 1/2 LT171550Ω

1715 F12a

–5V INPUT AMPLITUDE (dBm) TIME DELAY (ns) 0 51 0 1 5

1715 F12b

632mVP-P 2VP-P 6.32VP-P 25°C VCC = 5V VEE = –5V +VS = 3V 10MHz

Selected Specification

Linear Technology LTVV overview.

Summary

4ns, 150MHz Dual Comparator with Independent Input/Output Supplies

Description

4ns, 150MHz Dual Comparator with Independent Input/Output Supplies

Source title LTVV Datasheet(PDF) - Linear Technology

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