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LTC2421 LINER

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 32

Technical content

1-/2-Channel 20-Bit mPower No Latency DS TM ADCs in MSOP-10 n Weight Scales n Direct Temperature Measurement n Gas Analyzers n Strain Gauge Transducers n Instrumentation n Data Acquisition n Industrial Process Control No Latency DS is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. Pseudo Differential Bridge Digitizer , LTC and LT are registered trademarks of Linear Technology Corporation. The LTC 2421/LTC2422 are 1- and 2-channel 2.7V to 5.5V micropower 20-bit analog-to-digital converters with an integrated oscillator, 8ppm INL and 1.2ppm RMS noise. These ultrasmall devices use delta-sigma technology and a new digital filter architecture that settles in a single cycle. This eliminates the latency found in conventional DS converters and simplifies multiplexed applications. Through a single pin, the LTC2421/LTC2422 can be configured for better than 110dB rejection at 50Hz or 60Hz – 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. The internal oscillator requires no external fre- quency setting components. These converters accept an external reference voltage from 0.1V to V CC. With an extended input conversion range of –12.5% V REF to 112.5% V REF (VREF = FSSET – ZSSET), the LTC2421/LTC2422 smoothly resolve the off- set and overrange problems of preceding sensors or signal conditioning circuits. The LTC2421/LTC2422 communicate through a 2- or 3-wire digital interface that is compatible with SPI and MICROWIRE TM protocols. n 20-Bit ADCs in Tiny MSOP-10 Packages n 1- or 2-Channel Inputs n Single Supply 2.7V to 5.5V Operation n Low Supply Current (200mA) and Auto Shutdown n Automatic Channel Selection (Ping-Pong) (LTC2422) n No Latency: Digital Filter Settles in a Single Conversion Cycle n 8ppm INL, No Missing Codes n 4ppm Full-Scale Error n 0.5ppm Offset n 1.2ppm Noise n Zero Scale and Full Scale Set for Reference and Ground Sensing n Internal Oscillator—No External Components Required n 110dB Min, 50Hz/60Hz Notch Filter n Reference Input Voltage: 0.1V to VCC n Live Zero—Extended Input Range Accommodates 12.5% Overrange and Underrange n Pin Compatible with LTC2401/LTC2402 ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.12VREF (VREF = FSSET – ZSSET) VCC FO FSSET ZSSET SCK CH1 SDO GND CS REFERENCE VOLTAGE ZSSET + 0.1V TO VCC 0V TO FSSET – 100mV CH0 = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 3-WIRE SPI INTERFACE 1µF 11 0 2.7V TO 5.5V LTC2422

24212 TA01

2.7V TO 5.5V 24012TA02 DESCRIPTIO UFEATURES APPLICATIO SU TYPICAL APPLICATIO U

(Notes 1, 2) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) TJMAX = 125°C, qJA = 130°C/W LTC2421CMS LTC2421IMS ABSOLUTE MAXIMUM RATINGSW WW U PACKAGE/ORDER INFORMATIONUU W V CC FSSET CH1 CH0 ZSSET F O SCK SDO CS GND TOP VIEW MS10 PACKAGE 10-LEAD PLASTIC MSOP Operating Temperature Range ORDER PART NUMBER MS10 PART MARKING LTC2422CMS LTC2422IMS LTUZ LTVA MS10 PART MARKING LTUX LTUY TJMAX = 125°C, qJA = 130°C/W PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution l 20 Bits No Missing Codes Resolution 0.1V £ FSSET £ VCC, ZSSET = 0V (Note 5) l 20 Bits Integral Nonlinearity FS SET = 2.5V, ZSSET = 0V (Note 6) l 4 10 ppm of V REF FSSET = 5V, ZSSET = 0V (Note 6) l 8 20 ppm of V REF Offset Error 2.5V £ FSSET £ VCC, ZSSET = 0V l 0.5 10 ppm of V REF Offset Error Drift 2.5V £ FSSET £ VCC, ZSSET = 0V 0.04 ppm of V REF/°C Full-Scale Error 2.5V £ FSSET £ VCC, ZSSET = 0V l 4 10 ppm of V REF Full-Scale Error Drift 2.5V £ FSSET £ VCC, ZSSET = 0V 0.04 ppm of V REF/°C Total Unadjusted Error FS SET = 2.5V, ZSSET = 0V 8 ppm of V REF FSSET = 5V, ZSSET = 0V 16 ppm of V REF Output Noise V IN = 0V (Note 13) 6 mVRMS Normal Mode Rejection 60Hz –2% (Note 7) l 110 130 dB Normal Mode Rejection 50Hz –2% (Note 8) l 110 130 dB Power Supply Rejection, DC FS SET = 2.5V, ZSSET = 0V, VIN = 0V 100 dB Power Supply Rejection, 60Hz –2% FS SET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 7, 15) 110 dB Power Supply Rejection, 50Hz –2% FS SET = 2.5V, ZSSET = 0V, VIN = 0V, (Notes 8, 15) 110 dB The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Notes 3, 4) CONVERTER CHARACTERISTICSU V CC FSSET VIN NC ZSSET TOP VIEW MS10 PACKAGE 10-LEAD PLASTIC MSOP FO SCK SDO CS GND Consult factory for parts specified with wider operating temperature ranges.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage 2.7V £ VCC £ 5.5V l 2.5 V CS, FO 2.7V £ VCC £ 3.3V 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V l 0.8 V CS, FO 2.7V £ VCC £ 5.5V 0.6 V VIH High Level Input Voltage 2.7V £ VCC £ 5.5V (Note 9) l 2.5 V SCK 2.7V £ VCC £ 3.3V (Note 9) 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V (Note 9) l 0.8 V SCK 2.7V £ VCC £ 5.5V (Note 9) 0.6 V IIN Digital Input Current 0V £ VIN £ VCC l –10 10 mA CS, FO IIN Digital Input Current 0V £ VIN £ VCC (Note 9) l –10 10 mA SCK CIN Digital Input Capacitance 10 pF CS, FO CIN Digital Input Capacitance (Note 9) 10 pF SCK VOH High Level Output Voltage I O = –800 mA l VCC – 0.5 V SDO VOL Low Level Output Voltage I O = 1.6mA l 0.4 V SDO VOH High Level Output Voltage I O = –800 mA (Note 10) l VCC – 0.5 V SCK VOL Low Level Output Voltage I O = 1.6mA (Note 10) l 0.4 V SCK IOZ High-Z Output Leakage l –10 10 mA SDO DIGITAL I PUTS A D DIGITAL OUTPUTSU U SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage l 2.7 5.5 V ICC Supply Current Conversion Mode CS = 0V (Note 12) l 200 300 mA Sleep Mode CS = V CC (Note 12) l 20 30 mA POWER REQUIRE E TSW U The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range (Note 14) l ZSSET – 0.12VREF FSSET + 0.12VREF V FSSET Full-Scale Set Range l 0.1 + ZSSET VCC V ZSSET Zero-Scale Set Range l 0F S SET – 0.1 V CS(IN) Input Sampling Capacitance 1 pF CS(REF) Reference Sampling Capacitance 1.5 pF IIN(LEAK) Input Leakage Current CS = V CC l –100 1 100 nA IREF(LEAK) Reference Leakage Current V REF = 2.5V, CS = VCC l –100 1 100 nA The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Note 3) A ALOG I PUT A D REFERE CEU U U U

The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) fEOSC External Oscillator Frequency Range l 2.56 307.2 kHz tHEO External Oscillator High Period l 0.5 390 ms tLEO External Oscillator Low Period l 0.5 390 ms tCONV Conversion Time F O = 0V l 130.86 133.53 136.20 ms FO = VCC l 157.03 160.23 163.44 ms External Oscillator (Note 11) l 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz External Oscillator (Notes 10, 11) f EOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) 45 55 % fESCK External SCK Frequency Range (Note 9) l 2000 kHz tLESCK External SCK Low Period (Note 9) l 250 ns tHESCK External SCK High Period (Note 9) l 250 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 1.23 1.25 1.28 ms External Oscillator (Notes 10, 11) l 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Note 9) l 24/fESCK (in kHz) ms t1 CS ﬂ to SDO Low Z l 0 150 ns t2 CS › to SDO High Z l 0 150 ns t3 CS ﬂ to SCK ﬂ (Note 10) l 0 150 ns t4 CS ﬂ to SCK › (Note 9) l 50 ns tKQMAX SCK ﬂ to SDO Valid l 200 ns tKQMIN SDO Hold After SCK ﬂ (Note 5) l 15 ns t5 SCK Set-Up Before CS ﬂ l 50 ns t6 SCK Hold After CS ﬂ l 50 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Input source resistance = 0W . Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz – 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz –2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance C LOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: VREF = FSSET – ZSSET. The minimum input voltage is limited to – 0.3V and the maximum to VCC + 0.3V. Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P. TI I G CHARACTERISTICSUW

TYPICAL PERFOR A CE CHARACTERISTICS UW Total Unadjusted Error (3V Supply) INL (3V Supply) Negative Extended Input Range Total Unadjusted Error (3V Supply) Positive Extended Input Range Total Unadjusted Error (3V Supply) Total Unadjusted Error (5V Supply) INL (5V Supply) Negative Extended Input Range Total Unadjusted Error (5V Supply) Offset Error vs Reference Voltage Positive Extended Input Range Total Unadjusted Error (5V Supply) INPUT VOLTAGE (V) ERROR (ppm) 2.0

24212 G01

–10 0.5 1.0 1.5 2.5 VCC = 3V VREF = 2.5V INPUT VOLTAGE (V) ERROR (ppm) 2.0

24212 G02

–10 0.5 1.0 1.5 2.5 VCC = 3V VREF = 2.5V INPUT VOLTAGE (V) –10

24212 G03

–0.25 –0.30 ERROR (ppm) VCC = 3V VREF = 2.5V TA = 90°C TA = 25°C TA = –45°C TA = –55°C INPUT VOLTAGE (V) 2.50 –10 2.55 2.60 2.65 2.70

24212 G04

2.75 2.80 ERROR (ppm) VCC = 3V VREF = 2.5V INPUT VOLTAGE (V) ERROR (ppm)

24212 G05

–10 1 2 3 5 VCC = 5V VREF = 5V INPUT VOLTAGE (V) ERROR (ppm)

24212 G06

–10 1 2 3 5 VCC = 5V VREF = 5V INPUT VOLTAGE (V) –10

24212 G07

–0.25 –0.30 ERROR (ppm) VCC = 5V VREF = 5V TA = 90°C TA = 25°C TA = –55°C TA = –45°C INPUT VOLTAGE (V) 5.00 –10 5.05 5.10 5.15 5.20

24212 G08

5.25 5.30 ERROR (ppm) VCC = 5V VREF = 5V TA = –45°C TA = –55°C TA = 25°CTA = 90°C REFERENCE VOLTAGE (V) OFFSET ERROR (ppm) 120 150

24212 G09

VCC = 5V TA = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS UW RMS Noise vs Reference Voltage Offset Error vs V CC RMS Noise vs VCC Noise Histogram RMS Noise vs Code Out Offset Error vs Temperature Full-Scale Error vs Temperature Full-Scale Error vs Reference Voltage Full-Scale Error vs V CC REFERENCE VOLTAGE (V) RMS NOISE (ppm OF VREF) 1234

24212 G10

VCC = 5V TA = 25°C VCC (V) 2.7 –10 OFFSET ERROR (ppm)–5 3.2 3.7 4.2 4.7

24212 G11

5.2 5.5 VREF = 2.5V TA = 25°C VCC (V) 2.7 RMS NOISE (ppm) 2.5 5.0 7.5 10.0 3.2 3.7 4.2 4.7

24212 G12

5.2 5.5 VREF = 2.5V TA = 25°C OUTPUT CODE (ppm) 100 150 200 250 300 350

24212 G13

–2 0 4 NUMBER OF READINGS VCC = 5 VREF = 5 VIN = 0 CODE OUT (HEX) 0 7FFFF FFFFF RMS NOISE (ppm) 1.25 2.50 3.75 5.00

24212 G14

VCC = 5V VREF = 5V VIN = 0.3V TO 5.3V TA = 25°C TEMPERATURE (°C) –55 –10 OFFSET ERROR (ppm)–5 –30 –5 20 45

24212 G15

VCC = 5V VREF = 5V VIN = 0V TEMPERATURE (°C) –55 –10 FULL-SCALE ERROR (ppm)–5 –30 –5 20 45

24212 G16

VCC = 5V VREF = 5V VIN = 5V REFERENCE VOLTAGE (V) –150 FULL-SCALE ERROR (ppm) –125 –100 –75 –50 –25 1234

24212 G17

VCC = 5V VIN = VREF VCC (V) 2.7 –10 FULL-SCALE ERROR (ppm)–5 3.2 3.7 4.2 4.7

24212 G18

5.2 5.5 VREF = 2.5V VIN = 2.5V TA = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS UW Conversion Current vs Temperature Sleep Current vs Temperature Rejection vs Frequency at VIN Rejection vs Frequency at VIN Rejection vs Frequency at VINRejection vs Frequency at VIN Rejection vs Frequency at VCC Rejection vs Frequency at VCC Rejection vs Frequency at VCC TEMPERATURE (°C) –5 5 SUPPLY CURRENT (µA) 220

24212 G19

–30 –5 45 160 150 230 210 200 180 70 95 120 VCC = 5.5V VCC = 4.1V VCC = 2.7V TEMPERATURE (°C) –55 SUPPLY CURRENT (mA) –30 –5 20 45

24212 G20

VCC = 2.7V VCC = 5V FREQUENCY AT VCC (Hz) REJECTION (dB) –60 –40 –20 200

24212 G21

–80 –100 –120 50 100 150 250 VCC = 4.1V VIN = 0V TA = 25°C FO = 0 FREQUENCY AT VCC (Hz) 15200 –120 REJECTION (dB) –100 –80 –60 –40 15250 15300 15350 15400

24212 G22

–20 VCC = 4.1V VIN = 0V TA = 25°C FO = 0 FREQUENCY AT VCC (Hz) –120 REJECTION (dB) –100 –80 –60 –40 –20 100 10k 1M

24212 G23

VCC = 4.1V VIN = 0V TA = 25°C FO = 0 FREQUENCY AT VIN (Hz) –120 REJECTION (dB) –100 –80 –60 –40 –20 50 100 150 200

24212 G24

VCC = 5V VREF = 5V VIN = 2.5V FO = 0 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) – 1 2 – 8 – 4 048 1 2 REJECTION (dB)

24212 G25

–60 –70 –80 –90 –100 –110 –120 –130 –140 FREQUENCY AT VIN (Hz) 15100 –120 REJECTION (dB) –100 –80 –60 –40 –20 15200 15300 15400 15500

24212 G26

VCC = 5V VREF = 5V VIN = 2.5V FO = 0 SAMPLE RATE = 15.36kHz – 2% INPUT FREQUENCY –60 –40

24212 G27

–80 –100 fS/2 f S –120 –140 –20REJECTION (dB)

TYPICAL PERFOR A CE CHARACTERISTICS UW PIN FUNCTIONSUU U VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin␣ 6) with a 10mF tantalum capacitor in parallel with 0.1mF ceramic capacitor as close to the part as possible. FSSET (Pin 2): Full-Scale Set Input. This pin defines the full-scale input value. When VIN = FSSET, the ADC outputs full scale (FFFFF H). The total reference voltage is FSSET – ZSSET. CH0, CH1 (Pins 4, 3): Analog Input Channels. The input voltage range is – 0.125 • V REF to 1.125 • V REF. For VREF > 2.5V, the input voltage range may be limited by the absolute maximum rating of – 0.3V to VCC + 0.3V. Conver- sions are performed alternately between CH0 and CH1 for the LTC2422. Pin 4 is a No Connect (NC) on the LTC2421. ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the zero-scale input value. When V IN = ZS SET, the ADC outputs zero scale (00000H). GND (Pin 6): Ground. Shared pin for analog ground, digital ground, reference ground and signal ground. Should be connected directly to a ground plane through a mini- mum length trace or it should be the single-point-ground in a single-point grounding system. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A LOW-to-HIGH transition on this pin disables the SDO digital output. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the data output period, this pin is used for serial data output. When the chip select CS is HIGH (CS = V CC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status out- put. The conversion status can be observed by pulling CS LOW. INL vs Output Rate Resolution vs Output Rate OUTPUT RATE (Hz) TUE RESOLUTION (BITS)

24212 G28

10 20 30 50 60 70 80 90 100 VCC = 5V VREF = 5V FO = EXTERNAL TA = –45°C TA = 25°C TA = 90°C OUTPUT RATE (Hz) TUE RESOLUTION (BITS)

24212 G29

10 20 30 50 60 70 80 90 100 VCC = 3V VREF = 2.5V FO = EXTERNAL TA = –45°C TA = 25°C TA = 90°C OUTPUT RATE (Hz) 0 7.5 EFFECTIVE RESOLUTION (BITS)

24212 G30

TA = 25°C TA = 90°C TA = –45°C VCC = 5V VREF = 5V fO = EXTERNAL STANDARD DEVIATION OF 100 SAMPLES INL vs Output Rate

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In the External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. An internal pull-up current source is automatically activated in Internal Serial Clock Operation mode. The Serial Clock mode is determined by the level applied to SCK at power up and the falling edge of CS. F O (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter’s first null is located at 50Hz. When the F O pin is connected to GND (FO = 0V), the converter uses its internal oscillator and the digital filter’s first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560. FUNCTIONAL BLOCK DIAGRA UU W TEST CIRCUITS 3.4k SDO

24212 TC01

CLOAD = 20pF 3.4k SDO

24212 TC02

CLOAD = 20pF VCC AUTOCALIBRATION AND CONTROL DAC DECIMATING FIR INTERNAL OSCILLATOR SERIAL INTERFACEADC∑ ∫∫∫ GND VCC VIN SDO SCK VREF CS FO (INT/EXT) 24212 FD

which are always logic HIGH. ter while the converter is in the sleep state. Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402

4 STATUS BITS 20 DATA BITS

24212 F01

24212 F02

1 CS AND

Figure 2. LTC2421/LTC2422 State Transition Diagram initiates a new conversion and the cycle repeats. Interface Timing Modes section.

multiplexing an analog input voltage is easy. rate within the specifications of the device. the input leakage current increase rapidly. Figure 3. LTC2421/LTC2422 Input Range

24212 F03

Figure 4. Output Data Timing state. The next 20 bits are the conversion result, MSB first. conversion and sleep states whenever the CS pin is LOW. when the conversion is complete. CH1. This bit is always LOW for the LTC2421. bit is LOW. The sign bit changes state during the zero code. normal input range, VIN > VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1. Table 1. LTC2421/LTC2422 Status Bits Bit 19 (fifth output bit) is the most significant bit (MSB). Bits 19-0 are the 20-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). ignored by the internal data out shift register.

24212 F04

to the value corresponding to – 0.125 • VREF. conversions will not be affected. LTC2422 can operate with an external conversion clock. be at least 2560Hz (1Hz notch frequency) to be detected. Table 2. LTC2421/LTC2422 Output Data Format *Bit 22 is always 0 for the LTC2421 **The sign bit changes state during the 0 code.

data stream will remain valid. the SDO pin on the falling edge of the serial clock. Table 3. LTC2421/LTC2422 State Duration Figure 5. LTC2421/LTC2422 Normal Mode Rejection When

24212 F05

state, the device is in a LOW power state if CS is HIGH. described in the previous sections. (i.e., after the first rising edge of SCK occurs with CS = 0). of operation, see Serial Interface Timing Modes section. the FO pin. Refer to Table 4 for a summary. trol the state of the conversion cycle, see Figure 6. The serial clock mode is selected on the falling edge of CS. (SCK) must be LOW during each CS falling edge. pulled LOW in order to monitor the state of the converter. order of magnitude if CS is HIGH. conversion result is held in an internal static shift register. (EOC = 1) indicating a conversion is in progress. Table 4. LTC2421/LTC2422 Interface Timing Modes

and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. order to monitor the conversion status. Typically, CS remains LOW during the data output state. Figure 6. External Serial Clock, Single Cycle Operation

24212 F06

Figure 7. External Serial Clock, Reduced Data Output Length

24212 F07

user interface or isolation barrier. in order to enter the external serial clock timing mode. trol the state of the conversion cycle, see Figure 9. matically selected if SCK is not externally driven. pulled LOW in order to monitor the state of the converter. and EOC = 0 if the device is in the sleep state. Figure 8. External Serial Clock, CS = 0 Operation

24212 F08

HIGH, and a new conversion starts. Typically, CS remains LOW during the data output state. the SCK pin or by never pulling CS HIGH when SCK is LOW. nally driven if the device is in the internal SCK timing mode. the internal SCK timing mode. Figure 9. Internal Serial Clock, Single Cycle Operation

24212 F09

EOCtest), the internal pull-up is activated. external 10k pull-up resistor to the SCK pin. Figure 11. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier. ternal SCK mode will be selected). remains HIGH during the conversion. Figure 10. Internal Serial Clock, Reduced Data Output Length

24212 F10

2-wire I/O described above with one additional feature. pacitor and properly cleaning the PCB surface. SCK LOW while CS is discharging. The LTC2421/LTC2422’s digital interface is easy to use. Figure 11. Internal Serial Clock, Continuous Operation

24212 F11

Figure 12. Internal Serial Clock, Autostart Operation

2420 F12

Figure 13. CS Capacitance vs tSAMPLE Figure 14. CS Capacitance

24212 F13

24212 F15

not generally active during the conversion state. Figure 15. CS Capacitance

resistance ground plane through a minimum length trace. reduce the connection resistance. propagation delay from the driver to LTC2421/LTC2422. impedance and connection topology. at 153,600Hz corresponding to a 6.5ms sampling period. is switched in order to achieve 1ppm settling accuracy. Figure 16. LTC2421/LTC2422 Equivalent Analog Input Circuit

24212 F16

tance at VIN (CIN < 0.01mF). IN (VIN = 0V and VIN = VREF, when VREF = 5V). readings for every 10W of input source resistance. Figure 18. An RC Network at VIN Figure 19. Offset vs RSOURCE (Small C) Figure 17. Offset/Full-Scale Shift

24212 F17

24212 F19

Figure 20. Offset vs RSOURCE (Large C) Figure 21. Full-Scale Error vs RSOURCE (Large C)

24212 F20

24212 F21

at VREF) may be tolerated, see Figure 24.

24212 F22

Figure 22. Full-Scale Error vs RSOURCE (Small C) Figure 23. Full-Scale Error vs RVREF (Large C) Figure 24. Full-Scale Error vs RVREF (Small C)

24212 F23

24212 F24

Figure 25. INL Error vs RVREF (Small C)

24212 F25

Figure 26. INL Error vs RVREF (Large C)

24212 F26

cantly simplify antialiasing filter requirements. width of the frequencies rejected. minimize the effects of input dynamic current. Figure 27. Sinc4 Filter Rejection

24212 F27

24212 F28

148 GOSUB 2200: v31 = v31 + 1

150 IF bita% = 31 THEN GOTO 152 ELSE 156

152 IF dfrm% = c0% THEN GOTO 156

155 IF v31 > 2 THEN LOCATE 16, 16: OUT port, c0%: PRINT "waiting for eoc":

156 LOCATE 16, 16: PRINT" ": GOSUB 2000

161 IF dfrm% = c1% THEN chan% = c1%: ch1% = c0%

171 IF bita% = 29 THEN IF dfrm% = c0% THEN signneg% = c1%: ' NEG

1600 PPM = (d2400 / km) * kn: rw% = 6: hz% = (chan% * 20) + 1

1700 IF d2400 <> c0% THEN PPM = (PPM - 2000000)

1705 LOCATE rw%, hz%: PRINT PPM; " "; : LOCATE rw%, hz% + 11:

1800 LOOP WHILE INKEY$ = "": REM Works with "DO"

2040 IF x3% = c16% THEN dfrm% = c1% ELSE dfrm% = c0%

3700 FOR n = 6 TO 9: LOCATE n, 20

Figure 29. The voltage drop across these parasitic resis- tors leads to systematic offset and full-scale errors.

directly digitize the output of the bridge sensor. Figure 31. Transfer Curve with Zero-Scale and Full-Scale Set Figure 30. Half-Bridge Digitizer with Figure 29. Errors Due to Excitation Currents

24212 F29

Figure 32. Isolated Temperature Measurement

24212 F32

was performed on CH1 (see Figure 33). LTC2422 only requires two digital signals (SCK and SDO). differential conversion using the LTC2422. Figure 33. Embedded Selected Channel Indicator

24212 F33

Figure 34. Pseudo Differential Strain Guage Application

root of 2, independent of the common mode input voltage. have long lead lengths between the ADC and RTD sensor. be measured and removed from the conversion result. then removed with simple digital correction. driving bridge circuits and for ratiometric applications. VCC2 to reach its undervoltage lockout threshold of 4.2V. Figure 35. RTD Remote Temperature Measurement

24212 F35

24212 F36

Figure 36. Complete, Isolated 20-Bit Data Acquisition System output has reached 5V, is approximately 1ms. without the need for any external components.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) MSOP (MS) 1001 0.53 – 0.01 (.021 – .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) 0.13 – 0.05 (.005 – .002) 0.86 (.034) REF 0.50 (.0197) TYP 12 3 45 4.88 – 0.10 (.192 – .004) 0.497 – 0.076 (.0196 – .003) REF8910 7 6 3.00 – 0.102 (.118 – .004) (NOTE 3) 3.00 – 0.102 (.118 – .004) NOTE 4 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.889 – 0.127 (.035 – .005) RECOMMENDED SOLDER PAD LAYOUT 3.05 – 0.38 (.0120 – .0015) TYP 0.50 (.0197) BSC

clocking out data and beginning the next conversion.

24212 F37

Figure 37. Mulitchannel Isolated Temperature Measurement System

Selected Specification

Linear Technology LTVA overview.

Summary

1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10

Description

1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10

Source title LTVA Datasheet(PDF) - Linear Technology

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