LTM9008-14 LINER
Document overview
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Technical content
FEATURES
APPLICATIONS
DESCRIPTION
14-Bit, 65Msps/40Msps/ 25Msps Low Power Octal ADCs LTM9008-14, 65Msps, 2-Tone FFT, fIN = 70MHz and 75MHz The LT M®9008-14/LTM9007-14/LTM9006-14 are 8-chan- nel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73dB SNR and 90dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flowthrough pinout reduces overall board space requirements. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The ENC + and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 8-Channel Simultaneous Sampling ADC n 73dB SNR n 90dB SFDR n Low Power: 88mW/59mW/46mW per Channel n Single 1.8V Supply n Serial LVDS Outputs: 1 or 2 Bits per Channel n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n Internal Bypass Capacitance, No External Components n 140-Pin (11.25mm × 9mm) BGA Package n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition n Nondestructive Testing L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. DATA SERIALIZER ENCODE INPUT SERIALIZED LVDS OUTPUTS 1.8V VDD 1.8V OVDD OUT1A OUT1B OUT2A OUT2B OUT8A OUT8B DATA CLOCK OUT FRAME GNDGND
90067814 TA01
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- • • FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 10 20 30
90067814 TA01b
(Notes 1, 2) PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM9008CY-14#PBF LTM9008CY-14#PBF LTM9008Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9008IY-14#PBF LTM9008IY-14#PBF LTM9008Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9007CY-14#PBF LTM9007CY-14#PBF LTM9007Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9007IY-14#PBF LTM9007IY-14#PBF LTM9007Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9006CY-14#PBF LTM9006CY-14#PBF LTM9006Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9006IY-14#PBF LTM9006IY-14#PBF LTM9006Y14 140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ Supply Voltages Analog Input Voltage (AIN+, AIN–, Digital Input Voltage (ENC+, ENC–, CS, Operating Temperature Range P C D E F G H J K L M N A B 10 9 8 7 6 5 4 3 2 BGA PACKAGE 140-LEAD (11.25mm × 9.00mm × 2.72mm) TOP VIEW TJMAX = 150°C, θJA = 30°C/W, θJC = 25°C/W, θJB = 15°C/W, θJCbottom = 12°C/W
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS LTM9008-14 LTM9007-14 LTM9006-14 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX Resolution (No Missing Codes) l 14 14 14 Bits Offset Error (Note 7) l –12 ±3 12 –12 ±3 12 –12 ±3 12 mV Gain Error Internal Reference External Reference l –2.5 –1.3 –1.3 0.5 –2.5 –1.3 –1.3 0.5 –2.6 –1.3 –1.3 0.5 %FS %FS Offset Drift ±20 ±20 ±20 µV/°C Full-Scale Drift Internal Reference External Reference ±35 ±25 ±35 ±25 ±35 ±25 ppm/°C ppm/°C Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS Offset Matching ±3 ±3 ±3 mV T ransition Noise External Reference 1.2 1.2 1.2 LSB RMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l 1 to 2 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 65Msps Per Pin, 40Msps Per Pin, 25Msps µA µA µA I IN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 µA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS LTM9008-14 LTM9007-14 LTM9006-14 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX SNR Signal-to-Noise Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 71.8 73.7 73.7 73.5 69.6 73.5 73.4 73.4 72.8 69.6 72.9 72.9 72.8 72.3 dBFS dBFS dBFS dBFS SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 76.8 76.8 dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS dBFS S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 73.6 73.5 73.2 72.5 69.5 73.3 73.2 73.1 72.3 69.5 72.8 72.7 72.5 71.9 dBFS dBFS dBFS dBFS Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V VCM Output Temperature Drift ±25 ppm/°C VCM Output Resistance –600µA < IOUT < 1mA 4 Ω VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V VREF Output Temperature Drift ±25 ppm/°C VREF Output Resistance –400µA < IOUT < 1mA 7 Ω VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.2 1.6 V V V IN Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V RIN Input Resistance (See Figure 10) 10 kΩ CIN Input Capacitance 3.5 pF Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD = 1.8V 1.26 V VIL Low Level Input Voltage VDD = 1.8V 0.54 V VIN Input Voltage Range ENC+ to GND 0 to 3.6 V RIN Input Resistance (See Figure 11) 30 kΩ CIN Input Capacitance 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance 3 pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used) R OL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance 3 pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 V V R TERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTM9008-14 LTM9007-14 LTM9006-14 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX IVDD Analog Supply Current Sine Wave Input l 357 400 232 275 175 250 mA IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 104 102 100 mA mA mA mA P DISS Power Dissipation 1-Lane Mode, 1.75mA Mode 1-Lane Mode, 3.5mA Mode 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 700 751 733 812 824 907 475 522 504 583 592 679 369 416 401 477 547 630 mW mW mW mW P SLEEP Sleep Mode Power 2 2 2 mW PNAP Nap Mode Power 170 170 170 mW PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled (No Decrease for Sleep Mode) 40 40 40 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTM9008-14 LTM9007-14 LTM9006-14 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Notes 10,11) l 5 65 5 40 5 25 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 7.69 7.69 100 100 11.88 12.5 12.5 100 100 100 100 ns ns t ENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 7.69 7.69 100 100 11.88 12.5 12.5 100 100 100 100 ns ns t AP Sample-and-Hold Acquisition Delay Time 0 0 0 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization 1/(8 • f 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) s s s s s s t FRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8) tSCK SCK Period Write Mode Read Back Mode, CSDO = 20pF, RPULLUP = 2k l l 250 ns ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTM9008), 40MHz (LTM9007), or 25MHz (LTM9006), 2-lane output mode, differential ENC+/ ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: V DD = OVDD = 1.8V, fSAMPLE = 65MHz (LTM9008), 40MHz (LTM9007), or 25MHz (LTM9006), 2-lane output mode, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire device, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Ch.2 to Ch.8.
2-Lane Output Mode, 14-Bit Serialization TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 *SEE THE DIGITAL OUTPUTS SECTION SAMPLE N-5 SAMPLE N-4 N+1 N
90067814 TD01
D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A– OUT#A+ FR– FR+ D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8OUT#B– OUT#B+ ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 N+1 N+2N
90067814 TD02
D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A– OUT#A+ FR– FR+ D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8OUT#B– OUT#B+ NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–
2-Lane Output Mode, 12-Bit Serialization 1-Lane Output Mode, 16-Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N
90067814 TD03
D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 OUT#A– OUT#A+ FR+ FR– D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8OUT#B– OUT#B+ ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER
90067814 TD04
D1 D0 0 0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 14-Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER
90067814 TD06
D3 D2 D1 D0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER
90067814 TD07
D5 D4 D3 D2 D13 D12 D11 D10 D12 D11D9 D8 D7 D6 D5 D4 D3 D2 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED tS tDS A5 A4 A3 A2 A1 A0 XX D7 D6 D5 D4 D3 D2 D1 D0 XX XX XX XX XX XX XX CS SCK SDI R/W SDO HIGH IMPEDANCE SPI Port Timing (Readback Mode) SPI Port Timing (Write Mode) tDH tDO tSCK tH A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
90067814 TD08
TYPICAL PERFORMANCE CHARACTERISTICS LTM9008-14: Integral Nonlinearity (INL) vs Output Code LTM9008-14: Differential Nonlinearity (DNL) vs Output Code LTM9008-14: 64k Point FFT, f IN = 5MHz, –1dBFS, SENSE = VDD LTM9008-14: 64k Point FFT, fIN = 30MHz, –1dBFS, SENSE = VDD LTM9008-14: 64k Point FFT, fIN = 70MHz, –1dBFS, SENSE = VDD LTM9008-14: 64k Point 2-Tone FFT, fIN = 28.5MHz and fIN = 31.5MHz, –7dBFS per Tone, SENSE = VDD LTM9008-14: Shorted Input Histogram OUTPUT CODE INL ERROR (LSB) 1.0 16384
90067814 G01
–1.0 –2.0 4096 8192 12288 2.0 –0.5 0.5 –1.5 1.5 OUTPUT CODE –0.5 DNL ERROR (LSB) –0.4 –0.2 –0.1 0.5 0.2 4096 8192
90067814 G02
–0.3 0.3 0.4 0.1 12288 16384 FREQUENCY (MHz) AMPLITUDE (dBFS)–80 –20 –10 10 20 25
90067814 G03
–100 –110 –40 –60 –90 –30 –120 –50 –70 5 15 30 35 FREQUENCY (MHz) AMPLITUDE (dBFS)–80 –20 –10 10 20 25
90067814 G04
–100 –110 –40 –60 –90 –30 –120 –50 –70 5 15 30 35 FREQUENCY (MHz) AMPLITUDE (dBFS)–80 –20 –10 10 20 25
90067814 G05
–100 –110 –40 –60 –90 –30 –120 –50 –70 5 15 30 35 FREQUENCY (MHz) AMPLITUDE (dBFS)–80 –20 –10 10 20 25
90067814 G06
–100 –110 –40 –60 –90 –30 –120 –50 –70 5 15 30 35 OUTPUT CODE 8197 1000 3000
2000 COUNT
90067814 G07
TYPICAL PERFORMANCE CHARACTERISTICS LTM9008-14: SNR vs Input Frequency, –1dBFS, 2V Range, 65Msps LTM9008-14: SFDR vs Input Level, f IN = 70MHz, 2V Range, 65Msps LTM9008-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS LTM9008-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 65Msps I OVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS LTM9008-14: SNR vs SENSE, f IN = 5MHz, –1dBFS LTM9008-14: SNR vs Input Level, f IN = 70MHz, 2V Range, 65Msps INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300 350
90067814 G08
INPUT FREQUENCY (MHz) SFDR (dBFS) 50 100 150 200 250 300 350
90067814 G09
INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 110
90067814 G11
INPUT LEVEL (dBFS) SNR (dBc AND dBFS) SAMPLE RATE (Msps) 320 310 300 290 280 270 260 250 240 230
220 IVDD (mA)
90067814 G12
SENSE PIN (V) 0.6 SNR (dBFS)
90067814 G14
SAMPLE RATE (Msps) IOVDD (mA) 0 20 40 60
90067814 G13
1-LANE, 1.75mA 2-LANE, 3.5mA 2-LANE, 1.75mA 1-LANE, 3.5mA
TYPICAL PERFORMANCE CHARACTERISTICS LTM9007-14: Integral Nonlinearity (INL) vs Output Code LTM9007-14: Differential Nonlinearity (DNL) vs Output Code LTM9007-14: 64k Point FFT, f IN = 5MHz, –1dBFS, SENSE = VDD LTM9007-14: Shorted Input Histogram LTM9007-14: 64k Point FFT, f IN = 70MHz, –1dBFS, SENSE = VDD LTM9007-14: 64k Point 2-Tone FFT, fIN = 28.5MHz and fIN = 31.5MHz, –7dBFS per Tone, SENSE = VDD LTM9007-14: 64k Point FFT, fIN = 30MHz, –1dBFS, SENSE = VDD OUTPUT CODE INL ERROR (LSB) 1.0 16384
90067814 G15
–1.0 –2.0 4096 8192 12288 2.0 –0.5 0.5 –1.5 1.5 OUTPUT CODE –0.5 DNL ERROR (LSB) –0.4 –0.2 –0.1 0.5 0.2 4096 8192
90067814 G16
–0.3 0.3 0.4 0.1 12288 16384 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G17
–70 –80 –120 5 10 15 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G18
–70 –80 –120 5 10 15 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G19
–70 –80 –120 5 10 15 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G20
–70 –80 –120 2 8 144 10 166 12 18 –100 –10 –40 –50 –90 –110 OUTPUT CODE 8198 1000 3000
90067814 G21
LTM9007-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS LTM9007-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 40Msps TYPICAL PERFORMANCE CHARACTERISTICS LTM9007-14: SNR vs Input Frequency, –1dBFS, 2V Range, 40Msps LTM9007-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 40Msps LTM9007-14: SNR vs SENSE, f IN = 5MHz, –1dBFS INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300 350
90067814 G22
INPUT FREQUENCY (MHz) SFDR (dBFS) 50 100 150 200 250 300 350
90067814 G23
INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 110
90067814 G24
SAMPLE RATE (Msps) 200 190 180 170 160 150
140 IVDD (mA)
90067814 G25
SENSE PIN (V) 0.6 SNR (dBFS)
90067814 G26
TYPICAL PERFORMANCE CHARACTERISTICS LTM9006-14: 64k Point 2-Tone FFT, fIN = 28.5MHz and 31.5MHz, –7dBFS per Tone, SENSE = VDD LTM9006-14: Shorted Input Histogram LTM9006-14: 64k Point FFT, fIN = 30MHz, –1dBFS, SENSE = VDD LTM9006-14: 64k Point FFT, fIN = 70MHz, –1dBFS, SENSE = VDD LTM9006-14: Integral Nonlinearity (INL) vs Output Code LTM9006-14: Differential Nonlinearity (DNL) vs Output Code LTM9006-14: 64k Point FFT, fIN = 5MHz, –1dBFS, SENSE = VDD OUTPUT CODE INL ERROR (LSB) 1.0 16384
90067814 G27
–1.0 –2.0 4096 8192 12288 2.0 –0.5 0.5 –1.5 1.5 OUTPUT CODE –0.5 DNL ERROR (LSB) –0.4 –0.2 –0.1 0.5 0.2 4096 8192
90067814 G28
–0.3 0.3 0.4 0.1 12288 16384 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G29
–70 –80 –120 2 84 106 12 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G30
–70 –80 –120 2 84 106 12 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G31
–70 –80 –120 2 84 106 12 –100 –10 –40 –50 –90 –110 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –30 –20
90067814 G32
–70 –80 –120 2 84 106 12 –100 –10 –40 –50 –90 –110 OUTPUT CODE 8198 1000 3000
90067814 G33
TYPICAL PERFORMANCE CHARACTERISTICS LTM9006-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dBFS DCO Cycle-Cycle Jitter vs Serial Data Rate LTM9006-14: SNR vs SENSE, f IN = 5MHz, –1dBFS LTM9006-14: SFDR vs Input Level, f IN = 70MHz, 2V Range, 25Msps LTM9006-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 25Msps LTM9006-14: SNR vs Input Frequency, –1dBFS, 2V Range, 25Msps INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300 350
90067814 G34
INPUT FREQUENCY (MHz) SFDR (dBFS) 50 100 150 200 250 300 350
90067814 G35
INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 110
90067814 G36
SAMPLE RATE (Msps) 160 150 140 130
120 IVDD (mA)
90067814 G37
SENSE PIN (V) 0.6 SNR (dBFS)
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SERIAL DATA RATE (Mbps) 350 300 250 200 150 100 PEAK-TO-PEAK JITTER (ps) 0 200 400 600 800 1000
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AIN1+ (B2): Channel 1 Positive Differential Analog Input. AIN1– (B1): Channel 1 Negative Differential Analog Input. VCM12 (B3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 2. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN2+ (C2): Channel 2 Positive Differential Analog Input. AIN2– (C1): Channel 2 Negative Differential Analog Input. AIN3+ (E2): Channel 3 Positive Differential Analog Input. AIN3– (E1): Channel 3 Negative Differential Analog Input. VCM34 (F3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 3 and 4. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN4+ (G2): Channel 4 Positive Differential Analog Input. AIN4– (G1): Channel 4 Negative Differential Analog Input. AIN5+ (H1): Channel 5 Positive Differential Analog Input. AIN5– (H2): Channel 5 Negative Differential Analog Input. VCM56 (J3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 5 and 6. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. A IN6+ (K1): Channel 6 Positive Differential Analog Input. AIN6– (K2): Channel 6 Negative Differential Analog Input. AIN7+ (M1): Channel 7 Positive Differential Analog Input. AIN7– (M2): Channel 7 Negative Differential Analog Input. VCM78 (N3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 7 and 8. VCM is internally bypassed to ground with a 0.1µF ceramic capacitor. No external capacitance is required. AIN8+ (N1): Channel 8 Positive Differential Analog Input. AIN8– (N2): Channel 8 Negative Differential Analog Input VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power Supply. VDD is internally bypassed to ground with 0.1μF ceramic capacitors. ENC + (P5): Encode Input. Conversion starts on the rising edge. ENC – (P6): Encode Complement Input. Conversion starts on the falling edge. CSA (L5): In serial programming mode, (PAR/SER = 0V), CSA is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. CSB (M5): In serial programming mode, (PAR/SER = 0V), CSB is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (L6): In serial programming mode, (PAR /SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (M6): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = V DD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (See Pin Configuration Table): ADC Power Ground. Use multiple vias close to pins.
OVDD (G9, G10): Output Driver Supply. OVDD is internally bypassed to ground with a 0.1µF ceramic capacitor. SDOA (E6): In serial programming mode, (PAR/SER = 0V), SDOA is the optional serial interface data output for registers controlling channels 1, 4, 5 and 8. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resis- tor is not necessary and SDO can be left unconnected. In parallel programming mode (PAR/SER = VDD), SDOA is an input that enables internal 100Ω termination resistors on the digital outputs of channels 1, 4, 5 and 8. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6 and 7. See description for SDOA. PAR/SER (A7): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CSA, CSB, SCK, SDI, SDOA and SDOB become a serial interface that control the A/D operating modes. Connect to VDD to enable parallel programming mode where CSA, CSB, SCK, SDI, SDOA and SDOB become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/ SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. V REF (B6): Reference Voltage Output. VREF is internally bypassed to ground with a 1μF ceramic capacitor, nomi- nally 1.25V. SENSE (C5): Reference Programming Pin. Connecting SENSE to V DD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. SENSE is internally bypassed to ground with a 0.1µF ceramic capacitor. LVDS Outputs All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OUT1A –/OUT1A+, OUT1B–/OUT1B+ (E7/E8, C8/D8): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A–/OUT1A+ are used. OUT2A–/OUT2A+, OUT2B–/OUT2B+ (B8/A8, D7/C7): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A–/OUT2A+ are used. OUT3A–/OUT3A+, OUT3B–/OUT3B+ (D10/D9, E10/E9): Serial Data Outputs for Channel 3. In 1-lane output mode only OUT3A–/OUT3A+ are used. OUT4A–/OUT4A+, OUT4B–/OUT4B+ (C9/C10, F7/F8): Serial Data Outputs for Channel 4. In 1-lane output mode only OUT4A–/OUT4A+ are used. OUT5A–/OUT5A+, OUT5B–/OUT5B+ (J8/J7, K8/K7): Serial Data Outputs for Channel 5. In 1-lane output mode only OUT5A–/OUT5A+ are used. OUT6A–/OUT6A+, OUT6B–/OUT6B+ ( K9/K10, L9/L10): Serial Data Outputs for Channel 6. In 1-lane output mode only OUT6A–/OUT6A+ are used. OUT7A–/OUT7A+, OUT7B–/OUT7B+ (M7/L7, P8/N8): Serial Data Outputs for Channel 7. In 1-lane output mode only OUT7A–/OUT7A+ are used. OUT8A–/OUT8A+, OUT8B–/OUT8B+ (L8/M8, M10/M9): Serial Data Outputs for Channel 8. In 1-lane output mode only OUT8A–/OUT8A+ are used. FRA–/FRA+ (H7/H8): Frame Start Outputs for Channels 1, 4, 5 and 8. FRB –/FRB+ (J9/J10): Frame Start Outputs for Channels 2, 3, 6 and 7. DCOA –/DCOA+ (G8/G7): Data Clock Outputs for Channels 1, 4, 5 and 8. DCOB –/DCOB+ (F10, F9): Data Clock Outputs for Chan- nels 2, 3, 6 and 7.
A GND GND GND GND GND GND PAR/SER O2A+ GND GND B AIN1– AIN1+ VCM12 GND GND VREF GND O2A– GND GND C AIN2– AIN2+ GND GND SENSE GND O2B+ O1B– O4A– O4A+ D GND GND VDD VDD GND SDOB O2B– O1B+ O3A+ O3A– E AIN3– AIN3+ VDD VDD GND SDOA O1A– O1A+ O3B+ O3B– F GND GND VCM34 GND GND GND O4B– O4B+ DCOB+ DCOB– G AIN4– AIN4+ GND GND GND GND DCOA+ DCOA– OVDD OVDD H AIN5+ AIN5– GND GND GND GND FRA– FRA+ GND GND J GND GND VCM56 GND GND GND O5A+ O5A– FRB– FRB+ K AIN6+ AIN6– VDD VDD GND GND O5B+ O5B– O6A– O6A+ L GND GND VDD VDD CSA SCK O7A+ O8A– O6B– O6B+ M AIN7+ AIN7– GND GND CSB SDI O7A– O8A+ O8B+ O8B– N AIN8+ AIN8– VCM78 GND GND GND GND O7B+ GND GND P GND GND GND GND CLK+ CLK– GND O7B– GND GND Top View of BGA Package (Looking Through Component). PIN CONFIGURATION TABLE
Figure 1. Functional Block Diagram
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mode control registers through a serial SPI port. resulting in lower A/D distortion. Figure 2. Equivalent Input Circuit. Only One Figure 3. Analog Input Circuit Using a T ransformer.
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mode voltage can be optimally set to minimize distortion. See back page for a DC-coupled example. Figure 4. Recommended Front End Circuit for Input Figure 5. Recommended Front End Circuit for Input Figure 6. Recommended Front End Circuit for Input Figure 7. Front End Circuit Using a High Speed
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Figure 8. Reference Circuit Figure 9. Using an External 1.25V Reference apply a 1.25V reference voltage to SENSE (Figure 9). adjust the input range of individual channels. bypassed, as shown in Figure 8.
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soidal, PECL, or LVDS encode inputs (Figures 12 and 13). Figure 13. PECL or LVDS Encode DriveFigure 12. Sinusoidal Encode Drive Figure 10. Equivalent Encode Input Circuit Figure 11. Equivalent Encode Input Circuit for performance ENC+ should have fast rise and fall times.
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requires 25µs to lock onto the input clock. of the applied encode signal to vary from 30% to 70%. with 12-bit versions of these parts. mode, the frequency of the FR output is halved. all serialization modes is 5Msps. isolated from the A/D core power and ground. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9008-14.
2.5mA LVDS output current modes. inductive coupling or coupling through the ground plane. and all other bits. The FR and DCO outputs are not affected. Table 2. Output Codes vs Input Voltage
but the differential impedance may remain low. required to recover from sleep mode is about 2ms. register A1 in the serial programming mode. has more flexibility and can program all available modes. modes set by CS, SCK, SDI and SDO. Table 3. Parallel Programming Mode Control Bits
Table 4. Serial Programming Mode Register Map (PAR/SER = GND) Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only. Bits 6-0 Unused, Don’t Care Bits. Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Note: Any Combination of Channels Can Be Placed in Nap Mode. serial interface that program the A/D mode control registers. can also be read back from a register to verify its contents. SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). the register is not updated and data on SDI is ignored. through SDO, an external 2k pull-up resistor is required. needed. Table 4 shows a map of the mode control registers.
REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_7 NAP_6 NAP_3 NAP_2 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Tw o’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Tw o’s Complement Data Format Bits 4-0 SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 2 in Nap Mode 0XX1X = Channel 3 in Nap Mode 0X1XX = Channel 6 in Nap Mode 01XXX = Channel 7 in Nap Mode 1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes. Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled. 1 = Digital Outputs Are Disabled. Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don’t Care Bit. Bit 5-0 TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7-0 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB). Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. GROUNDING AND BYPASSING The LTM9008-14/LTM9007-14/LTM9006-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. Bypass capacitors are integrated inside the package; ad- ditional capacitance is optional. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. The pin assignments of the LTM9008-14/LTM9007-14/ LTM9006-14 allow a flow- through layout that makes it possible to use multiple parts in a small area when a large number of ADC channels are required. The device has similar layout rules to other BGA pack- ages. The layout can be implemented with 6mil blind vias and 5mil traces. The pinout has been designed to minimize the space required to route the analog and digital traces. The analog and digital traces can essentially be routed within the width of the package. This allows multiple packages to be located close together for high channel count applications. T race lengths for the analog inputs and digital outputs should be matched as well as possible.
Table 5. Internal T race Lengths digital outputs is 188.5ps/in or 7.417ps/mm.
Inner Layer 2 Inner Layer 3
Bottom Side Silkscreen Bottom
3.3 AUX
31.6k R13 31.6k 10k LANE CSB JP3 1k 1 LANE
2 LANE
+1.8V+1.8V +1.8V +1.8V ILVDS SCK JP5 1k1.7mA 3.5mA LANE CSA JP2 1k1 LANE +1.8V PAR/SER PAR/SER PAR/SER SENSE VREF SCI SCK CSA CSB SDOA SDOB MOSIJP4 1kPAR SER 100/uni03A9 EXT REF R10 2.2µF , 0603 A10 B10 H10 N10 P10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND L TM9008-14+1.8V R20 100/uni03A9 R14 (OPT) (OPT)
4 R18
(OPT) R25 (OPT) (OPT) R24 (OPT) C13 100µF 10V R28
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OUT1A– OUT1B+ OUT1B– OUT1A+ OUT1A– OUT1B+ OUT1B– OUT2A+ OUT2A– OUT2B+ OUT2B– OUT2A+ OUT2A– OUT2B+ OUT2B– OUT3A+ OUT3A– OUT3B+ OUT3B– OUT3A+ OUT3A– OUT3B+ OUT3B– D10 E10 OUT4A+ OUT4A– OUT4B+ OUT4B– OUT4A+ OUT4A– OUT4B+ OUT4B– C10 OUT5A+ OUT5A– OUT5B+ OUT5B– OUT5A+ OUT5A– OUT5B+ OUT5B– OUT6A+ OUT6A– OUT6B+ OUT6B– OUT6A+ OUT6A– OUT6B+ OUT6B– K10 L10 AIN1+ AIN1– VCM12 AIN1+ AIN1– VCM12 AIN2+ AIN2– AIN2+ AIN2– AIN3+ AIN3– VCM34 AIN3+ AIN3– VCM34 VCM12 AIN4+ AIN4– AIN4+ AIN4– AIN5+ AIN5– VCM56 AIN5+ AIN5– VCM56 AIN6+ AIN6– AIN6+ AIN6– AIN8+ AIN8– VCM78 AIN8+ AIN8– VCM78 AIN7+ AIN7– AIN7+ AIN7– M2CLK+ CLK– CLK+ CLK– P6 OUT7A+ OUT7A– OUT7B+ OUT7B– OUT7A+ OUT7A– OUT7B+ OUT7B– M10 FRA+ FRA– FRB+ FRB– FRA+ FRA– FRB+ FRB– J10 DCOA+ DCOA– DCOB+ DCOB– DCOA+ DCOA– DCOB+ DCOB– F10 +1.8VO +1.8VO +1.8VO G10 +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V 4.7pF 4.7pF R23 5.1/uni03A9 R37 100/uni03A9 R17 5.1/uni03A9 R22 49.9/uni03A9 R21 49.9/uni03A9 0.01µF R27 (OPT) 0.01µF (OPT) 0.01µF R26 (OPT) R16 (OPT) R15 (OPT) MABA- 007159-000000 FB1 BLM31PG330SN1L FB2 BLM31PG330SN1L 0.01µF 0.01µF R19 100/uni03A9 +1.8V +1.8VO L T3080EDD C11 1µF 0603 OUT OUT OUT OUT C56 0.1µF C14 0.1µF C10 4.7µF 6.3V 0603 C12 1µF 0603 4SET6 NC IN IN VCTRL R29 180k +1.8V +1.8V C18 (OPT) C23 (OPT) C15 (OPT) C19 (OPT) C17 (OPT) (SAME FOR OTHER CHANNELS) R30 0/uni03A9 0603 R36 0/uni03A9 0603 R31 0/uni03A9 0805 R37 0/uni03A9 0805 R32 0/uni03A9 0603 R38 0/uni03A9 0603 IN+ IN– R48 100/uni03A9
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW X aaa Z SEE NOTES BGA 140 0709 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” Øb (140 PLACES) D DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee 0.4 Ø 140x SYMBOL A b D E e aaa bbb ccc ddd eee MIN 2.57 0.35 2.22 0.45 0.35 NOM 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 MAX 2.87 0.45 2.42 0.55 0.45 0.15 0.10 0.12 0.15 0.08 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 140 Y aaa Z E e b e L TMXXXXXX µModule DETAIL A SUGGESTED PCB LAYOUT TOP VIEW 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 5.200 4.400 4.400 5.200 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 PIN “A1” CORNER P DETAIL A C D E F G H J K L M N A B 10 9 8 7 6 5 4 3 2 PIN 1 PACKAGE BOTTOM VIEW b A Z DETAIL B SUBSTRATE 0.27 – 0.37 1.95 – 2.05 // bbb Z ccc Z MOLD CAP 140-Lead (11.25mm × 9.00mm × 2.72mm) (Reference L TC DWG # 05-08-1849 Rev A) Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORA TION 2012 LT 1112 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2170-14/LTC2171-14/ LTC2172-14 14-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2173-14/LTC2174-14/ LTC2175-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 412mW/481mW/567mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTM9009-14/LTM9010-14/ LTM9011 -14 14-Bit, 80Msps/105Msps/125Msps 1.8V Octal ADCs, Ultralow Power 801mW/950mW/1145mW, 73.1dB SNR, 85dB SFDR, Serial LVDS Outputs, 11.25mm × 9mm BGA-140 Amplifiers/Filters LTC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V , 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm × 4mm QFN-20 LTC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm × 4mm QFN-20 LTC6605-7/ LTC6605-10/ LTC6605-14 Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22 Signal Chain Receivers LTM9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers TYPICAL APPLICATION Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown). Filter for Use at 61.44Msps L TM9008-14 VCM12 AIN2+ AIN2– AIN3+ AIN3– VCM34 AIN4+ AIN4– AIN8+ AIN8– AIN1+ AIN1– O1A+ O1A– DCO+ DCO– FR+ FR– CLK+ CLK– P5 P6 B6C5 1.8V 1.8V SENSE VDD VREF OVDD 33pF 100pF 150pF 180nH180nH 3.3V 180nH180nH 150pF 150/uni03A9 474/uni03A9 37.4/uni03A9 37.4/uni03A9 OUT– OUT+ VOCM IN+ IN– 474/uni03A9 75/uni03A9 75/uni03A9 66.9/uni03A9 66.9/uni03A9 0.1µF 0.8pF 0.8pF 68pF 68pF0.1µF
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- • • 150/uni03A9 SHDN GND 49.9/uni03A9 50/uni03A9
- • • L TC6409