LTM9003 LINER
Document overview
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Technical content
DESCRIPTION
12-Bit Digital Pre-Distortion Receiver Subsystem The L TM®9003 is a 12-bit digital pre-distortion receiver subsystem for the transmit path of cellular basestations. Utilizing an integrated system in a package (SiP) tech-nol- ogy, it includes a downconverting mixer , wideband fi lter and analog-to-digital converter (ADC). The system is tuned for an intermediate frequency (IF) of 184MHz and a signal bandwidth of up to 125MHz. The 12-bit ADC samples at rates up to 250Msps. Contact Linear Technology regard- ing customization. The high signal level downconverting active mixer is opti- mized for high linearity, wide dynamic range IF sampling applications. It includes a differential LO buffer amplifi er driving a double-balanced mixer . Broadband, integrated transformers on the RF and LO inputs provide single ended 50Ω interfaces. The RF and LO inputs are internally matched to 50Ω from 1.1GHz to 1.8GHz. The CLK input controls converter operation and may be driven differentially or single-ended. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.FFT of 4-Channel WCDMA Input at 1.95GHz
FEATURES
APPLICATIONS
n Fully Integrated Receiver Subsystem for Digital Pre-Distortion Applications n Down-Converting Mixer with Wide RF Frequency Range: 400MHz to 3.8GHz n 125MHz Wide Bandpass Filter , <0.5dB Passband Ripple n Low Power ADC with Up to 12-Bit Resolution, 250Msps Sample Rate n –145.5dBm/Hz Input Noise Floor , 25.8dBm IIP3 n 1.5W Total Power Consumption n 50Ω Single-Ended RF and LO Ports n Internal Bypass Capacitance, No External Components n ADC Clock Duty Cycle Stabilizer n 11.25mm × 15mm LGA package n T ransmit Observation Path Receivers n Digital Pre-Distortion (DPD) Receivers n Wideband Receiver n Wideband Instrumentation IF FREQUENCY (MHz) 154 –110 –90 –100 –80 –50 –60 –70(dB) 164 174 194 184 204 214
9003 TA01b
–40 L TM9003 OVDD = 2.5V DGND ENC– ENC+GNDLO 3.3V 2.5V RF
9003 TA01
Electrical Specifications Subject to Change
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC1) Supply Voltage (V CC1 + 1V CC1 + 0.3V DD + 0.3V) Operating Ambient Temperature Range CAUTION: The RF and LO inputs are sensitive to electro- static discharge (ESD). It is very important that proper ESD precautions be observed when handling the L TM9003. (Notes 1, 2) VCC2 23456789 1 0 1 111 2 A B C D E F G H J LGA PACKAGE 108-LEAD (15mm s 11.25mm s 2.32mm) TOP VIEW VCC1 ALL OTHERS = GND DATA, CONTROLAMP_EN ENC– ENC+ VDD OVDD RF LO MIX_EN TJMAX = 125°C, θJA = 15°C/W , θJC = 6°C/W DERIVED FROM TBDmm × TBDmm PCB WITH 4 LAYERS WEIGHT = TBD g ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM9003CV-AA#PBF L TM9003CV-AA#PBF L TM9003V AA 108-Lead (11.25mm × 15mm × 2.3mm) LGA 0°C to 70°C L TM9003IV-AA#PBF L TM9003IV-AA#PBF L TM9003V AA 108-Lead (11.25mm × 15mm × 2.3mm) LGA –40°C to 85°C L TM9003CV-AB#PBF L TM9003CV-AB#PBF L TM9003V AB 108-Lead (11.25mm × 15mm × 2.3mm) LGA 0°C to 70°C L TM9003IV-AB#PBF L TM9003IV-AB#PBF L TM9003V AB 108-Lead (11.25mm × 15mm × 2.3mm) LGA –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS RF Input Frequency Range L TM9003-AA No External Matching (Midband) With External Matching (Low Band or High Band) 400 1100 to 1800 3800 MHz MHz L TM9003-AB No External Matching (Midband) With External Matching (Low Band or High Band) 400 1100 to 1800 3700 MHz MHz LO Input Frequency Range L TM9003-AA No External Matching With External Matching 380 800 to 3500 MHz MHz L TM9003-AB No External Matching With External Matching 380 900 to 3500 MHz MHz RF Input Return Loss Z O = 50Ω, 1100MHz to 1800MHz (No External Matching) L TM9003-AA L TM9003-AB >12 >12 dB dB LO Input Return Loss Z O = 50Ω, 900MHz to 3500MHz (No External Matching) L TM9003-AA L TM9003-AB >10 >10 dB dB RF Input Power for –1dBFS L TM9003-AA L TM9003-AB –1.8 –1.8 dBm dBm LO Input Power 1200MHz to 4200MHz, L TM9003-AA or 1200MHz to 3500MHz, L TM9003-AB 380MHz to 1200MHz dBm dBm LO to RF Leakage L TM9003-AA f LO = 380MHz to 1600MHz fLO = 1600MHz to 4000MHz <–50 <–45 dBm dBm L TM9003-AB fLO = 400MHz to 2100MHz fLO = 2100MHz to 3200MHz <–44 <–36 dBm dBm RF to LO Isolation L TM9003-AA fRF = 400MHz to 1700MHz fRF = 1700MHz to 3800MHz >50 >42 dBm dBm L TM9003-AB fRF = 400MHz to 2200MHz fRF = 2200MHz to 3700MHz >43 >38 dBm dBm CONVERTER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 Bits Integral Linearity Error (Note 4) IF = 184.32MHz TBD LSB Differential Linearity Error IF = 184.32MHz TBD LSB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio at –1dBFS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD 143.7 143.7 dB/Hz dB/Hz dB/Hz IIP3 Input 3rd Order Intercept, 2-Tone L TM9003-AA RF = 1948MHz, 1952MHz, LO = 1766MHz 25.8 dBm L TM9003-AB RF = 1948MHz, 1952MHz, LO = 1766MHz 26.5 dBm IIP2 Input 2nd Order Intercept, 1-Tone L TM9003-AA RF = 1950MHz, LO = 1766MHz 61 dBm L TM9003-AB RF = 1950MHz, LO = 1766MHz 67 dBm SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic at –1dBFS L TM9003-AA RF = 1889MHz, LO = 1766MHz RF = 1950MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD 52.4 67.4 dB dB dB L TM9003-AB RF = 1889MHz, LO = 1766MHz RF = 1950MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD 71.5 dB dB dB SFDR Spurious Free Dynamic Range 4th or Higher at –1dBFS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD dB dB dB S/(N+D) Signal-to-Noise Plus Distortion Ratio at –1dBFS RF = 1950MHz, LO = 1766MHz RF = 1889MHz, LO = 1766MHz RF = 2011MHz, LO = 1766MHz l TBD dB dB dB IMD3 Intermodulation Distortion at –7dBFS per Tone RF = 1950MHz, LO = 1766MHz –67 dB ACPR Adjacent Channel Power Ratio at 2.4dBm per Carrier , Four Carriers 58.5 dB AL TCPR Alternate Channel Power Ratio at 2.4dBm per Carrier , Four Carriers 63.3 dB The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) FILTER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Center Frequency L TM9003-Ax 184.32 MHz Lower 3dB Bandedge L TM9003-Ax 84 MHz Upper 3dB Bandedge L TM9003-Ax 304 MHz Lower 20dB Stopband L TM9003-Ax 40 MHz Upper 20dB Stopband L TM9003-Ax 450 MHz Passband Flatness 129MHz to 239.6MHz, L TM9003-Ax 174MHz to 194MHz, L TM9003-Ax 0.5 0.15 dB dB Group Delay Flatness 129MHz to 239.6MHz, L TM9003-Ax 174MHz to 194MHz, L TM9003-Ax 1.2 0.1 ns ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC–, ENC+) VID Differential Input Voltage l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set l 1.2 1.5 1.5 2 V V RIN Input Resistance 4.8 Ω CIN Input Capacitance 2p F Logic Inputs (OE, SHDN) VIH High Level Input Voltage V DD = 2.5V l 1.7 V VIL Low Level Input Voltage V DD = 2.5V l 0.7 V IIN Input Current V IN = 0V to VDD l –10 10 μA CIN Input Capacitance (Note 5) 3 pF Mixer Enable V IH High Level Input Voltage V CC1 = 3.3V , L TM9003-AA VCC1 = 5V , L TM9003-AB 2.7 V V VIL Low Level Input Voltage V CC1 = 3.3V , L TM9003-AA VCC1 = 5V , L TM9003-AB 0.3 0.3 V V IIN Input Current V IN = 0V to VCC1, L TM9003-AA 53 90 μA Turn-On Time 2.8 ms Turn-Off Time 2.9 ms Amplifi er Enable V IH High Level Input Voltage V CC2 = 3.3V 2.7 V VIL Low Level Input Voltage V CC2 = 3.3V 0.3 V IIN Input Current V IN = 0V to VCC2 53 90 μA Control Inputs (SENSE, MODE, LVDS) I SENSE SENSE Input Leakage 0V < SENSE < 1V l –1 1 μA IMODE MODE Pull-Down Current to GND See Pin Descriptions for Voltage Levels 7 μA ILVDS LVDS Pull-Down Current to GND See Pin Descriptions for Voltage Levels 7 μA Logic Outputs (LVDS Mode) OV DD = 2.5V VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.250 1.375 V DIGITAL INPUTS AND OUTPUTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC1 Mixer Supply Range L TM9003-AA L TM9003-AB 2.9 4.5 3.3 3.9 5.25 V V VCC2 Amplifi er Supply Range 2.8 3.3 5.25 V VDD ADC Analog Supply Voltage l 2.375 2.5 2.625 V ICC1 Mixer Supply Current MIX_EN = 3V , L TM9003-AA MIX_EN = 5V , L TM9003-AB l 82 mA mA I CC1(SHDN) Mixer Shutdown Supply Current MIX_EN = 0V l 100 μA ICC2 Amplifi er Supply Current AMP_EN = 3V l 104 140 mA ICC2(SHDN) Amplifi er Shutdown Supply Current AMP_EN = 0V l 35 m A IDD(ADC) ADC Supply Current l 285 320 mA PD(SHDN) ADC Shutdown Power SHDN = 3V , OE = 3V , No CLK TBD mW PD(NAP) ADC Nap Mode Power SHDN = 3V , OE = 0V , No CLK TBD mW LVDS Output Mode OV DD ADC Digital Output Supply Voltage l 2.375 2.5 2.625 V IOVDD(ADC) ADC Digital Output Supply Current l 58 70 mA PD(ADC) ADC Power Dissipation l 858 975 mW PD(TOTAL) Total Power Dissipation SHDN = 0V , MIX_EN = AMP_EN = 3V , f SAMPLE = MAX (L TM9003-AA) (L TM9003-AB) 1472 1591 mW mW The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f s Sampling Frequency l 1 250 MHz tL ENC Low Time Duty Cycle Stabilizer Off (Note 5) Duty Cycle Stabilizer On (Note 5) l l 1.9 1.5 500 500 ns ns tH ENC High Time Duty Cycle Stabilizer Off (Note 5) Duty Cycle Stabilizer On (Note 5) l l 1.9 1.5 500 500 ns ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 95 fs RMS tAP Sample-and-Hold Aperture Delay 0 ns tOE Output Enable Delay (Note 5) l 51 0 n s LVDS Output Mode t D ENC to DATA delay (Note 5) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 5) l 1 1.7 2.8 ns DATA to CLKOUT Skew (t C – tD) (Note 5) l –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 3) Note 3: VCC1 = VCC2 = 3.3V (L TM9003-AA) or VCC1 = 5V , VCC2 = 3.3V (L TM9003-AB), VDD = 2.5V , OVDD = 2.5V , fSAMPLE = 250MHz, input range = –1dBFS, differential ENC+/ENC– = 2VP–P sine wave, unless otherwise noted. Note 4: Integral nonlinearity is defi ned as the deviation of a code from a “best straight line” fi t to the transfer curve. The deviation is measured from the center of the quantization band. Note 5: Guaranteed by design, not subject to test.
All Outputs Are Differential and Have LVDS Levels tH tD tC tL N – 5 N – 4 N – 3 N – 2 N – 1 tAP N + 1 N + 2 N + 4 N + 3 NANALOG INPUT ENC– ENC+ CLKOUT– CLKOUT+ D0-D11, OF
9003 TD01
TYPICAL PERFORMANCE CHARACTERISTICS IF Frequency Response, L TM9003-AA IF Frequency Response, L TM9003-AA 64k Point FFT , L TM9003-AA 64k Point 2-Tone FFT , L TM9003-AA SNR vs Frequency, L TM9003-AA FREQUENCY (MHz) AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –10 –30 –50 –70 –90 –110 –120 40 8020 60 100
9003 G01
fIN = 1950MHz –1dBFS SENSE = V DD FREQUENCY (MHz) AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –10 –30 –50 –70 –90 –110 –120 40 8020 60 100
9003 G02
fIN = 1948MHz, fIN = 1952MHz –7dBFS PER TONE SENSE = V DD IF FREQUENCY (MHz) SNR (dBFS) 210 31016011060 260 360
9003 G03
IF FREQUENCY (MHz) AMPLITUDE (dBFS) –1.0 –2.0 –0.5 –1.5 –2.5 –3.0 210160135110 235 185
9003 G04
IF FREQUENCY (MHz) AMPLITUDE (dBFS) 210 31016011060 260 360
9003 G05
–20 –40 –10 –30 –25 –15 –35 –45 –50
TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT , L TM9003-AB 64k Point 2-Tone FFT , L TM9003-AB SNR vs Frequency, L TM9003-AB FREQUENCY (MHz) AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –10 –30 –50 –70 –90 –110 –120 40 8020 60 100
9003 G06
fIN = 1950MHz –1dBFS SENSE = V DD FREQUENCY (MHz) AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –10 –30 –50 –70 –90 –110 –120 40 8020 60 100
9003 G07
fIN = 1948MHz, fIN = 1952MHz –7dBFS PER TONE SENSE = V DD IF FREQUENCY (MHz) SNR (dBFS) 210 31016011060 260 360
9003 G08
IF Frequency Response, L TM9003-AB IF Frequency Response, L TM9003-AB IF FREQUENCY (MHz) AMPLITUDE (dBFS) –1.0 –2.0 –0.5 –1.5 –2.5 –3.0 210160135110 235 185
9003 G09
IF FREQUENCY (MHz) AMPLITUDE (dBFS) 210 31016011060 260 360
9003 G10
–20 –40 –10 –30 –25 –15 –35 –45 –50
VCC1 (Pins E1, E2, F2): 3.3V (L TM9003-AA) or 5V (L TM9003-AB) Supply Voltage for the Mixer . V CC1 is internally bypassed to GND. VCC2 (Pins B1, B2): 3.3V Supply Voltage for the Amplifi er . VCC2 is internally bypassed to GND. VDD (Pins D11, E7, E8): 2.5V Supply Voltage for ADC. VDD is internally bypassed to GND. OVDD (Pins G12, H9, H11): Positive Supply for the Out- put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor . OV DD can be 0.5V to 2.6V . OVDD is internally bypassed to OGND. GND (See Table for Locations): Module Ground. OGND (Pins F12, H8, H10, H12, J12): Output Driver Ground. RF (Pin G1): Single-Ended Input for the RF Signal. This pin is internally connected to the primary side of the RF input transformer , which has low DC resistance to ground. If the RF source is not DC blocked, then a series blocking capacitor must be used. The RF input is internally matched from 1.1GHz to 1.8GHz. Operation down to 400MHz or up to 3.8GHz is possible with simple external matching. LO (Pin J2): Single-Ended Input for the Local Oscillator Signal. This pin is internally connected to the primary side of the LO transformer , which is internally DC blocked. An external blocking capacitor is not required. The LO input is internally matched from 0.9GHz to 3.5GHz. Operation down to 380MHz is possible with simple external matching. MIX_EN (Pin F4): Mixer Enable Pin. Connecting MIX_EN to V CC1 results in normal operation. Connecting MIX_EN to GND disables the mixer . The MIX_EN pin should not be left fl oating. AMP_EN (Pin C3): Amplifi er Enable Pin. This pin is internally pulled high by a typically 30k resistor to V CC2. Connecting AMP_EN to VCC2 results in normal operation. Connecting AMP_EN to GND disables the amplifi er . ENC+ (Pin D12): ADC Encode Input. Conversion starts on the positive edge. ENC– (Pin E12): ADC Encode Complement Input. Conver- sion starts on the negative edge. Bypass to ground with 0.1μF ceramic for single-ended ENCODE signal. SHDN (Pin B11): ADC Shutdown Mode Selection Pin. Con- necting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to V DD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin C11): Output Enable Pin. Refer to SHDN pin function. MODE (Pin C7): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 V DD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. V DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin G7): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of SENSE. ±1V is the largest valid input range. LVDS (Pin D7): Output Mode Selection Pin. Connect LVDS to VDD. Digital Outputs D0–/D0+ – D11–/D11+ (See Table for Locations): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver . D11 –/D11+ is the MSB. CLKOUT–/CLKOUT+ (Pins J10/J11): LVDS Data Valid Output. Latch data on rising edge of CLKOUT –, falling edge of CLKOUT+. OF–/OF+ (Pins E5/F5): LVDS Over/Under Flow Output. High when an over or under fl ow has occurred.
9003 BD01
Figure 1. Simplifi ed Block Diagram
The L TM9003 is an integrated system in a package (SiP) that includes a high-speed 12-bit A/D converter , a wideband fi lter and an active mixer . The L TM9003 is designed for IF sampling, digital pre-distortion (DPD) applications, also known as transmit observation path receivers, with RF input frequencies up to 3.8GHz. Typical applications include multi- carrier base stations and telecom test instrumentation. Digital pre-distortion is a technique often used in third- generation (3G) wireless base stations to improve the linearity of power amplifi ers (PA). Improved PA linearity allows for a lower power PA to be used and therefore save a signifi cant amount of power in the base station. The DPD receiver captures the PA output, digitizes it and feeds it back where the distortion can be analyzed. A complementary distortion is then introduced to the transmit DAC thereby pre-distorting the signal. A signifi cant factor in PA linearity is the distortion caused by the odd order intermodulation (IM) products. The band- width to be digitized is equivalent to the signal bandwidth multiplied by the order of the IM product to be canceled. For example, four carrier WCDMA consumes 20MHz of signal bandwidth; therefore, to capture the fi fth order IM product requires 100MHz. The Nyquist theory requires that the ADC sample rate be at least twice that frequency. However , simply doubling the captured bandwidth to set the sample rate may not be the best choice. Selecting the exact ADC sample rate and intermediate frequency (IF) depends on other factors within the system. To simplify fi ltering, the sample rate is often set at a multiple of the chip rate. The chip rate for WCDMA is 3.84MHz; select- ing an ADC sample rate of 64 times the chip rate gives 245.76Msps. Placing the IF at 3/4ths the sample rate (f gives 184.32MHz and allows the entire bandwidth to fall within the second Nyquist zone. Many other frequency plans may be acceptable. The following sections describe in further detail the opera- tion of each functional element of the L TM9003. The SiP technology allows the L TM9003 to be customized and this is described in the Semi-Custom Options section. The outline of the remaining sections follows the basic functional elements as shown in Figure 2. Figure 2. Basic Functional Elements is matched for 1.1GHz to 1.8GHz with low side LO. tested to the exact parameters defi ned for the application.
highest linearity and the lowest noise fi gure. bandpass section, designed for 0.1dB passband ripple. Figure 3. Additional lowpass fi ltering is done just before
9003 F03
Figure 3. IF Filter Response a reconstruction DAC and an interstage residue amplifi er . that is sent to the fi fth stage ADC for fi nal evaluation. logic before being sent to the output buffer .
loss, shown in Figure 5, is typically 12dB at the band edges. with a series 3.9nH inductor and a 1pF shunt capacitor . Figure 4. RF Input Schematic
9003 F04
Figure 5. RF Input Return Loss with and without Matching
9003 F05
with a series chip inductor for a more compact layout. simulate board-level interfacing to the RF input fi lter .
match can be improved by using L4 = 2.7μH, C4 = 0.5pF . will still deliver good conversion gain and linearity. Figure 6. LO Input Schematic
9003 F06
to the LO pin with no external matching.
able the mixer , the enable voltage must be less than 0.3V . mended that the enable function be used in this manner . threshold for single-ended drive circuits. inherent ADC aperture jitter .
- Differential drive should be used.
- Use as large an amplitude as possible; if transformer
- If the ADC is clocked with a sinusoidal signal, fi lter the
encode signal to reduce wideband noise.
- Balance the capacitance and series resistance at both
Figure 7. LO Input Return Loss with and without Matching
9003 F07
9003 F08
The maximum conversion rate for the ADC is 250Msps. + pin to sample the analog input. DD or 2/3VDD using external resistors. SNR by 3dB at 140MHz, and 4.5dB at 190MHz. signals will be translated into phase noise. Figure 8. T ransformer Driven ENC+/ENC– Figure 9. Single-Ended ENC Driver , Not Recommended Figure 10. ENC Drive Using LVDS
9003 F09
9003 F10
ADC, and powered with a very quiet supply. vias no more than 1/4 inch apart. voltage, the digital data bits, and the overfl ow bit. Table 3. Output Codes vs Input Voltage Figure 11. Digital Output in LVDS Mode
9003 F11
traces should have about the same length. Table 5. MODE Pin Function
0 Straight Binary Off
+/OF– pins indicates an overfl ow or underfl ow. used to synchronize the converter data to the digital system. be latched on the falling edge of CLKOUT+/CLKOUT–. outputs are disabled and enter the Hi-Z state. ing circuitry if they have common input supplies.
The L TM9003 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the L TM9003 has been optimized for a fl ow-through layout so that the interaction between inputs and digital outputs is minimized. Ample ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The L TM9003 is internally bypassed with the ADC (V DD), amplifi er (VCC2) and mixer (VCC1) supplies returning to a common ground (GND). The digital output supply (OVDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is signifi cant. Heat T ransfer Most of the heat generated by the L TM9003 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of suffi cient area with as many vias as possible. Recommended Layout The high integration of the L TM9003 makes the PCB board layout very simple and easy. However , to optimize its electri- cal and thermal performance, some layout considerations are still necessary.
- Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the L TM9003, but can be connected on the PCB underneath the part to provide a common return path.
- Use multiple ground vias. Using as many vias as pos- sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies.
- Separate analog and digital traces as much as possible, using vias to create high-frequency barriers. This will re- duce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the L TM9003. Figures 12 through 15 give a good example of the recom- mended layout. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The L TM9003 employs gold-fi nished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materi- als declaration is available online at http://www.linear . com/leadfree/mat_dec.jsp. APPLICATIONS INFORMATION
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 108 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.15 0.10 0.05 2.22 – 2.42 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 1.95 – 2.05 Z 11.25 BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 10.16 BSC 1.27 BSC 13.97 BSC 11 10 9 8 7 6 5 4 3 2 PACKAGE BOTTOM VIEW DIA (0.635) PAD 1 PADS SEE NOTES 12 1 A B C D E F G H J SUGGESTED PCB LAYOUT TOP VIEW 1.270 1.270 0.000 2.540 2.540 3.810 3.810 5.080 5.080 6.985 6.985 5.715 5.715 4.445 4.445 3.175 3.175 1.905 1.905 0.635 0.635 0.000 LGA 108 0707 REV Ø PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX μModule TRAY PIN 1 BEVEL COMPONENT PIN “A1” // bbb Z 0.22 × 45° CHAMFER DETAIL A 0.630 ±0.025 SQ. 108x S YXeee 108-Lead (15mm × 11.25mm × 2.32mm) (Reference L TC DWG # 05-08-1757 Rev Ø)
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2009 LT 0709 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TC2240-10 10-Bit, 170Msps, 2.5V ADC, LVDS Outputs 445mW , 60.6dB SNR, 78dB SFDR, 64-Pin QFN L TC2240-12 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs 445mW , 65.5dB SNR, 80dB SFDR, 64-Pin QFN L TC2241-10 10-Bit, 210Msps, 2.5V ADC, LVDS Outputs 585mW , 60.6dB SNR, 78dB SFDR, 64-Pin QFN L TC2241-12 12-Bit, 210Msps, 2.5V ADC, LVDS Outputs 585mW , 65.5dB SNR, 78dB SFDR, 64-Pin QFN L TC2242-10 10-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW , 60.5dB SNR, 78dB SFDR, 64-Pin QFN L TC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW , 65.4dB SNR, 78dB SFDR, 64-Pin QFN L TC6410 Differential IF Amplifi er with Confi gurable Input Impedance 1.4GHz, –3dB BW , 6dB Fixed Voltage Gain (50Ω System), 36dBm OIP3 L T5527 400MHz to 3.7GHz, 5V High Signal Level Downconverting Mixer 23.5dBm IIP3 at 1.9GHz, NF = 12.5dB, Single-Ended RF and LO Ports L T5557 800MHz to 2.7GHz High Linearity Direct Conversion Quadrature Demodulator 24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO Ports, 3.3V Supply L TM9001 16-Bit, IF/Receiver Subsystem 16-Bit, 130Msps ADC, 20dB Gain Amplifi er , Anti-Alias Filter , Internal Bypass Capacitance L TM9002 Dual 14-Bit, IF/Baseband Receiver Subsystem Dual 14-Bit, 125Msps ADC, dual 26dB Gain Amplifi ers, Anti-Alias Filters, Auxi liary DAC for Gain Adjustment, Internal Bypass Capacitance