LTM9002

LTC2188 LINER

Document overview

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applicaTions

DescripTion

16-Bit, 20Msps Low Power Dual ADC n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing n T wo-Channel Simultaneously Sampling ADC n 77dB SNR n 90dB SFDR n Low Power: 76mW Total, 38mW per Channel n Single 1.8V Supply n CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: 1VP-P to 2VP-P n 550MHz Full Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Serial SPI Port for Configuration n 64-Lead (9mm × 9mm) QFN Package The L TC®2188 is a two-channel simultaneous sampling 16-bit A/D converter designed for digitizing high frequency wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07ps RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.2LSB RMS. The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V . The ENC + and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Integral Non-Linearity (INL) CMOS, DDR CMOS OR DDR LVDS OUTPUTS 1.8V VDD 1.8V OVDD CLOCK CONTROL D1_15 D1_0

2188 TA01a

D2_15 D2_0 20MHz CLOCK OUTPUT CODE –4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

2188 TA01b

Analog Input Voltage (AIN+, AIN–, 0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, 0.3V to 3.9V 0.3V to 3.9V (Notes 1, 2) pin conFiguraTions Operating Temperature Range °C to 70°C 40°C to 85°C 65°C to 150°C FULL-RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16

48 D1_5

47 D1_4

46 D1_3

45 D1_2

44 D1_1

43 D1_0

41 OGND

40 CLKOUT

39 CLKOUT–

38 D2_15

37 D2_14

36 D2_13

35 D2_12

34 D2_11

33 D2_10

64 VDD

63 SENSE

61 SDO

60 OF1

59 OF2

58 D1_15

57 D1_14

56 D1_13

55 D1_12

54 D1_11

53 D1_10

52 D1_9

51 D1_8

50 D1_7

49 D1_6

V DD 17 ENC+ 18 ENC– 19 CS 20 SCK 21 SDI 22 D2_0 23 D2_1 24 D2_2 25 D2_3 26 D2_4 27 D2_5 28 D2_6 29 D2_7 30 D2_8 31 D2_9 32 TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TOP VIEW UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16

48 D1_4_5

47 DNC

46 D1_2_3

45 DNC

44 D1_0_1

43 DNC

38 D2_14_15

37 DNC

36 D2_12_13

35 DNC

34 D2_10_11

33 DNC

60 OF2_1

59 DNC

58 D1_14_15

57 DNC

56 D1_12_13

55 DNC

54 D1_10_11

53 DNC

52 D1_8_9

51 DNC

50 D1_6_7

49 DNC

V DD 17 ENC+ 18 ENC– 19 CS 20 SCK 21 SDI 22 DNC 23 D2_0_1 24 DNC 25 D2_2_3 26 DNC 27 D2_4_5 28 DNC 29 D2_6_7 30 DNC 31 D2_8_9 32 TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC2188CUP#PBF L TC2188CUP#TRPBF L TC2188UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2188IUP#PBF L TC2188IUP#TRPBF L TC2188UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16

48 D1_4_5+

47 D1_4_5–

46 D1_2_3+

45 D1_2_3–

44 D1_0_1+

43 D1_0_1–

42 OVDD

40 CLKOUT+

38 D2_14_15+

37 D2_14_15–

36 D2_12_13+

35 D2_12_13–

34 D2_10_11+

33 D2_10_11–

59 OF2_1–

58 D1_14_15+

57 D1_14_15–

56 D1_12_13+

55 D1_12_13–

54 D1_10_11+

53 D1_10_11–

52 D1_8_9+

51 D1_8_9–

50 D1_6_7+

49 D1_6_7–

ENC– 19 CS 20 SCK 21 SDI 22 D2_0_1– 23 D2_0_1+ 24 D2_2_3– 25 D2_2_3+ 26 D2_4_5– 27 D2_4_5+ 28 D2_6_7– 29 D2_6_7+ 30 D2_8_9– 31 D2_8_9+ 32 TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB pin conFiguraTions

analog inpuT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l 1 to 2 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l 0.7 VCM 1.25 V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 20Msps 32 µA IIN1 Analog Input Leakage Current (No Encode) 0 < A IN+, AIN– < VDD l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 µA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode Differential Encode 0.07 0.09 ps RMS psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 550 MHz converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 16 Bits Integral Linearity Error Differential Analog Input (Note 6) l –6.5 ±2 6.5 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.5 0.9 LSB Offset Error (Note 7) l –7 ±1.5 7 mV Gain Error Internal Reference External Reference l –1.8 ±1.5 –0.5 0.8 %FS %FS Offset Drift ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±10 ppm/°C ppm/°C Gain Matching ±0.3 %FS Offset Matching ±1.5 mV T ransition Noise 3.2 LSB RMS

inTernal reFerence characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V VCM Output Temperature Drift ±25 ppm/°C VCM Output Resistance –600µA < IOUT < 1mA 4 Ω VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V VREF Output Temperature Drift ±25 ppm/°C VREF Output Resistance –400µA < IOUT < 1mA 7 Ω VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 75.3 77.1 76.9 76.4 dBFS dBFS dBFS dBFS SFDR Spurious Free Dynamic Range 2nd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS dBFS S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input l 74.9 76.9 76.8 76.5 76.4 dBFS dBFS dBFS dBFS Crosstalk 10MHz Input –110 dBc

DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.2 1.6 V V V IN Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V RIN Input Resistance (See Figure 10) 10 kΩ CIN Input Capacitance (Note 8) 3.5 pF Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD = 1.8V l 1.2 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V VIN Input Voltage Range ENC+ to GND l 0 3.6 V RIN Input Resistance (See Figure 11) 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance (Note 8) 3 pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) R OL Logic Low Output Resistance to GND V DD = 1.8V , SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance (Note 8) 3 pF DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OV DD = 1.8V VOH High Level Output Voltage IO = –500µA l 1.750 1.790 V VOL Low Level Output Voltage IO = 500µA l 0.010 0.050 V OVDD = 1.5V VOH High Level Output Voltage IO = –500µA 1.488 V VOL Low Level Output Voltage IO = 500µA 0.010 V OVDD = 1.2V VOH High Level Output Voltage IO = –500µA 1.185 V VOL Low Level Output Voltage IO = 500µA 0.010 V DIGITAL DATA OUTPUTS (LVDS MODE) V OD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l 247 350 175 454 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.250 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

power requireMenTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input Sine Wave Input l 42 50 mA mA I OVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 1.6 mA PDISS Power Dissipation DC Input Sine Wave Input, OV DD = 1.2V l 75.6 79.3 90 mW mW LVDS Output Mode V DD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l mA mA I OVDD Digital Supply Current (0V DD = 1.8V) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l mA mA P DISS Power Dissipation Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 149 218 247 mW mW All Output Modes P SLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No increase for Nap or Sleep Modes) 20 mW TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency (Note 10) l 1 20 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 500 500 ns ns t H ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 500 500 ns ns t AP Sample-and-Hold Acquisition Delay Time 0 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode Double Data Rate Mode 6.5 Cycles Cycles

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles SPI Port Timing (Note 8) t SCK SCK Period Write Mode Readback Mode, CSDO = 20pF , RPULLUP = 2k l l 250 ns ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF , RPULLUP = 2k l 125 ns TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: V DD = OVDD = 1.8V , fSAMPLE = 20MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: V DD = 1.8V , fSAMPLE = 20MHz, CMOS outputs, ENC+ = single- ended 1.8V square wave, ENC– = 0V , input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions.

Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels TiMing DiagraMs tH tD tC tL B – 6 B – 5 B – 4 B – 3 B – 2 tAP A + 1 A + 2 A + 4 A + 3 ACH 1 ANALOG INPUT ENC– ENC+ CLKOUT+ CLKOUT– D2_0 - D2_15, OF2 tAP B + 1 B + 2 B + 4 B + 3 BCH 2 ANALOG INPUT A – 6 A – 5 A – 4 A – 3 A – 2D1_0 - D1_15, OF1

2188 TD01

Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tD tD tC tC tL BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 ENC– ENC+ D1_0_1 D1_14_15 BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF B-6 OF A-6 OF B-5 OF A-5 OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 D2_0_1 D2_14_15 CLKOUT+ CLKOUT– OF2_1

2188 TD02

Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tD tD tC tC tL BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 ENC– ENC+ D1_0_1+ D1_14_15+ BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF B-6 OF A-6 OF B-5 OF A-5 OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 D2_0_1+ D2_14_15+ CLKOUT+ CLKOUT– OF2_1+ D1_0_1– D1_14_15– D2_0_1– D2_14_15– OF2_1–

2188 TD03

SPI Port Timing (Readback Mode) SPI Port Timing (Write Mode) tDH tDO tSCK tH A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

2188 TD04

Typical perForMance characTerisTics Shorted Input HistogramIntegral Non-Linearity (INL) Differential Non-Linearity (DNL) OUTPUT CODE –4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

2188 G01

–1.0 –0.4 –0.2 –0.6 –0.8 DNL ERROR (LSB) 0.4 0.2 0.6 0.8 1.0

2188 G02

2000 COUNT

2188 G03

INPUT FREQUENCY (MHz) SNR (dBFS) 50 100 150 200 250 300

2188 G04

SNR vs Input Frequency, –1dBFS, 20Msps, 2V Range 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

2188 G05

2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 20Msps, 2V Range 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 100 2ND AND 3RD HARMONIC (dBFS)

2188 G06

2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 20Msps, 1V Range SFDR vs Input Level, f IN = 70MHz, 20Msps, 2V Range INPUT LEVEL (dBFS) –80 SFDR (dBc AND dBFS) 100 130 120 110

2188 G07

IVDD vs Sample Rate, 5MHz, –1dBFS, Sine Wave Input on Each Channel SAMPLE RATE (Msps) IVDD (mA) 8 124 16 20

2188 G08

3.5mA LVDS OUTPUTS

Typical perForMance characTerisTics IOVDD vs Sample Rate, 5MHz, –1dBFS, Sine Wave Input on Each Channel SNR vs SENSE, f IN = 5MHz, –1dBFS 0 8 124 16 20 SAMPLE RATE (Msps) IOVDD (mA)

2188 G09

1.75mA LVDS 1.8V CMOS 3.5mA LVDS SENSE PIN (V) 0.6 SNR (dBFS)

2188 G10

PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to 1.9V . Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor . VCM1 (Pin 2): Common Mode Bias Output, nominally equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs to channel 1. Bypass to ground with a 0.1µF ceramic capacitor . GND (Pins 3, 6, 14): ADC Power Ground. A IN1+ (Pin 4): Channel 1 Positive Differential Analog Input. AIN1– (Pin 5): Channel 1 Negative Differential Analog Input. REFH (Pins 7, 9): ADC High Reference. See the Applica- tions Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 8, 10): ADC Low Reference. See the Applica- tions Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 11): Programming mode selection pin. Con- nect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to V DD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or V DD and not be driven by a logic signal. AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input. AIN2– (Pin 13): Channel 2 Negative Differential Analog Input. VCM2 (Pin 15): Common Mode Bias Output, nominally equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs to channel 2. Bypass to ground with a 0.1µF ceramic capacitor . ENC + (Pin 18): Encode Input. Conversion starts on the rising edge. ENC – (Pin 19): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 20): In serial programming mode, (PAR/SER = 0V), CS is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = V DD), CS controls the clock duty cycle stabilizer (See Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 21): In serial programming mode, (PAR/SER = 0V), SCK is the Serial Interface Clock Input. In the parallel programming mode (PAR/SER = V DD), SCK controls the digital output mode. (See Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 22): In serial programming mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/ SER = V DD), SDI can be used together with SDO to power down the part (see Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 41): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OV DD (Pin 42): Output Driver Supply. Bypass to ground with a 0.1µF ceramic capacitor . SDO (Pin 61): In serial programming mode, (PAR/SER = 0V), SDO is the optional Serial Interface Data Output. Data on SDO is read back from the mode control regis- ters and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V . If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = V DD), SDO can be used together with SDI to power down the part (see Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor . V REF (Pin 62): Reference Voltage Output. Bypass to ground with a 2.2µF ceramic capacitor . The output voltage is nominally 1.25V . pin FuncTions

SENSE (Pin 63): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • V SENSE. Ground (Exposed Pad Pin 65): The exposed pad must be soldered to the PCB ground. FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OV DD) D2_0 to D2_15 (Pins 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_15 is the MSB. CLKOUT – (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. D1_0 to D1_15 (Pins 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_15 is the MSB. OF2 (Pin 59): Channel 2 Over/Under Flow Digital Output. OF2 is high when an overflow or underflow has occurred. OF1 (Pin 60): Channel 1 Over/Under Flow Digital Output. OF1 is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OV DD) D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36, 38): Channel 2 Double Data Rate Digital Outputs. T wo data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT + is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47, 49, 51, 53, 55, 57, 59): Do not connect these pins. CLKOUT – (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The digital outputs normally transition at the same time as the falling and ris- ing edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. D1_0_1 to D1_14_15 (Pins 44, 46, 48, 50, 52, 54, 56, 58): Channel 1 Double Data Rate Digital Outputs. T wo data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT + is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1 (Pin 60): Over/Under Flow Digital Output. OF2_1 is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT + is low, and Channel 1 appears when CLKOUT+ is high.

DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level Is Programmable. There Is an Optional Internal 100Ω Termination Resistor Between the Pins of Each LVDS Output Pair . D2_0_1 nel 2 Double Data Rate Digital Outputs. T wo data bits are multiplexed onto each differential output pair . The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT + is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT +. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. nel 2 Double Data Rate Digital Outputs. T wo data bits are multiplexed onto each differential output pair . The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT + is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1–/OF2_1+ (Pins 59/60): Over/Under Flow Digital Output. OF2_1+ is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLK- OUT + is low, and Channel 1 appears when CLKOUT+ is high. pin FuncTions

Figure 1. Functional Block Diagram

2188 F01

• VDD

resulting in lower A/D distortion.

2188 F02

2188 F03

Figure 2. Equivalent Input Circuit. Only One of the T wo Analog Channels Is Shown Figure 3. Analog Input Circuit Using a T ransformer .

Figure 5. Recommended Front-End Circuit for Input Figure 6. Recommended Front-End Circuit for Input mode voltage can be optimally set to minimize distortion. Figure 4. Recommended Front-End Circuit for Input

2188 F04

2188 F05

2188 F06

2188 F07

Figure 7. Front-End Circuit Using a High Speed

2188 F08a

2188 F09

Figure 9. Using an External 1.25V Reference

2188 F08b

on the back side of the circuit board).

2188 F12

Figure 12. Sinusoidal Encode Drive

2188 F13

Figure 13. PECL or LVDS Encode Drive

2188 F10

Figure 10. Equivalent Encode Input Circuit

2188 F11

Figure 11. Equivalent Encode Input Circuit avoid falsely triggering the single ended encode mode. mately 500kHz, the A/D enters nap mode. to make the sampling clock have a 50% (±10%) duty cycle. The duty cycle stabilizer should not be used below 5Msps.

In full rate CMOS mode the data outputs (D1_0 to D1_15 and D2_0 to D2_15), overflow (OF2, OF1), and the data output clocks (CLKOUT +, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OV DD can range from 1.1V to 1.9V , allowing 1.2V through 1.8V CMOS logic outputs. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate CMOS Mode In Double Data Rate CMOS mode, two data bits are multi- plexed and output on each data pin. This reduces the num- ber of digital lines by seventeen, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D1_0_1, D1_2_3, D1_4_5, D2_12_13, D2_14_15), overflow (OF2_1), and the data output clocks (CLKOUT +, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OV DD can range from 1.1V to 1.9V , allowing 1.2V through 1.8V CMOS logic outputs. Note that the overflow for both ADC channels is multiplexed onto the OF2_1 pin. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate LVDS Mode In double data rate LVDS mode, two data bits are multi- plexed and output on each differential output pair . There are eight LVDS output pairs per ADC channel (D1_0_1 D2_0_1– through D2_14_15+/D2_14_15–) for the digital output data. Overflow (OF2_1 +/OF2_1–) and the data output clock (CLKOUT +/CLKOUT–) each have an LVDS output pair . Note that the overflow for both ADC channels is multiplexed onto the OF2_1 +/OF2_1– output pair . By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode volt- age. An external 100Ω differential termination resistor is required for each LVDS output pair . The termination resistors should be located as close as possible to the LVDS receiver . The outputs are powered by OV DD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V . Programmable LVDS Output Current In LVDS mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addi- tion, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver . When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either over-ranged or under-ranged. The overflow bit has the same pipeline latency as the data bits. In Full-Rate CMOS mode each ADC channel has its own overflow pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS or DDR LVDS mode the overflow for both ADC channels is multiplexed onto the OF2_1 output.

the best place to adjust the timing. signals by serially programming mode control register A2. enables phase shifts of 45° up to 315° (Figure 14). ming mode control register A4. Table 1. Output Codes vs Input Voltage

2188 F14

Figure 14. Phase Shifting CLKOUT

inductive coupling or coupling through the ground plane. programming mode control register A4. for very small analog input signals. the ground plane, reducing the digital noise. enabled by serially programming mode control register A4.

2188 F15

2188 F16

Figure 15. Functional Equivalent of Digital Output Randomizer Figure 16. Unrandomizing a Randomized Digital

channel 1 in nap mode and channel 2 operating normally. SDO (parallel programming mode). either a parallel interface or a simple serial interface. modes set by CS, SCK, SDI and SDO. Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD) complement, randomizer , alternate bit polarity. suggested values in Fig. 8, the A/D will stabilize after 2ms.

To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be writ- ten to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the timing diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. G ROUNDING AND BYP ASSING The L TC2188 requires a printed cir cuit board with a clean unbroken ground plane. A multilayer board with an in- ternal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular , care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the V DD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as pos- sible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other . Ground fill and grounded vias should be used as barriers to isolate these signals from each other . H EA T TRANSFER Most of the heat generated by the L TC2188 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. applicaTions inForMaTion

Table 3. Serial Programming Mode Register Map (PAR/SER = GND) Reset Register Will Be Random. Bits 6-0 Unused, Don’t Care Bits. Bits 7-2 Unused, Don’t Care Bits. Bits 7-4 Unused, Don’t Care Bits.

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0 Bit 7 Unused, Don’t Care Bit. Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 3 TERMON LVDS Internal T ermination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0 Bit 2 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled 1 = Digital Outputs Are Disabled and Have High Output Impedance Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels). Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = Full-Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bit 7-6 Unused, Don’t Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output T est Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF , D15-D0 Alternate Between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010 111 = Alternating Output Pattern. OF , D15-D0 Alternate Between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111 Note: Other Bit Combinations Are not Used Bit 2 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binar y Bit 1 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP T wo’ s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = T wo’s Complement Data Format applicaTions inForMaTion

D1_4_5+ D1_4_5– D1_2_3+ D1_2_3– D1_0_1+ D1_0_1– OVDD OGND CLKOUT+ CLKOUT– D2_14_15+ D2_14_15– D2_12_13+ D2_12_13– D2_10_11+ D2_10_11– 65PAD VDD SENSE VREF SDO OF2_1+ OF2_1– D1_14_15+ D1_14_15– D1_12_13+ D1_12_13– D1_10_11+ D1_10_11– D1_8_9+ D1_8_9– D1_6_7+ D1_6_7– VDD ENC+ ENC– CS SCK SDI D2_0_1 D2_0_1+ D2_2_3– D2_2_3+ D2_4_5– D2_4_5+ D2_6_7– D2_6_7+ D2_8_9– D2_8_9+ C19 0.1µF SDO V DD VDD VCM1 GND A IN1+ AIN1– GND REFH REFL REFH REFL PAR/SER A IN2+ AIN2– GND V CM2 VDD C20 0.1µF C18 0.1µF VDD PAR/SER C17 1µF C23 2.2µF C37 0.1µF DIGITAL OUTPUTS DIGITAL OUTPUTS OV DD SPI BUS C67 0.1µF C78 0.1µF C79 0.1µF R51 100/uni03A9 L TC2188 ENCODE CLOCK CN1 AIN2+ AIN2– AIN1+ AIN1– C15 0.1µF C21 0.1µF SENSE

2188 TA02

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9 .00 ± 0.10 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE PIN 1 TOP MARK (SEE NOTE 5) 0.40 ± 0.10 64 63 BOTTOM VIEW—EXPOSED PAD 7.15 ± 0.10 7.15 ± 0.10

7.50 REF

(4-SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UP64) QFN 0406 REV C RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 (4 SIDES) 7.15 ±0.05 7.15 ±0.05 0.25 ±0.05 C = 0.35 64-Lead Plastic QFN (9mm × 9mm) (Reference L TC DWG # 05-08-1705 Rev C)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2012 LT 0312 • PRINTED IN USA relaTeD parTs PART NUMBER DESCRIPTION COMMENTS ADCs L TC2259-14/L TC2260-14/ L TC2261-14 14-Bit, 80Msps/105Msps/125Msps 1.8V ADCs, Ultralow Power 89mW/106mW/127mW , 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-40 L TC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW , 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-40 L TC2266-14/L TC2267-14/ L TC2268-14 14-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW , 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 L TC2266-12/L TC2267-12/ L TC2268-12 12-Bit, 80Msps/105Msps/125Msps 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW , 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 L TC2208 16-Bit, 130Msps 3.3V ADC 1250mW , 77.7dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 L TC2207/L TC2206 16-Bit, 105Msps/80Msps 3.3V ADCs 900mW/725mW , 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 L TC2217/L TC2216 16-Bit, 105Msps/80Msps 3.3V ADCs 1190mW/970mW , 81.2dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 RF Mixers/Demodulators L TC5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator L TC5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports L TC5557 400MHz to 3.8GHz High Linearity Downconverting Mixer Operation, Integrated T ransformer L TC5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator , Integrated RF and LO T ransformer Amplifiers/Filters L TC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 L TC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V , 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier , 3mm × 4mm QFN-20 L TC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Fixed Gain 10V/V , 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier , 3mm × 4mm QFN-20 L TC6605-7/L TC6605-10/ L TC6605-14 Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22 Signal Chain Receivers LT M ®9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers L TC2188: Integral Non-Linearity (INL) OUTPUT CODE –4.0 –3.0 –2.0 –1.0INL ERROR (LSB) 1.0 4.0 3.0 2.0 16384 32768 49152 65536

2188 TA03