LTM9001CV-GAPBF

LTM9001-GA LINER

Document overview

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Technical content

FeaTures

applicaTions

DescripTion

The L TM®9001 is an integrated System in a Package (SiP) that includes a high-speed 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The amplifier allows either AC- or DC- coupled input drive. A lowpass or bandpass filter network can be implemented with various bandwidths. Contact Linear Technology regarding semi-custom configurations, (see Table 1.) The L TM9001 is perfect for IF receivers in demanding communications applications, with AC performance that includes 78dBFS noise floor and 87dB spurious free dynamic range (SFDR) at 5MHz (L TM9001-GA). The digital outputs are single-ended CMOS. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V . An optional clock duty cycle stabilizer allows high perfor- mance at full speed with a wide range of clock duty cycles. Simplified IF Receiver Channel n Integrated 16-Bit, High-Speed ADC, Passive Filter and Fixed Gain Differential Amplifier n Up to 300MHz IF Range Lowpass and Bandpass Filter Versions n Low Noise, Low Distortion Amplifiers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50Ω, 200Ω or 400Ω Input Impedance n 78dB SNR, 87dB SFDR (L TM9001-GA) n Integrated Bypass Capacitance, No External Components Required n Optional Internal Dither n Optional Data Output Randomizer n 3.3V Single Supply n Power Dissipation: 550mW (L TM9001-GA) n Clock Duty Cycle Stabilizer n 11.25mm × 11.25mm × 2.32mm LGA Package n Telecommunications n High Sensitivity Receivers n Imaging Systems n Spectrum Analyzers n ATE 64k Point FFT, fIN = 5MHz, –1dBFS, PGA = 0 9001-GA TA01 CLKOUT OFLO VCC VDD = 3.3V CLK ADC CONTROL PINS DIFFERENTIAL FIXED GAIN AMPLIFIER 16-BIT 25Msps ADCRF IN– IN+ L TM9001-GA SENSE GND D15 0VDD = 0.5V TO 3.6V OGND SAW ANTI-ALIAS FIL TER L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. FREQUENCY (MHz) AMPLITUDE (dBFS) –10 –20 9001-GA TA01a –130 –60 –70 –80 –90 –100 –110 –120 –40 –50 –30 L TM9001-GA HD2 HD3

pin conFiguraTionabsoluTe MaxiMuM raTings Digital Input Voltage Digital Input Voltage Operating Temperature Range (Notes 1, 2) orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM9001CV-GA#PBF L TM9001CV-GA#PBF L TM9001V-GA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C L TM9001IV-GA#PBF L TM9001IV-GA#PBF L TM9001V-GA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS GDIFF Gain DC, L TM9001-GA fIN = 5MHz l 7.2 8 8.8 dB G TEMP Gain Temperature Drift VIN = Maximum, (Note 3) 2 mdB/°C VINCM Input Common Mode Voltage Range (IN+ + IN–)/2 1.0–1.6 V VIN Input Voltage Range at –1dBFS L TM9001-GA at 5MHz 900 mVP-P RINDIFF Differential Input Impedance L TM9001-GA 400 Ω CINDIFF Differential Input Capacitance Includes Parasitic 1 pF VOS Offset Error (Note 6) Including Amplifier and ADC (L TM9001-GA) l –50 –10 mV Offset Drift Including Amplifier and ADC ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±15 ppm/°C ppm/°C The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) IN– J H G F E D C B A 2 3 4 LGA PACKAGE T JMAX = 125°C, QJA = 15°C/W, QJC = 19°C/W QJA DERIVED FROM 60mm s 70mm PCB WITH 4 LAYERS WEIGHT = 0.71g 5 6 7 8 9 DATA TOP VIEWALL ELSE = GND CONTROL OGND OVDD VCC DNC VDD OGNDCONTROL OVDD OGND IN+ CLK

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMRR Common Mode Rejection Ratio 60 dB ISENSE SENSE Input Leakage Current 0V < SENSE < VDD (Note 9) l –3 3 µA IMODE MODE Pin Pull-Down Current to GND 10 µA IOE OE Pin Pull-Down Current to GND 10 µA tAP Sample-and-Hold Acquisition Delay Time 1 ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 70 fsRMS elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 16 Bits Integral Linearity Error Differential Input L TM9001-GA (Note 5) l ±2.4 ±8 LSB Differential Linearity Error Differential Input l ±0.3 ±1 LSB T ransition Noise External Reference 1 LSBRMS converTer characTerisTics The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 76 78 75.4 dBFS dBFS SFDR Spurious Free Dynamic Range, 2nd or 3rd Harmonic 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 76 87 89.8 dBc dBc SFDR Spurious Free Dynamic Range 4th or Higher 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 91 100 dBc dBc S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 75 77.4 74.8 dBFS dBFS SFDR Spurious Free Dynamic Range at –15dBFS, Dither “OFF” 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 91 105 107.5 dBFS dBFS SFDR Spurious Free Dynamic Range at –15dBFS, Dither “ON” 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) l 93 107 109 dBFS dBFS IMD3 Third Order Intermodulation Distortion; 1MHz Tone Spacing, 2 Tones at –7dBFS fIN = 5MHz 85 dB IIP3 Equivalent Third Order Input Intercept Point,

2 Tone

fIN = 5MHz 36.5 dBm DynaMic accuracy The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) power requireMenTs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Inputs (DITH, PGA, ADCSHDN, RAND, CLK, OE) VIH High Level Input Voltage VDD = 3.3V l 2 V VIL Low Level Input Voltage VDD = 3.3V l 0.8 V IIN Input Current VIN = 0V to VDD l ±10 µA CIN Input Capacitance (Note 7) 1.5 pF Logic Inputs (AMPSHDN) VIH High Level Input Voltage VCC = 3.3V l 2 V VIL Low Level Input Voltage VCC = 3.3V l 0.8 V IIH Input High Current VIN = 2V 1.3 µA IIL Input Low Current VIN = 0.8V 0.1 µA CIN Input Capacitance (Note 7) 1.5 pF Logic Outputs OVDD = 3.3V VOH High Level Output Voltage VDD = 3.3V , IO = –10µA VDD = 3.3V , IO = –200µA l 3.1 3.299 3.29 V V VOL Low Level Output Voltage VDD = 3.3V , IO = 10µA VDD = 3.3V , IO = 1.6mA l 0.01 0.1 0.4 V V ISOURCE Output Source Current VOUT = 0V –50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA OVDD = 2.5V VOH High Level Output Voltage VDD = 3.3V , IO = –200µA 2.49 V VOL Low Level Output Voltage VDD = 3.3V , IO = 1.6mA 0.1 V OVDD = 1.8V VOH High Level Output Voltage VDD = 3.3V , IO = –200µA 1.79 V VOL Low Level Output Voltage VDD = 3.3V , IO = 1.6µA 0.1 V DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD ADC Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V VCC Amplifier Supply Voltage l 2.85 3.5 V ICC Amplifier Supply Current l 100 136 mA PSHDN Total Shutdown Power AMPSHDN = ADCSHDN = 3.3V 10 mW OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V IVDD Analog Supply Current L TM9001-GA l 66 80 mA PDISS ADC Power Dissipation L TM9001-GA l 220 265 mW PDISS(TOTAL) Total Power Dissipation L TM9001-GA 550 mW

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency (Note 8) L TM9001-GA l 1 25 MHz tL CLK Low Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 18.9 500 500 ns ns tH CLK High Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 18.9 500 500 ns ns CMOS Output Mode tD CLK to DATA Delay (Note 7) l 1.3 3.1 4.9 ns tC CLK to CLKOUT Delay (Note 7) l 1.3 3.1 4.9 ns tSKEW DATA to CLKOUT Skew (tC – tD) (Note 7) l –0.6 0 0.6 ns Data Latency 7 Cycles The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) TiMing characTerisTics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: Gain is measured from IN+/IN– through the ADC. Note 4: VCC = VDD = 3.3V, fSAMPLE = maximum sample frequency, input range = –1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the voltage applied between the IN+ and IN– pins required to make the output code flicker between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: Leakage current will experience transient at power up. Keep resistance <1kΩ.

N – 7 N – 6 N – 5 N – 4 N – 3 CLK CLKOUT+ CLKOUT– D0-D15, OF 9001GA TD03 N + 1 N + 2 N + 4 N + 3N

Typical perForMance characTerisTics Integral Non-Linearity (INL) vs Output Code Differential Non-Linearity (DNL) vs Output Code 64k Point FFT, fIN = 5MHz, –15dBFS, PGA = 0, RAND “0n”, Dither “On” 64k Point FFT, fIN = 5MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 64k Point FFT, fIN = 5MHz, –1dBFS, PGA = 1, RAND “Off”, Dither “Off” IF Frequency Response Input Impedance vs Frequency SNR vs Frequency FREQUENCY (MHz) FIL TER GAIN (dB) 9001-GA G01 –10 0 1 10 100 FREQUENCY (MHz) IMPEDANCE MAGNITUDE (/uni03A9) 400 350 300 250 150 200 100 9001-GA G02 IMPEDANCE PHASE (°C) –16 –24 –32 1 10 100 1000 MAGNITUDE PHASE FREQUENCY (MHz) SNR (dB) 9001-GA G03 0 1 10 100 OUTPUT CODE INL ERROR (LSB) 4.0 3.5 3.0 2.5 1.5 1.0 0.0 0.5 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 – 3.0 – 3.5 2.0 9001-GA G04 – 4.0 0 16384 32768 49152 65536 OUTPUT CODE DNL ERROR (LSB) 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 9001-GA G05 –1.0 0 16384 32768 49152 65536 FREQUENCY (MHz) AMPLITUDE (dBFS) –10 –20 9001-GA G06 –130 –60 –70 –80 –90 –100 –110 –120 –40 –50 –30 FREQUENCY (MHz) AMPLITUDE (dBFS) –10 –20 9001-GA G07 –130 –60 –70 –80 –90 –100 –110 –120 –40 –50 –30 HD2 HD3 FREQUENCY (MHz) AMPLITUDE (dBFS) –10 –20 9001-GA G08 –130 –60 –70 –80 –90 –100 –110 –120 –40 –50 –30 HD2 HD3 FREQUENCY (MHz) 0.0 AMPLITUDE (dBFS) –80 –90 –60 –70 –40 –50 –20 –30 –10 5.0 9001-GA G09 –100 –110 –120 –130 2.5 7.5 10 12.5 64k Point 2-Tone FFT, fIN = 4.9MHz, and fIN = 5.1MHz, –7dBFS Per Tone, PGA = 0, RAND “Off”, Dither “Off”

VCC (Pins E1, E2): 3.3V Analog Supply Pin for Amplifier. The voltage on this pin provides power for the amplifier stage only and is internally bypassed to GND. VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This supply is internally bypassed to GND. OVDD (Pins A6, G9): Positive Supply for the ADC Output Drivers. This supply is internally bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Analog Inputs IN+ (Pin G1): Positive (Noninverting) Amplifier Input. IN– (Pin H1): Negative (Inverting) Amplifier Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They may be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. NC (See Pin Configuration Table for Pin Locations): No Connect. CLK (Pin B1): Clock Input. The sampled analog input is held on the falling edge of CLK. The output data may be latched on the rising edge of CLK. Control Inputs SENSE (Pin J3): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set the maximum full-scale input range. AMPSHDN (Pin H3): Power Shutdown Pin for Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with typically 3mA amplifier supply current. MODE (Pin G3): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3V DD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin F3): Digital Output Randomization Selection Pin. RAND = low results in normal operation. RAND = high selects D1 to D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin E3): Programmable Gain Amplifier Control Pin. PGA = low selects the normal (maximum) input voltage range. PGA = high selects a 3.5dB reduced input range for slightly better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = low results in normal operation. ADCSHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin A3): Internal Dither Enable Pin. DITH = low disables internal dither . DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. OE (Pin F5): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. Digital Outputs D0 to D15 (See Pin Configuration Table for Pin Locations): Digital Outputs. D15 is the MSB and D0 the LSB. CLKOUT+ (Pin E7): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. CLKOUT– (Pin E6): Data Valid Output. CLKOUT – will toggle at the sample rate. Latch the data on the falling edge of CLKOUT–. OF (Pin G5): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. pin FuncTions

J GND GND SENSE GND D14 NC D12 NC OGND H IN– GND AMPSHDN GND NC NC NC NC D11 G IN+ GND MODE GND OF D15 D13 OGND OVDD F GND GND RAND GND OE NC D9 NC D10 E VCC VCC PGA GND VDD CLKOUT– CLKOUT NC D8 D GND GND DNC GND VDD NC D6 NC D7 C NC GND DNC GND D0 NC D4 NC D5 B CLK GND ADCSHDN GND NC NC D1 D3 NC A GND GND DITH GND OGND OVDD NC D2 OGND Top View of LGA Pinout (Looking Through Component) 9001-GA LGA01 IN– J H G F E D C B A 2 3 4 5 6 7 8 9 DATA TOP VIEWALL ELSE = GND CONTROL OGND OVDD VCC DNC VDD OGNDCONTROL OVDD OGND IN+ CLK

CLKOUT– VDD OVDD ADC- SHDN RAND MODE OE DITH OGND CLK INPUT AMPLIFIER PGA ADC REFERENCE INPUT S/H CONTROL LOGIC OUTPUT DRIVERS LOW JITTER CLOCK DRIVER INTERNAL CLOCK SIGNALS IN+ IN– SENSE AMPSHDN VCC VCC D0…D15 OF ANTI-ALIAS FIL TER FIRST PIPELINED ADC STAGE VOL TAGE REFERENCE DITHER SIGNAL GENERATOR SHIFT REGISTER AND ERROR CORRECTION SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND PGA RANGE SELECT VDD

DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD= –20Log (V22 + V32 + V42 +...Vn2 )/V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Aperture Delay Time Aperture Delay is the time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and-hold circuit. Or, for single-ended CLK versions, the time from when CLK reaches 0.45 of V DD to the instant that the input signal is held by the sample- and-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) The L TM9001 is an integrated System in a Package (SiP) µModule® receiver that includes a high-speed, sampling 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It µModule is a registered trademark of Linear Technology Corporation.

Figure 1. Basic Functional Elements versions which have a different pin assignment. no difference in distortion performance. the overall gain of the subsystem 7.8dB. functional elements as shown in Figure 1. bandpass filter designed for 162.5MHz ±25MHz.

Table 1. Semi-Custom Options

The ADC has a delayed version of the encode input available as a digital output. Both a non-inverted version, CLKOUT+, and an inverted version, CLKOUT –, are provided. The CLKOUT pins can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated as CLKOUT+ falls and CLKOUT– rises. Data may be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT–. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits (see figure 10). To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits (see figure 11). The LSB, OF and CLKOUT output are not affected. The output randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any logic voltage up to the 3.6V . OGND can be powered with any voltage from ground up to 1V and must be less than OV DD. The logic outputs will swing between OGND and OVDD. Internal Dither The L TM9001 is a 16-bit receiver subsystem with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.

ADC, as compared to the noise floor with dither off. within 10% will give the best results. are separated as much as possible. be required if power supply noise is significant. minimize capacitance and to minimize noise pickup. Figure 12. Functional Equivalent Block Diagram of Internal Dither Circuit

Most of the heat generated by the L TM9001 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. Recommended Layout The high integration of the L TM9001 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary, see Figures 13 to 16.

• Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the L TM9001, but can be connected on the PCB underneath the part to provide a common return path.
• Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies.
• Separate analog and digital traces as much as possible, using vias to create high frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the L TM9001. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The µModule LGA Packaging Care and Assembly Instructions is available at http://www.linear . com/designtools/packaging/uModule_Instructions. The L TM9001 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb- free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www. linear .com/designtools/leadfree/mat_dec.jsp.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion 81-Lead (11.25mm × 11.25mm × 2.32mm) (Reference L TC DWG # 05-08-1809 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 81 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE SYMBOL aaa bbb TOLERANCE 0.15 0.10 11.250 BSC PACKAGE TOP VIEW LGA 81 1107 REV A 11.250 BSC PAD 1 CORNER PADS SEE NOTES X Y aaa Z aaa Z 2.17 – 2.47 DETAIL A PACKAGE SIDE VIEW DETAIL A SUBSTRATEMOLD CAP 0.27 – 0.37 1.90 – 2.10 bbb Z Z 1.27 BSC 0.605 – 0.665 0.25 s 45° CHAMFER 0.605 – 0.665 10.160 BSC 10.160 BSC PAD 16789 5 1234 PACKAGE BOTTOM VIEW 5.080 5.080 3.810 3.810 2.540 2.540 0.000 1.270 1.270 0.9525 1.5875 5.080 2.540 3.810 5.080 3.810 1.270 2.540 1.270 0.000 1.5875 0.9525 SUGGESTED PCB LAYOUT TOP VIEW L TMXXXXXX µModule TRAY PIN 1 BEVEL COMPONENT PIN “A1” PACKAGE IN TRAY LOADING ORIENTATION J H B A D C E F G

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2008 LT 0809 • PRINTED IN USA relaTeD parTs PART NUMBER DESCRIPTION COMMENTS L TC2202 16-Bit, 10Msps ADC 140mW, 81.6dB SNR, 100dB SFDR L TC2203 16-Bit, 25Msps ADC 220mW, 81.6dB SNR, 100dB SFDR L TC2204 16-Bit, 40Msps ADC 480mW, 79.1dB SNR, 100dB SFDR L TC2205 16-Bit, 65Msps ADC 610mW, 79dB SNR, 100dB SFDR L TC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR L TC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR L TC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR L TC2209 16-Bit, 160Msps ADC 1450mW, 77.1dB SNR, 100dB SFDR L TC6400-8/L TC6400-14/ L TC6400-20/L TC6400-26 Low Noise, Low Distortion Differential Amplifier for 300MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB 3V , 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF L TC6401-8/L TC6401-14/ L TC6401-20/L TC6401-26 Low Noise, Low Distortion Differential Amplifier for 140MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB 3V , 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF 75/uni03A9RS 50/uni03A9 9001-GA TA02 GROUND– REFERENCED SOURCE +– 75/uni03A9 51.1/uni03A9 3.3V VCC L TM9001-GA IN+ IN– L TM9001 with Ground-Referenced Single-Ended Input Typical applicaTion