LTM9001

Linear Technology

16-Bit IF/Baseband Receiver Subsystem

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LTM9001 LINER

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

The L TM®9001 is an integrated System in a Package (SiP) that includes a high-speed 16-bit A/D converter, matching network, anti-aliasing ﬁ lter and a low noise, differential ampliﬁ er with ﬁ xed gain. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The ampliﬁ er allows either AC- or DC-coupled input drive. A low-pass or bandpass ﬁ lter network can be implemented with various bandwidths. Contact Linear Technology regarding semi-custom con- ﬁ gurations. The L TM9001 is perfect for IF receivers in demanding communications applications, with AC performance that includes 72dBFS noise ﬂ oor and 82dB spurious free dy- namic range (SFDR) at 162.5MHz (L TM9001-AA). The digital outputs can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V . The differential ENC + and ENC– inputs may be driven with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. Simpliﬁ ed IF Receiver Channel n Integrated 16-Bit, High-Speed ADC, Passive Filter and Fixed Gain Differential Ampliﬁ er n Up to 300MHz IF Range Low-Pass and Bandpass Filter Versions n Low Noise, Low Distortion Ampliﬁ ers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50 Ω, 200Ω or 400Ω Input Impedance n 72dB SNR, 82dB SFDR (L TM9001-AA) n Integrated Bypass Capacitance, No External Components Required n Optional Internal Dither n Optional Data Output Randomizer n LVDS or CMOS Outputs n 3.3V Single Supply n Power Dissipation: 1.65W n Clock Duty Cycle Stabilizer n 11.25mm × 11.25mm × 2.32mm LGA Package n Telecommunications n High Sensitivity Receivers n Cellular Base Stations n Spectrum Analyzers L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 64k Point FFT , FIN = 162.4MHz, –1dBFS, PGA = 1

9001 TA01

VCC VDD = 3.3V ENC+ ENC– ADC CONTROL PINS DIFFERENTIAL FIXED GAIN AMPLIFIER 16-BIT 130Msps ADCRF IN IN+ L TM9001 SENSE GND D15 0VDD = 0.5V TO 3.6V OGND CMOS OR LVDS SAW ANTI-ALIAS FIL TER FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 TA01b

–100 –120 4096 20480 28672 HD2HD3

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Digital Input Voltage Digital Input Voltage Operating Temperature Range (Notes 1, 2) ORDER INFORMATION LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM9001CV-AA#PBF L TM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C L TM9001IV-AA#PBF L TM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C L TM9001CV-BA#PBF L TM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C L TM9001IV-BA#PBF L TM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS GDIFF Gain DC, L TM9001-AA fIN = 162.5MHz (Note 3) l 19.1 19.7 20.3 dB dB DC, L TM9001-BA f IN = 140MHz (Note 3) l 7.1 8.2 7.8 9.4 dB dB GTEMP Gain Temperature Drift VIN = Maximum, (Note 3) 2 mdB/°C VINCM Input Common Mode Voltage Range (IN + + IN–)/2 1.0–1.6 V VIN Input Voltage Range at –1dBFS L TM9001-AA at 162.5MHz L TM9001-BA at 140MHz 233 820 mV P-P mVP-P The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) IN– J H G F E D C B A 234 LGA PACKAGE T JMAX = 125°C, θJA = 15°C/W, θJC = 19°C/W θJA DERIVED FROM 60mm × 70mm PCB WITH 4 LAYERS WEIGHT = 0.71g 56789 DATA TOP VIEWALL ELSE = GND CONTROL OGND OVDD VCC DNC VDD OGNDCONTROL OV DD OGND ENC+ IN+ ENC–

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RINDIFF Differential Input Impedance L TM9001-AA L TM9001-BA 200 400 Ω Ω CINDIFF Differential Input Capacitance Includes Parasitic 1 pF VOS Offset Error (Note 6) Including Ampliﬁ er and ADC (L TM9001-AA) Including Ampliﬁ er and ADC (L TM9001-BA) l l –20 –3.2 –10 –0.5 –0.5 mV mV Offset Drift Including Ampliﬁ er and ADC ±10 μV/°C Full-Scale Drift Internal Reference External Reference ±30 ±15 ppm/°C ppm/°C CMRR Common Mode Rejection Ratio 60 dB ISENSE SENSE Input Leakage Current 0V < SENSE < V DD l –3 3 μA IMODE MODE Pin Pull-Down Current to GND 10 μA ILVDS LVDS Pin Pull-Down Current to GND 10 μA tAP Sample-and-Hold Acquisition Delay Time 1 ns tJITTER Sample-and-Hold Acquisition Delay Time Jitter 70 fs RMS ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 16 Bits Integral Linearity Error Differential Input L TM9001-AA (Notes 5, 7) Differential Input L TM9001-BA (Notes 5, 7) l l ±2.4 ±8 ±10 LSB LSB Differential Linearity Error Differential Input (Notes 5, 7) l ±0.3 ±1 LSB T ransition Noise External Reference 1 LSB RMS CONVERTER CHARACTERISTICS The l indicates speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA l 67.2 68.5 dBFS dBFS 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA l 67 69.2 67.2 dBFS dBFS SFDR Spurious Free Dynamic Range, 2nd or 3rd Harmonic 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA l 72 dBc dBc 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA l 64 72 dBc dBc SFDR Spurious Free Dynamic Range 4th or Higher 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA l 86 dBc dBc 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA l 86 95 104 dBc dBc DYNAMIC ACCURACY The l indicates speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC+, ENC–) VID Differential Input Voltage l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set 1.2 1.6 3.1 V V RIN Input Resistance 100 Ω CIN Input Capacitance (Note 7) 3 pF Logic Inputs (DITH, PGA, ADCSHDN, RAND) V IH High Level Input Voltage V DD = 3.3V l 2V VIL Low Level Input Voltage V DD = 3.3V l 0.8 V IIN Input Current V IN = 0V to VDD l ±10 μA CIN Input Capacitance (Note 7) 1.5 pF Logic Inputs (AMPSHDN) V IH High Level Input Voltage V CC = 3.3V l 2V VIL Low Level Input Voltage V CC = 3.3V l 0.8 V IIH Input High Current V IN = 2V 1.3 μA IIL Input Low Current V IN = 0.8V 0.1 μA CIN Input Capacitance (Note 7) 1.5 pF Logic Outputs (CMOS Mode) OV DD = 3.3V VOH High Level Output Voltage V DD = 3.3V , IO = –10μA VDD = 3.3V , IO = –200μA l 3.1 3.299 3.29 V V VOL Low Level Output Voltage V DD = 3.3V , IO = 10μA VDD = 3.3V , IO = 1.6mA l 0.01 0.1 0.4 V V DIGITAL INPUTS AND OUTPUTS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) DYNAMIC ACCURACY The l indicates speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N+D) Signal-to-Noise Plus Distortion Ratio 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA l 67 71.4 dBFS dBFS 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA l 64 67.5 66.4 dBFS dBFS SFDR Spurious Free Dynamic Range at –25dBFS, Dither “OFF” 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA dBFS dBFS Spurious Free Dynamic Range at –15dBFS, Dither “OFF” 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA dBFS dBFS SFDR Spurious Free Dynamic Range at –25dBFS, Dither “ON” 162.5MHz Input (PGA = 0) L TM9001-AA 162.5MHz Input (PGA = 1) L TM9001-AA l 90 100 dBFS dBFS Spurious Free Dynamic Range at –15dBFS, Dither “ON” 140MHz Input (PGA = 0) L TM9001-BA 140MHz Input (PGA = 1) L TM9001-BA l 90 95 dBFS dBFS IMD3 Third Order Intermodulation Distortion; 1MHz Tone Spacing, 2 Tones at –7dBFS fIN = 162.5MHz L TM9001-AA fIN = 140MHz L TM9001-BA –78 –84 dB dB IIP3 Equivalent Third Order Input Intercept Point,

2 Tone

fIN = 162.5MHz L TM9001-AA fIN = 140MHz L TM9001-BA 29.2 dBm dBm

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) POWER REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD ADC Analog Supply Voltage (Note 9) l 3.135 3.3 3.465 V VCC Ampliﬁ er Supply Voltage 2.85 3.5 V ICC Ampliﬁ er Supply Current l 100 136 mA PSHDN Total Shutdown Power AMPSHDN = ADCSHDN = 3.3V 10 mW Standard LVDS Output Mode OV DD Output Supply Voltage (Note 9) l 3 3.3 3.6 V IVDD Analog Supply Current L TM9001-AA L TM9001-BA l l 400 465 500 550 mA mA IOVDD Output Supply Current l 74 90 mA PDISS Power Dissipation L TM9001-AA L TM9001-BA l l 1564 1779 1947 2112 mW mW Low Power LVDS Output Mode OVDD Output Supply Voltage (Note 9) l 3 3.3 3.6 V IVDD Analog Supply Current L TM9001-AA L TM9001-BA l l 400 465 500 550 mA mA IOVDD Output Supply Current l 41 50 mA PDISS Power Dissipation L TM9001-AA L TM9001-BA l l 1455 1670 1815 1980 mW mW CMOS Output Mode OVDD Output Supply Voltage (Note 9) l 0.5 3.6 V IVDD Analog Supply Current L TM9001-AA L TM9001-BA l l 380 460 450 530 mA mA DIGITAL INPUTS AND OUTPUTS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISOURCE Output Source Current V OUT = 0V –50 mA ISINK Output Sink Current V OUT = 3.3V 50 mA OVDD = 2.5V VOH High Level Output Voltage V DD = 3.3V , IO = –200μA 2.49 V VOL Low Level Output Voltage V DD = 3.3V , IO = 1.6mA 0.1 V OVDD = 1.8V VOH High Level Output Voltage V DD = 3.3V , IO = –200μA 1.79 V VOL Low Level Output Voltage V DD = 3.3V , IO = 1.6μA 0.1 V Logic Outputs (LVDS Mode) Standard LVDS V OD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V Low Power LVDS V OD Differential Output Voltage 100Ω Differential Load l 125 175 250 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency (Note 9) L TM9001-AA L TM9001-BA l l 130 160 MHz MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off (L TM9001-AA) Duty Cycle Stabilizer Off (L TM9001-BA) Duty Cycle Stabilizer On (L TM9001-AA) Duty Cycle Stabilizer On (L TM9001-BA) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns t H ENC High Time (Note 7) Duty Cycle Stabilizer Off (L TM9001-AA) Duty Cycle Stabilizer Off (L TM9001-BA) Duty Cycle Stabilizer On (L TM9001-AA) Duty Cycle Stabilizer On (L TM9001-BA) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns LVDS Output Mode (Standard and Low Power) t D ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (t C – tD) (Note 7) l 4.3 10 ns tRISE Output Rise Time 0.5 ns tFALL Output Fall Time 0.5 ns Data Latency 7 Cycles CMOS Output Mode t D ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns tSKEW DATA to CLKOUT Skew (t C – tD) (Note 7) l 4.3 10 ns Data Latency Full Rate CMOS Demuxed Cycles Cycles The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) TIMING CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4) POWER REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PDISS ADC Power Dissipation L TM9001-AA L TM9001-BA l l 1320 1584 1650 1914 mW mW PDISS(TOTAL) Total Power Dissipation L TM9001-AA L TM9001-BA 1650 1914 mW mW Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: Gain is measured from IN +/IN– through the ADC. The ampliﬁ er provides approximately 20dB of gain and the ﬁ lter has 1dB loss (L TM9001-AA). Note 4: V CC = VDD = 3.3V , fSAMPLE = maximum sample frequency, differential ENC+/ENC– = 2VP-P with 1.6V common mode, input range = –1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless otherwise noted. Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from a “best ﬁ t straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the voltage applied between the IN + and IN– pins required to make the output code ﬂ icker between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Ampliﬁ er dynamic performance tests are done from IN +/IN– through the DNC pins without using the ADC. Note 9: Recommended operating conditions.

N – 7 N – 6 N – 5 N – 4 N – 3 ANALOG INPUT ENC– ENC+ CLKOUT– CLKOUT+ D0-D15, OF

9001 TD01

All Outputs are Differential and Have LVDS Levels TIMING DIAGRAM Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT tH tD tC tL N – 7 N – 6 N – 5 N – 4 N – 3 ENC– ENC+ CLKOUTA CLKOUTB DA0-DA15, OFA DB0-DB15, OFB

9001 TD02

Demultiplexed CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tH tD tD tC tL N – 8 N – 6 N – 4 N – 7 N – 5 N – 3 ENC– ENC+ CLKOUTA CLKOUTB DA0-DA15, OFA DB0-DB15, OFB

9001 TD03

TYPICAL PERFORMANCE CHARACTERISTICS Best Fit Integral Non-Linearity (INL) vs Output Code Differential Non-Linearity (DNL) vs Output Code 64k Point FFT, FIN = 162.4MHz, –1dBFS, PGA = 0 64k Point FFT, FIN = 162.4MHz, –1dBFS, PGA = 1 64k Point 2-Tone FFT, FIN = 161.5MHz, and 163.5MHz, –7dBFS, PGA = 0 IF Frequency Response Input Impedance vs Frequency Shorted Inputs Histogram with 130k Samples FREQUENCY (MHz) 120 FIL TER GAIN (dB) 150 170 200

9001 G01

–10 130 140 160 180 190 FREQUENCY (MHz) IMPEDANCE MAGNITUDE (Ω) IMPEDANCE PHASE (deg) 150 100 200 250 0 –45 –90 10010 1000

9001 G02

9001 G03

INL ERROR (LSB) 49152

9001 G04

DNL ERROR (LSB) 0.1 0.3 0.4 0.2 0.5 49152

9001 G05

–0.1 –0.2 –0.3 –0.4 –0.5 16384 32768 6553 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G06

–100 –120 4096 20480 28672 HD3 HD2 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G07

–100 –120 4096 20480 28672 HD2HD3 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G08

–100 –120 4096 20480 28672 (L TM9001-AA)

64k Point 2-Tone FFT, FIN = 161.5MHz, and 163.5MHz, –15dBFS, PGA = 0 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT, FIN = 162.4MHz, –15dBFS, PGA = 0, Dither “Off” 64k Point FFT, FIN = 162.4MHz, –15dBFS, PGA = 0, Dither “On” SFDR vs Input Level, FIN = 162.4MHz, PGA = 0, Dither = “Off” SFDR vs Input Level, FIN = 162.4MHz, PGA = 0, Dither = “On” SFDR and SNR vs Sample Rate, FIN = 162.4MHz, –1dBFS, PGA = 0 SFDR vs Input Common-Mode Voltage, FIN = 162.4MHz, –1dBFS, PGA = 0 SFDR vs VCC Supply Voltage, FIN = 162.4MHz, –1dBFS, PGA = 0 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G09

–100 –120 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G10

–100 –120 4096 20480 28672 FFT BIN NUMBER (32k TOTAL) AMPLITUDE (dBFS)–80 –60 –40 –20 12288

9001 G11

–100 –120 4096 20480 28672 INPUT LEVEL (dBFS) –90 SFDR (dBc AND dBFS) 100 120 140 –60 –40

9001 G12

INPUT COMMON-MODE VOL TAGE (V) 0.5 SFDR (dBc) 2.0 3.0

9001 G15

1.0 1.5 2.5 INPUT COMMON-MODE VOL TAGE (V) 2.8 SFDR (dBc) 78.0 78.5 79.0 79.5 80.0 80.5 81.0 3.1 3.5

9001 G16

77.5 77.0 76.5 76.0 75.5 INPUT LEVEL (dBFS) –90 SFDR (dBc AND dBFS) 100 120 140 –60 –40

9001 G13

ADC SAMPLE RATE (Msps) SFDR (dBc) AND SNR (dBFS) 150 250

9001 G14

(L TM9001-AA)

TYPICAL PERFORMANCE CHARACTERISTICS(L TM9001-BA) Input Impedance vs Frequency IF Frequency Response 64k Point FFT , fIN = 140MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 64k Point FFT , f IN = 250MHz, –1dBFS, PGA = 0, RAND “Off”, Dither “Off” 64k Point 2-Tone FFT , f IN = 136MHz, –7dBFS Per Tone, PGA = 0, RAND “Off”, Dither “Off” Differential Non-Linearity (DNL) vs Output Code Best Fit Integral Non-Linearity (INL) vs Output Code SNR vs Frequency OUTPUT CODE DNL ERROR (LSB) –0.2 0.0 0.2 0.4 0.6 0.8 1.0 49152 65536

9001 G17

–0.4 –0.6 –0.8 –1.0 16384 32768 OUTPUT CODE DNL ERROR (LSB) –2.0 –1.5 –1.0 –0.5 0.0 2.0 1.0 1.5 0.5 2.5 3.0 3.5 4.0 49152 65536

9001 G18

–2.5 –3.0 –3.5 –4.0 16384 32768 IF FREQUENCY (MHz) SNR (dB)

9001 G19

FREQUENCY (MHz) IMPEDANCE MAGNITUDE (Ω) IMPEDANCE PHASE (°C)

9001 G20

–24 –16 –32 1 100 1000 10 MAGNITUDE PHASE IF FREQUENCY (MHz) AMPLITUDE (dBFS)

9001 G21

–15 –25 –20 –10 –30 1 100 1000 10 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –50 –40 –30 –20 –10 50 60

9001 G22

–70 –80 –90 –100 –110 –120 10 20 30 40 HD2 HD3 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –50 –40 –30 –20 –10 50 60 70 80

9001 G23

–70 –80 –90 –100 –110 –120 10 20 30 40 HD2 HD3 FREQUENCY (MHz) AMPLITUDE (dBFS) –60 –50 –40 –30 –20 –10 50 60

9001 G24

–70 –80 –90 –100 –110 –120 10 20 30 40

VCC (Pins E1, E2): 3.3V Analog Supply Pin for Ampliﬁ er . The voltage on this pin provides power for the ampliﬁ er stage only and is internally bypassed to GND. VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This supply is internally bypassed to GND. OVDD (Pins A6, G9): Positive Supply for the ADC Output Drivers. This supply is internally bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Analog Inputs IN+ (Pin G1): Positive (Non-Inverting) Ampliﬁ er Input. IN– (Pin H1): Negative (Inverting) Ampliﬁ er Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They may be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. ENC + (Pin C1): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. This input is internally biased to 1.6V through a 6.2k resistor . Output data can be latched on the rising edge of ENC +. The Encode pins have a differential 100Ω input impedance. ENC– (Pin B1): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC–. This input is internally biased to 1.6V through a 6.2k resistor . Bypass to ground with a 0.1μF capacitor for a single-ended Encode signal. The Encode pins have a differential 100Ω input impedance. Control Inputs SENSE (Pin J3): Reference Mode Select and External Reference Input. Tie SENSE to V DD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set the maximum full scale input range. AMPSHDN (Pin H3): Power Shutdown Pin for Ampliﬁ er . This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down ampliﬁ er with typically 3mA ampliﬁ er supply current. MODE (Pin G3): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer . Connecting MODE to 1/3V DD selects offset binary output format and enables the clock duty cycle sta- bilizer . Connecting MODE to 2/3V DD selects 2’s complement output format and enables the clock duty cycle stabilizer . Connecting MODE to V DD selects 2’s complement output format and disables the clock duty cycle stabilizer . RAND (Pin F3): Digital Output Randomization Selection Pin. RAND = low results in normal operation. RAND = high selects D1 to D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin E3): Programmable Gain Ampliﬁ er Control Pin. PGA = low selects the normal (maximum) input voltage range. PGA = high selects a 3.5dB reduced input range for slightly better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = low results in normal operation. ADCSHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin A3): Internal Dither Enable Pin. DITH = low disables internal dither . DITH = high enables internal dither . Refer to Internal Dither section of this data sheet for details on dither operation. LVDS (Pin F5): Data Output Mode Select Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3V DD selects demultiplexed CMOS mode. Connecting LVDS to 2/3VDD selects Low Power LVDS mode. Connect- ing LVDS to VDD selects Standard LVDS mode. PIN FUNCTIONS

For CMOS Mode, Full Rate or Demultiplexed DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode. CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA. OFB (Pin E6): Over/Under Flow Digital Output for the B Bus. OFB is high when an over or under ﬂ ow has occurred on the B bus. OFB is in a high impedance state in full rate CMOS mode. DB0 to DB15 (Pins B5 to D9): Digital Outputs, B Bus. DB15 is the MSB. Active in demultiplexed mode. The B bus is in a high impedance state in full rate CMOS mode. CLKOUTB (Pin E7): Data Valid Output. CLKOUTB will toggle at the sample rate in full rate CMOS mode or at 1/2 the sample rate in demultiplexed mode. Latch the data on the falling edge of CLKOUTB. OFA (Pin G5): Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under ﬂ ow has occurred on the A bus. For LVDS Mode, STANDARD or LOW POWER –/D0+ to D15–/D15+ (Pins B5 to G6): LVDS Digital Out- puts. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver . D15 +/D15– is the MSB. CLKOUT–/CLKOUT+ (Pins E6, E7): LVDS Data Valid Output. Latch data on the rising edge of CLKOUT +, falling edge of CLKOUT–. OF–/OF+ (Pins H5, G5): Over/Under Flow Digital Output. OF is high when an over or under ﬂ ow has occurred. Pin Conﬁ guration (LVDS Outputs/CMOS Outputs) 123456 7 8 9 J GND GND SENSE GND D14 +/DA12 D14 –/DA11 D12 +/DA8 D12 –/DA7 OGND HI N – GND AMPSHDN GND OF –/DA15 D15 –/DA13 D13 –/DA9 D11 –/DA5 D11 +/DA6 GI N + GND MODE GND OF +/OFA D15 +/DA14 D13 +/DA10 OGND OV DD F GND GND RAND GND LVDS D9 –/DA1 D9 +/DA2 D10 –/DA3 D10 +/DA4 EV CC VCC PGA GND V DD CLKOUT–/OFB CLKOUT +/CLKOUTB D8 –/CLKOUTA D8 +/DA0 D GND GND DNC GND V DD D6–/DB12 D6 +/DB13 D7 –/DB14 D7 +/DB15 CE N C + GND DNC GND D0 +/DB1 D4 –/DB8 D4 +/DB9 D5 –/DB10 D5 +/DB11 BE N C – GND ADCSHDN GND D0 –/DB0 D1 –/DB2 D1 +/DB3 D3 +/DB7 D3 –/DB6 A GND GND DITH GND OGND OV DD D2–/DB4 D2+/DB5 OGND

Top View of LGA Pinout (Looking Through Component) PIN FUNCTIONS

9001 LGA01

IN– J H G F E D C B A 23456789 DATA TOP VIEWALL ELSE = GND CONTROL OGND OV DD VCC DNC VDD OGNDCONTROL OV DD OGND ENC+ IN+ ENC–

CLKOUT– VDD OVDD ENC+ ADC- SHDN RAND MODE LVDS DITH OGNDENC– INPUT AMPLIFIER PGA ADC REFERENCE INPUT S/H CONTROL LOGIC OUTPUT DRIVERS DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER INTERNAL CLOCK SIGNALS IN+ IN– SENSE AMPSHDN AMPSHDN VCC D15± … D0± OF+ OF– ANTI-ALIAS FIL TER FIRST PIPELINED ADC STAGE VOL TAGE REFERENCE DITHER SIGNAL GENERATOR SHIFT REGISTER AND ERROR CORRECTION SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE PGA RANGE SELECT 100Ω

DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the ﬁ rst ﬁ ve harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD= –20Log (V2 2 + V32 + V42 +...Vn2 )/V1⎛ where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is deﬁ ned as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Aperture Delay Time Aperture Delay is the time from when a rising ENC + equals the ENC– voltage to the instant that the input signal is held by the sample and-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNR JITTER = –20log (2π • fIN • tJITTER) The L TM9001 is an integrated System in a Package (SiP) μModule™ receiver that includes a high-speed, sampling 16-bit A/D converter , matching network, anti-aliasing ﬁ lter and a low noise, differential ampliﬁ er with ﬁ xed gain. It is designed for digitizing high frequency, wide dynamic range signals with an Intermediate Frequency (IF) range up to 300MHz. μModule is a trademark of Linear Technology Corporation.

Figure 1. Basic Functional Elements

9001 F01

functional elements as shown in Figure 1. signiﬁ cantly from existing values. no difference in distortion performance. Table 1. Semi-Custom Options pass ﬁ lter designed for 162.5MHz ±25MHz.

by applying a DC voltage to the SENSE pin. for the source. Several choices are available. reﬂ ection due to input mismatch. Table 2. Differential Ampliﬁ er Input Termination Values

9001 F02

9001 F03

Figure 2. Input Termination for Differential 50Ω Input Impedance Figure 3. Input Termination for Differential 50Ω value seven cycles later (see the Timing Diagram section).

9001 F04

Figure 4. Input Termination for Differential Table 3. Single-Ended Ampliﬁ er Input Termination Values ﬁ gure by adding 6dB voltage gain at the inputs. Figure 5. Calculate Differential Gain

9001 F05

Figure 6. Reference Circuit

9001 F06

will result in the maximum full scale range.

The PGA pin selects between two gain settings for the ADC front-end. PGA = low selects the maximum input span; PGA = high selects a 3.5dB lower input span. The high input range has the best SNR. For applications with high linearity requirements, the low input range will have improved distortion; however , the SNR will be 1.8dB worse. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the converter can depend on the encode signal quality as much as the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in ad- ditional aperture jitter that will be RMS summed with the inherent ADC aperture jitter . In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use the largest amplitude possible. If using transformer coupling, use a higher turns ratio to increase the am- plitude. 3. If the ADC is clocked with a ﬁ xed frequency sinusoidal signal, ﬁ lter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to V DD. Each input may be driven from ground to VDD for single-ended drive. The encode clock inputs have a differential 100Ω input impedance. For 50Ω inputs e.g. signal generators, an additional 100Ω impedance will provide an impedance match, as shown in Figure 7b. Maximum and Minimum Encode Rates The maximum encode rate for the L TM9001-AA is 130Msps and 160Msps for L TM9001-BA. For the ADC to operate properly the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 3.65ns (L TM9001-AA, or 2.97ns for L TM9001-BA) for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. VDD VDDL TM9001

9001 F07a

ENC– ENC+ 100Ω 1.6V 1.6V TO INTERNAL ADC CLOCK DRIVERS 50Ω 8.2pF 0.1μF 0.1μF 0.1μF T1 = M/A-COM ETC1-1-13 50Ω L TM9001

9001 F07b

ENC– ENC+ 100Ω Figure 7a. Equivalent Encode Input Circuit Figure 7b. T ransformer Driven Encode

uses the rising edge of ENC to sample the analog input. DD or 2/3VDD using external resistors. can be used to set the 1/3V DD and 2/3V DD logic levels. Table 4 shows the logic states for the LVDS pin. Table 4. LVDS Pin Function in the output driver allows operation down to low voltages. the need for external damping resistors. Figure 8. Single-Ended ENC Drive, Figure 9. ENC Drive Using a CMOS to PECL T ranslator

9001 F09

9001 F10

Figure 10. Equivalent Circuit for a Digital Output Buffer

a series resistor of 43Ω on chip. the 100Ω termination resistor at the LVDS receiver. should have about the same length. mode voltage is 1.2V , the same as standard LVDS Mode. Table 5. MODE Pin Function +/OF– pins indicates an overﬂ ow or underﬂ ow. Figure 11. Equivalent Output Buffer in LVDS Mode

9001 F11

to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. the falling edge of CLKOUTB. of CLKOUTA or the falling edge of CLKOUTB. to the same power supply as for the logic being driven. Figure 12. Functional Equivalent of Digital Output Randomizer Figure 13. Derandomizing a Randomized Digital Output

9001 F12

9001 F13

a 3.3V supply and OGND should be connected to GND. Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit

9001 F14

ADC, as compared to the noise ﬂ oor with dither off. within 10% will give the best results.

The L TM9001 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the L TM9001 has been optimized for a ﬂ ow-through layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The L TM9001 is internally bypassed with the ampliﬁ er (V CC) and ADC (VDD) supplies returning to a common ground (GND). The digital output supply (0V DD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is signiﬁ cant. The differential inputs should run parallel and close to each other . The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat T ransfer Most of the heat generated by the L TM9001 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufﬁ cient area with as many vias as possible. Recommended Layout The high integration of the L TM9001 makes the PC board layout very simple and easy. However , to optimize its electri- cal and thermal performance, some layout considerations are still necessary, see Figures 15-18.

Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the L TM9001, but can be connected on the PCB underneath the part to provide a common return path.
Use multiple ground vias. Using as many vias as pos- sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies.
Separate analog and digital traces as much as pos- sible, using vias to create high-frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the L TM9001. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The L TM9001 employs gold-ﬁ nished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materi- als declaration is available online at http://www.linear . com/designtools/leadfree/mat_dec.jsp.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 81-Lead (11.25mm × 11.25mm × 2.32mm) (Reference L TC DWG # 05-08-1809 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 81 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE SYMBOL aaa bbb TOLERANCE 0.15 0.10 11.250 BSC PACKAGE TOP VIEW LGA 81 1107 REV A 11.250 BSC PAD 1 CORNER PADS SEE NOTES X Y aaa Z aaa Z 2.17 – 2.47 DETAIL A PACKAGE SIDE VIEW DETAIL A SUBSTRATEMOLD CAP 0.27 – 0.37 1.90 – 2.10 bbb Z Z 1.27 BSC 0.605 – 0.665 0.25 × 45° CHAMFER 0.605 – 0.665 10.160 BSC 10.160 BSC PAD 1678951 234 PACKAGE BOTTOM VIEW 5.080 5.080 3.810 3.810 2.540 2.540 0.000 1.270 1.270 0.9525 1.5875 5.080 2.540 3.810 5.080 3.810 1.270 2.540 1.270 0.000 1.5875 0.9525 SUGGESTED PCB LAYOUT TOP VIEW LTMXXXXXX μModule TRAY PIN 1 BEVEL COMPONENT PIN “A1” PACKAGE IN TRAY LOADING ORIENTATION J H B A D C E F G

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 1108 REV A • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TC2202 16-Bit, 10Msps ADC 140mW , 81.6dB SNR, 100dB SFDR L TC2203 16-Bit, 25Msps ADC 220mW , 81.6dB SNR, 100dB SFDR L TC2204 16-Bit, 40Msps ADC 480mW , 79.1dB SNR, 100dB SFDR L TC2205 16-Bit, 65Msps ADC 610mW , 79dB SNR, 100dB SFDR L TC2206 16-Bit, 80Msps ADC 725mW , 77.9dB SNR, 100dB SFDR L TC2207 16-Bit, 105Msps ADC 900mW , 77.9dB SNR, 100dB SFDR L TC2208 16-Bit, 130Msps ADC 1250mW , 77.7dB SNR, 100dB SFDR L TC2209 16-BIT , 160Msps ADC 1450mW , 77.1dB SNR, 100dB SFDR L TC6400-20/L TC6400-26 Low Noise, Low Distortion Differential Ampliﬁ er for 300MHz IF , Fixed Gain of 20dB or 26dB 3V , 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF L TC6401-20/L TC6401-26 Low Noise, Low Distortion Differential Ampliﬁ er for 140MHz IF , Fixed Gain of 20dB or 26dB 3V , 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF 75ΩRS 50Ω

9001 TA02

GROUND– REFERENCED SOURCE 75Ω 51.1Ω 3.3V VCC L TM9001IN+ IN– L TM9001 with Ground-Referenced Single-Ended Input TYPICAL APPLICATIONS

Selected Specification

Linear Technology LTM9001 overview.

Summary

16-Bit IF/Baseband Receiver Subsystem

Description

16-Bit IF/Baseband Receiver Subsystem

Source title LTM9001 Datasheet(PDF) - Linear Technology

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