LTM2882_10 LINER
Document overview
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Technical content
DESCRIPTION
µModule Transceiver + Power The L TM®2882 is a complete galvanically isolated dual RS232 μModule® transceiver . No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter . A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V , independent of the main supply. Coupled inductors and an isolation power transformer provide 2500V RMS of isolation between the line transceiver and the logic interface. This device is ideal for systems with different grounds, allowing for large common mode voltages. Uninterrupted communication is guaranteed for common mode transients greater than 30kV/μs. This part is compatible with the TIA/EIA-232-F standard. Driver outputs are protected from overload and can be shorted to ground or up to ±15V without damage. An auxiliary isolated digital channel is available. This channel allows confi guration for half-duplex operation by control- ling the DE pin. Enhanced ESD protection allows this part to withstand up to ±10kV (human body model) on the transceiver interface pins to isolated supplies and across the isolation barrier to logic supplies without latchup or damage. Isolated Dual RS232 μModule T ransceiver
FEATURES
APPLICATIONS
n Isolated Dual RS232 Transceiver: 2500VRMS n Isolated DC Power: 5V at Up to 200mA n No External Components Required n 1.62V to 5.5V Logic Supply for Flexible Digital Interface n High Speed Operation 1Mbps for 250pF/3kΩ Load 250kbps for 1nF/3kΩ Load 100kbps for 2.5nF/3kΩ TIA/EIA-232-F Load n 3.3V (L TM2882-3) or 5V (L TM2882-5) Operation n No Damage or Latchup to ±10kV ESD HBM on Isolated RS232 Interface or Across Isolation Barrier n High Common Mode T ransient Immunity: 30kV/μs n Common Mode Working Voltage: 560VPEAK n T rue RS232 Compliant Output Levels n Small Low Profi le (15mm × 11.25mm × 2.8mm) Surface Mount BGA and LGA Packages n Isolated RS232 Interface n Industrial Communication n Test and Measurement Equipment n Breaking RS232 Ground Loops 1Mbps Operation
2882 TA01a
3.3V (L TM2882-3) 5V (L TM2882-5) VL VCC GND GND2 ISOLATION BARRIER ONOFF VCC2 DE AVAILABLE CURRENT: 150mA (L TM2882-5) 100mA (L TM2882-3) 400ns/DIV DRIVER OUTPUTS TIED TO RECEIVER INPUTS TOUT LOAD = 250pF + RIN ROUT LOAD = 150pF 10V/DIV 5V/DIV TIN T1OUT/R1IN T2OUT/R2IN 5V/DIV
2882 TA01b
L, L T , L TC, L TM, Linear Technology, the Linear logo and μModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Logic Inputs Logic Outputs Driver Output Voltage Receiver Input Voltage Operating Temperature Range (Note 4) (Note 1) VCC GND GND2 A B C D E F G H I J K L 12345678 TOP VIEW VCC2 VLONDINT1INR1OUTT2IN DEDOUTT1OUTR1INT2OUTR2IN R2OUT BGA PACKAGE 32-PIN (15mm s 11.25mm s 3.42mm) TJMAX = 125°C, QJA = 30°C/W , QJCTOP = 27.8°C/W , QJCBOTTOM = 19.3°C/W , QJB = 24°C/W , WEIGHT = 1.1g LGA PACKAGE 32-PIN (15mm s 11.25mm s 2.8mm) TJMAX = 125°C, QJA = 29°C/W , QJCTOP = 27.9°C/W , QJCBOTTOM = 18°C/W , QJB = 22.7°C/W , WEIGHT = 1.1g LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM2882CY-3#PBF L TM2882CY-3#PBF L TM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA 0°C to 70°C L TM2882IY-3#PBF L TM2882IY-3#PBF L TM2882Y-3 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 85°C L TM2882CY-5#PBF L TM2882CY-5#PBF L TM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA 0°C to 70°C L TM2882IY-5#PBF L TM2882IY-5#PBF L TM2882Y-5 32-Pin (15mm × 11.25mm × 3.42mm) BGA –40°C to 85°C L TM2882CV-3#PBF L TM2882CV-3#PBF L TM2882V-3 32-Pin (15mm × 11.25mm × 2.8mm) LGA 0°C to 70°C L TM2882IV-3#PBF L TM2882IV-3#PBF L TM2882V-3 32-Pin (15mm × 11.25mm × 2.8mm) LGA –40°C to 85°C L TM2882CV-5#PBF L TM2882CV-5#PBF L TM2882V-5 32-Pin (15mm × 11.25mm × 2.8mm) LGA 0°C to 70°C L TM2882IV-5#PBF L TM2882IV-5#PBF L TM2882V-5 32-Pin (15mm × 11.25mm × 2.8mm) LGA –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . Consult L TC Marketing for information on lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ ORDER INFORMATION
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5.0V , VL = VCC, and GND = GND2 = 0V , ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCC Input Supply Range L TM2882-3 l 3.0 3.3 3.6 V L TM2882-5 l 4.5 5.0 5.5 V VL Logic Supply Range l 1.62 5.5 V ICC Input Supply Current ON = 0V l 01 0 μ A L TM2882-3, No Load l 24 30 mA L TM2882-5, No Load l 17 21 mA VCC2 Regulated Output Voltage, Loaded L TM2882-3 DE = 0V , I LOAD = 100mA l 4.7 5.0 V L TM2882-5 DE = 0V , ILOAD = 150mA l 4.7 5.0 V VCC2(NOLOAD) Regulated Output Voltage, No Load DE = 0, No Load 4.8 5.0 5.35 V Effi ciency I CC2 = 100mA, L TM2882-5 (Note 2) 65 % ICC2 Output Supply Short-Circuit Current l 250 mA Driver V OLD Driver Output Voltage Low R L = 3kΩ l –5 –5.7 V VOHD Driver Output Voltage High R L = 3kΩ l 5 6.2 V IOSD Driver Short-Circuit Current V T1OUT, VT2OUT = 0V , VCC2 = 5.5V l ±35 ±70 mA IOZD Driver Three-State (High Impedance) Output Current DE = 0V , VT1OUT, VT2OUT = ±15V l ±0.1 ±10 μA Receiver VIR Receiver Input Threshold Input Low l 0.8 1.3 V Input High l 1.7 2.5 V VHYSR Receiver Input Hysteresis l 0.1 0.4 1.0 V RIN Receiver Input Resistance –15V ≤ (V R1IN, VR2IN) ≤ 15V l 357 k Ω Logic VITH Logic Input Threshold Voltage ON, T1IN, T2IN, DIN = 1.62V ≤ V L < 2.35V l 0.25•V L 0.75•V L V ON, T1IN, T2IN, DIN = 2.35V ≤ VL ≤ 5.5V l 0.4 0.67•V L V DE l 0.4 0.67•V CC2 V IINL Logic Input Current l ±1 μA VHYS Logic Input Hysteresis T1IN, T2IN, DIN (Note 2) 150 mV VOH Logic Output High Voltage R1OUT, R2OUT ILOAD = –1mA (Sourcing), 1.62V ≤ VL < 3.0V ILOAD = –4mA (Sourcing), 3.0V ≤ VL ≤ 5.5V l l VL – 0.4 VL – 0.4 V V DOUT , ILOAD = –4mA (Sourcing) l VCC2 – 0.4 V VOL Logic Output Low Voltage R1OUT, R2OUT ILOAD = 1mA (Sinking), 1.62V ≤ VL < 3.0V ILOAD = 4mA (Sinking), 3.0V ≤ VL ≤ 5.5V l l 0.4 0.4 V V DOUT , ILOAD = 4mA (Sinking) l 0.4 V ESD (HBM) (Note 2) RS232 Driver and Receiver Protection (T1OUT, T2OUT, R1IN, R2IN) to (V CC2, GND2) ±10 kV (T1OUT, T2OUT, R1IN, R2IN) to (VCC, VL, GND) ±10 kV Isolation Boundary (V CC2, GND2) to (VCC, VL, GND) ±10 kV
SWITCHING CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5.0V , VL = VCC, and GND = GND2 = 0V , ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Maximum Data Rate (T1IN to T1OUT, T2IN to T2OUT) RL = 3kΩ, CL = 2.5nF (Note 3) l 100 kbps RL = 3kΩ, CL = 1nF (Note 3) l 250 kbps RL = 3kΩ, CL = 250pF (Note 3) l 1000 kbps Maximum Data Rate (DIN to DOUT) C L = 15pF l 10 Mbps Driver Driver Slew Rate (6V/tTHL or tTLH)R L = 3kΩ, CL = 50pF (Figure 1) l 150 V/μs tPHLD, tPLHD Driver Propagation Delay R L = 3kΩ, CL = 50pF (Figure 1) l 0.2 0.5 μs tSKEWD Driver Skew |tPHLD – tPLHD|R L = 3kΩ, CL = 50pF (Figure 1) 40 ns tPZHD, tPZLD Driver Output Enable Time DE = ↑ , RL = 3kΩ, CL = 50pF (Figure 2) l 0.6 2 μs tPHZD, tPLZD Driver Output Disable Time DE = ↓ , RL = 3kΩ, CL = 50pF (Figure 2) l 0.3 2 μs Receiver t PHLR, tPLHR Receiver Propagation Delay C L = 150pF (Figure 3) l 0.2 0.4 μs tSKEWR Receiver Skew |tPHLR – tPLHR|C L = 150pF (Figure 3) 40 ns tRR, tFR Receiver Rise or Fall Time C L = 150pF (Figure 3) l 60 200 ns Auxiliary Channel t PHLL, tPLHL Propagation Delay C L = 15pF , tR and tF < 4ns (Figure 4) l 60 100 ns tRL, tFL Rise or Fall Time C L = 150pF (Figure 4) l 60 200 ns Power Supply Power-Up Time ON = ↑ to VCC2(MIN) l 0.2 2 ms ISOLATION CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5.0V , VL = VCC, and GND = GND2 = 0V , ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 2500 V RMS
1 Second ±4400 V
Common Mode T ransient Immunity (Note 2) 30 kV/μs VIORM Maximum Working Insulation Voltage (Note 2) 560 V PEAK Partial Discharge V PR = 1050 VPEAK (Note 2) <5 pC Input to Output Resistance (Note 2) >10 9 Ω Input to Output Capacitance (Note 2) 6 pF Creepage Distance (Note 2) 9.48 mm Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum Data Rate is guaranteed by other measured parameters and is not tested directly. Note 4: This device includes over-temperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specifi ed maximum operating junction temperature may result in device degradation or failure.
TYPICAL PERFORMANCE CHARACTERISTICS VCC Supply Current vs Load Capacitance (Dual Transceiver) VCC Supply Current vs Data Rate (Dual Transceiver) Driver Short-Circuit Current vs Temperature Receiver Input Threshold vs Temperature VCC Supply Current vs Temperature VCC Supply Current vs Temperature TA = 25°C, L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5V , VL = 3.3V , and GND = GND2 = 0V , ON = VL unless otherwise noted. TEMPERATURE (°C) –50 VCC CURRENT (mA) 500 100
2882 G01
12525–25 75 NO LOAD VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5 TEMPERATURE (°C) –50 VCC CURRENT (mA) 500 100
2882 G02
12525–25 75 T1OUT AND T2OUT BAUD = 100kbps R L = 3k, CL = 2.5nF VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5 LOAD CAPACITANCE (nF) VCC CURRENT (mA) 100 250kbps, L TM2882-3 100kbps, L TM2882-3 19.2kbps, L TM2882-3 19.2kbps, L TM2882-5 250kbps, L TM2882-5 100kbps, L TM2882-5
2882 G03
2.50.5 1.5 DATA RATE (kbps) VCC CURRENT (mA) 140 100 120 400 800
2882 G04
5.0V CL = 1nF 5.0V CL = 250pF 3.3V CL = 1nF 3.3V CL = 250pF TEMPERATURE (°C) –50 THRESHOLD VOL TAGE (V) 3.0 2.0 0.5 1.5 2.5 1.0 500 100
2882 G05
25–25 75 INPUT HIGH LOAD CAPACITANCE (nF) SLEW RATE (V/μs)
2882 G06
TEMPERATURE (°C) –50 SHORT-CIRCUIT CURRENT (mA) 0 50 75 100
2882 G07
125–25 25 SOURCING SINKING Driver Slew Rate vs Load Capacitance Receiver Output Voltage vs Load Current LOAD CURRENT(mA) OUTPUT VOL TAGE (V)
2882 G09
VL = 5.5V VL = 3.3V VL = 1.62V Driver Disabled Leakage Current vs Temperature at ±15V TEMPERATURE (°C) –50 LEAKAGE CURRENT (nA) 1000 0.01 100 0.1 0.001 0 50 75 100
2882 G08
125–25 25 VTOUT = ±15V
TYPICAL PERFORMANCE CHARACTERISTICS Driver Outputs Exiting Shutdown Driver Outputs Enable/Disable Logic Input Threshold vs VL Supply Voltage TA = 25°C, L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5V , VL = 3.3V , and GND = GND2 = 0V , ON = VL unless otherwise noted. VL SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 452
2882 G10
100μs/DIV 5V/DIV T1OUT T1OUT ON T2OUT T2OUT
2882 G12
DE = VCC2 DE = DOUT , DIN = VL 2μs/DIV 5V/DIV 2V/DIV T1OUT T2OUT
2882 G13
Operating Through 35kV/μs Common Mode Transients 50ns/DIV 500V/DIV 2V/DIV T1IN R1OUT * MUL TIPLE SWEEPS OF COMMON MODE TRANSIENTS 2V/DIV
2882 G14
T1OUT = R1IN VCC2 Output Voltage vs Load Current LOAD CURRENT (mA) VCC2 VOL TAGE (V) 5.2 5.0 4.6 4.7 4.9 5.1 4.8 4.5 15050 250
2882 G11
3.0V 100 200 VCC = 3.0V TO 3.6V , L TM2882-3 VCC = 4.5V TO 5.5V , L TM2882-5 5.5V 5.0V 4.5V 3.6V 3.3V
100μs/DIV 50mA/DIV 200mV/DIV
2882 G18
VCC2 Power Effi ciency 10μs/DIV 100mV/DIV
2882 G17
T1IN = 250kbps T1OUT , T2OUT , RL = 3k LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.2 1.0 0.2 0.4 0.8 0.6 200 250100
2882 G16
TA = 25°C TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, L TM2882-3 VCC = 3.3V , L TM2882-5 VCC = 5V , VL = 3.3V , and GND = GND2 = 0V , ON = VL unless otherwise noted. VCC2 Surplus Current vs Temperature TEMPERATURE (°C) –50 VCC2 CURRENT (mA) 300 200 150 250 100 500 100
2882 G15
12525–25 75 T1OUT AND T2OUT BAUD = 100kbps R L = 3k, CL = 2.5nF VCC2 = 4.8V VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5
Figure 3. Receiver Timing Measurement Figure 4. Auxiliary Channel Timing Measurement
2882 F03
2882 F04
Figure 1. Driver Slew Rate and Timing Measurement Figure 2. Driver Enable/Disable Times
2882 F01
2882 F02
0 OR VL
R2OUT (Pin A1): Channel 2 RS232 Inverting Receiver Output. Controlled through isolation barrier from receiver input R2IN. Under the condition of an isolation communi- cation failure R2OUT is in a high impedance state. T2IN (Pin A2): Channel 2 RS232 Inverting Driver Input. A logic low on this input generates a high on isolated output T2OUT. A logic high on this input generates a low on isolated output T2OUT. Do not fl oat. R1OUT (Pin A3): Channel 1 RS232 Inverting Receiver Output. Controlled through isolation barrier from receiver input R1IN. Under the condition of an isolation communi- cation failure R1OUT is in a high impedance state. T1IN (Pin A4): Channel 1 RS232 Inverting Driver Input. A logic low on this input generates a high on isolated output T1OUT. A logic high on this input generates a low on isolated output T1OUT. Do not fl oat. DIN (Pin A5): General Purpose Non-Inverting Logic Input. A logic high on DIN generates a logic high on isolated output DOUT. A logic low on DIN generates a logic low on isolated output DOUT. Do not fl oat. ON (Pin A6): Enable. Enables power and data communica- tion through the isolation barrier . If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset and the isolated side is unpowered. Do not fl oat. V L (Pin A7): Logic Supply. Interface supply voltage for pins DIN, R2OUT, T2IN, R1OUT, T1IN, and ON. Operat- ing voltage is 1.62V to 5.5V . Internally bypassed to GND with 2.2μF . V CC (Pins A8, B7-B8): Supply Voltage. Operating volt- age is 3.0V to 3.6V for L TM2882-3, and 4.5V to 5.5V for L TM2882-5. Internally bypassed to GND with 2.2μF . GND (Pins B1-B6): Circuit Ground. ISOLATED SIDE GND2 (Pins K1-K7): Isolated Side Circuit Ground. These pads should be connected to the isolated ground and/or cable shield. V CC2 (Pins K8, L7-L8): Isolated Supply Voltage Output. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 5V. Supply voltage for pins R1IN, R2IN, DE, and DOUT. Internally bypassed to GND2 with 2.2μF . R2IN (Pin L1): Channel 2 RS232 Inverting Receiver Input. A low on isolated input R2IN generates a logic high on R2OUT. A high on isolated input R2IN generates a logic low on R2OUT. Impedance is nominally 5kΩ in receive mode or unpowered. T2OUT (Pin L2): Channel 2 RS232 Inverting Driver Output. Controlled through isolation barrier from driver input T2IN. High impedance when the driver is disabled (DE pin is low). R1IN (Pin L3): Channel 1 RS232 Inverting Receiver Input. A low on isolated input R1IN generates a logic high on R1OUT. A high on isolated input R1IN generates a logic low on R1OUT. Impedance is nominally 5kΩ in receive mode or unpowered. T1OUT (Pin L4): Channel 1 RS232 Inverting Driver Output. Controlled through isolation barrier from driver input T1IN. High impedance when the driver is disabled (DE pin is low). DOUT (Pin L5): General Purpose Non-Inverting Logic Output. Logic output connected through isolation barrier to DIN. DE (Pin L6): Driver Output Enable. A low input forces both RS232 driver outputs, T1OUT and T2OUT, into a high impedance state. A high input enables both RS232 driver outputs. Do not fl oat. PIN FUNCTIONS
2.2μF 2.2μF VCC VCC2 GND2 DE DOUT T1OUT R1IN T2OUT R2IN VL 2.2μF GND ON DIN T1IN T2IN R2OUT R1OUT DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG VDD VEE VDD VDD VEE VEE
Figure 5. VCC and VL Are Independent
2882 F05
networks where grounds can take on different voltages. than 30kV/μs providing excellent noise isolation. translate signals and power across an isolation barrier . coreless transformers formed in the μModule substrate. voltage, and is rectifi ed by a full-wave voltage doubler . levels that guarantee greater than ±5V output swing. Figure 5. Simply connect the desired logic supply to V is bypassed internally by a 2.2μF capacitor . and mitigation of this phenomenon.
ary by encoding and decoding of the inputs and outputs. ±6ns, but may vary up to about 40ns. active. This mode of operation is illustrated in Figure 6. Figure 6. Half-Duplex Confi guration Using DOUT to Drive DE
2882 F06
prevent damaging the L TM2882. voltages of ±25V relative to GND2. logic high on each receiver’s respective output pin. signed per the data sheet PCB layout recommendations. Specifi c limits per test are detailed in Table 1.
layout considerations are necessary.
- Under heavily loaded conditions, V CC and GND current can exceed 300mA. Use suffi cient copper on the PCB to ensure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, size the V CC2 and GND2 conductors to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity.
- Input and Output decoupling is not required, since these components are integrated within the package. If an additional bulk capacitor is used a value of 6.8μF to 22μF is recommended. The recommendation for EMI sensitive applications is to include an additional low ESL ceramic capacitor of 1μF to 4.7μF , placed close to the power and ground terminals. Alternatively, use a number of smaller value parallel capacitors to reduce ESL and achieve the same net capacitance.
- Do not place copper on the PCB between the inner col- umns of pads. This area must remain open to withstand the rated isolation voltage. Slot the PCB in this area to facilitate cleaning and ensure contamination does not compromise the isolation voltage.
- The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fi delity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure, which can radiate differential voltages formed between GND and GND2. If ground planes are used, minimize their area, and use contiguous planes, any openings or splits can increase RF emissions.
- For large ground planes a small capacitance (≤ 330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance is not as effective due to parasitic ESL; in addition consider voltage rating, leakage, and clearance for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates the other component selection issues, however the PCB must be 4 layers and the use of a slot is not compatible. Exercise care in applying either technique to ensure the voltage rating of the barrier is not compromised. The PCB layout in Figure 7 shows a recommended con- fi guration for a low EMI RS232 application.
Figure 7. Recommended PCB Layout
2882 F07
Figure 8. Single Line Dual Half-Duplex
2882 F08
Figure 12. Isolated Multirail Power Supply
2882 F12
Figure 9. Driving Larger Capacitive Loads Figure 10. 1.8V Microprocessor Interface
2882 F09
2882 F10
Figure 11. Isolated 5V Power Supply
2882 F11
32-Lead (15mm × 11.25mm × 3.42mm) (Reference L TC DWG # 05-08-1851 Rev B) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 32 0110 REV B L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 DETAIL A Øb (32 PLACES) F G H L J K E A B C D 21435678 DETAIL B SUBSTRATE 0.27 – 0.37 2.45 – 2.55 // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M XYZddd M Zeee 0.630 ±0.025 Ø 32x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 3.22 0.50 2.72 0.73 0.60 NOM 3.42 0.60 2.82 0.78 0.63 15.0 11.25 1.27 12.70 8.89 MAX 3.62 0.70 2.92 0.83 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 32 E b e e b F G
32-Lead (15mm × 11.25mm × 2.82mm) (Reference L TC DWG # 05-08-1773 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 32 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.290 – 0.350 2.400 – 2.600 bbb Z Z PACKAGE TOP VIEW 11.25 BSC 15.00 BSC PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW LGA 32 0308 REV Ø L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 8.89 BSC 1.27 BSC PAD 1 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 DETAIL A 0.630 ±0.025 Ø 32x S YXeee DETAIL C 0.630 ±0.025 Ø 32x S YXeee F G H L J K E A B C D 2143567 2.69 – 2.95 DETAIL A 12.70 BSC DETAIL c
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 3/10 Changes to Features Add BGA Package to Pin Confi guration, Order Information and Package Description Sections Changes to LGA Package in Pin Confi guration Section Update to Pin Functions Update to RF , Magnetic Field Immunity Section “PCB Layout Isolation Considerations” Section Replaced 2, 15
Figure 15. Isolated Gate Drive with Overcurrent Detection Figure 13. Isolated RS232 Interface with Handshaking Figure 14. Isolated Dual Inverting Level T ranslator