LTM2220-AA LINER
Document overview
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Technical content
FEATURES
APPLICATIONS
DESCRIPTION
12-Bit, 170Msps ADC The LTM®2220-AA is a 170Msps sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTM2220-AA is perfect for demanding communications applications with AC per- formance that includes 66.2dB SNR and 84dB spurious free dynamic range. DC specs include ±0.5LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The CLK+ and CLK- inputs may be driven differentially or single ended with a sine wave, PECL, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536V PP input range. ■ Pin Compatible with the AD9430 ■ Sample Rate: 170Msps ■ 66.2dB SNR, 84dB SFDR ■ No Missing Codes ■ Single 3.3V supply ■ Power Dissipation: 1050mW ■ LVDS Digital Outputs ■ 1.536V PP Input Range ■ Clock Duty Cycle Stabilizer ■ Out-of-Range Indicator ■ Data Ready Output Clock ■ Integrated Bypass Capacitors ■ 100-Pin SiPLGA Package ■ Wireless and Wired Broadband Communication ■ Spectral Analysis , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. INPUT S/H CORRECTION LOGIC OUTPUT DRIVERS 12-BIT PIPELINED ADC CORE CLOCK/DUTY CYCLE CONTROL REFERENCE D11 CLOCK INPUT ANALOG INPUT
2220 TA01
3.3V 3.3V AVDD AGND DRVDD DRGND
AVDD = DRVDD (Notes 1, 2) 100 99 98 97 96 TOP VIEW AGND AGND AGND AGND SiPLGA PACKAGE 100-LEAD (16mm × 16mm) NC NC NC AGND NC NC NC AVDD AGND NC NC AGND AGND AVDD AVDD AGND AGND AVDD AVDD AGND V IN+ VIN– AGND AVDD AGND DRVDD DRGND D8+ D8– D7+ D7– D6+ D6– DRGND D5+ D5– DCO+ DCO– DRVDD DRGND D4+ D4– D3+ D3– D2+ D2– DRVDD DRGND D1+ D1– AGND AVDD AVDD AGND AGND AVDD AVDD AGND AGND AGND AVDD AVDD AVDD AGND AGND OR+ OR– DRVDD DRGND D11+ D11– D10+ D10– D9+ D9– AGND AVDD AVDD AVDD AGND AGND AGND NC AVDD AGND CLK+ CLK– AGND AVDD AVDD AGND NC NC NC NC NC DRVDD DRGND D0– D0+ 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TJMAX = 125°C, θJA = 20°C/W EXPOSED PADS ARE AGND ORDER PART NUMBER LGA PART MARKING LTM2220IV-AA#PBF LTM2220V-AA Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) ● 12 Bits Integral Linearity Error (Note 5) ● –1.5 ±0.5 1.5 LSB Differential Linearity Error ● –1 ±0.3 1 LSB Offset Error (Note 6) –35 ±3 35 mV Gain Error ±0.5 %FS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) ANALOG INPUTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Differential Input Range V IN+ – VIN– ● 1.536 V VIN, CM Common Mode Input Range (V IN+ + VIN–)/2 ● 0 3.6 V fL Lower –3dB Frequency 1.6 kHz fH Upper –3dB Frequency R S = 75Ω 195 MHz tJITTER Sample and Hold Jitter 0.2 ps RMS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) DYNAMIC ACCURACY SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 10MHz Input 66.2 dB 70MHz Input ● 63.5 66.1 dB SINAD Signal to Noise Plus Distortion Ratio 10MHz Input 66.1 dB 70MHz Input ● 63.2 65.9 dB SFDR Spurious Free Dynamic Range: 2nd or 3rd Harmonic 10MHz Input 84 dB 70MHz Input ● 70 84 dB SFDR Spurious Free Dynamic Range: 4th Harmonic or Higher 10MHz Input 90 dB 70MHz Input ● 78 90 dB IMD Intermodulation Distortion f IN1 = 138MHz, fIN2 = 140MHz 81 dB The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
DIGITAL INPUTS AND OUTPUTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CLOCK INPUTS (CLK+, CLK–) VID Differential Input Voltage ● 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set ● 1.1 1.6 1.6 2.5 V V RIN Input Resistance 6k Ω CIN Input Capacitance (Note 7) 3 pF DIGITAL LOGIC OUTPUTS V OD Differential Output Voltage 100 Ω Load ● 247 350 454 mV VOS Output Common Mode Voltage ● 1.125 1.250 1.375 V The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) POWER REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AVDD Analog Supply Voltage (Note 8) ● 3.1 3.3 3.5 V DRVDD Digital Supply Voltage (Note 8) ● 3.0 3.3 3.6 V IAVDD Analog Supply Current ● 264 288 mA IDVDD Digital Supply Current ● 55 70 mA PDISS Power Dissipation ● 1050 1182 mW The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency ● 1 170 MHz tL CLK Low Time (Note 7) ● 2 2.94 500 ns tH CLK High Time (Note 7) ● 2 2.94 500 ns tAP Sample-and-Hold Aperture Delay 0 ns tD CLK to DATA Delay (Note 7) ● 1.5 3 4.3 ns tC CLK to DCO Delay (Note 7) ● 1.5 3 4.3 ns DATA to DCO Skew (t C – tD), (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with AGND and DRGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup. Note 4: AVDD = DRVDD = 3.3V, fSAMPLE =170MHz, differential CLK+/CLK- = 2Vpp sine wave, differential analog inputs, unless otherwise noted. Note 5: Integral nonlinearity is defi ned as the deviation of a code from a “best fi t straight line” fi t to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code fl ickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions.
TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point FFT, fIN = 5MHz, –1dB,
8192 Point FFT, fIN = 30MHz,
–1dB, 170Msps
8192 Point FFT, fIN = 70MHz,
–1dB, 170Msps FREQUENCY (MHz) AMPLITUDE (dB) –80 –20 –10 20 40 50
2220 G01
–100 –40 –60 –90 –30 –110 –50 –70 10 30 60 70 80 FREQUENCY (MHz) AMPLITUDE (dB) –80 –20 –10 20 40 50
2220 G02
–100 –40 –60 –90 –30 –110 –50 –70 10 30 60 70 80 FREQUENCY (MHz) AMPLITUDE (dB) –80 –20 –10 20 40 50
2220 G03
–100 –40 –60 –90 –30 –110 –50 –70 10 30 60 70 80 FREQUENCY (MHz) AMPLITUDE (dB) –80 –20 –10 20 40 50
2220 G04
–100 –40 –60 –90 –30 –110 –50 –70 10 30 60 70 80 OUTPUT CODE ERROR (LSB) 4096
2220 G05
1.0 0.8 0.6 0.4 0.2 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 0 4096 1024 2048 3072 1.0 0.8 0.6 0.4 0.2 – 0.2 – 0.4 – 0.6 – 0.8 – 1.0 OUTPUT CODE ERROR (LSB)
2220 G06
8192 Point FFT, fIN = 140MHz,
–1dB, 170Msps INL Error DNL Error
Pin is not connected internally. AGND (Pins 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, Analog Ground. AVDD (Pins 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99): 3.3V Analog Supply. VIN+ (Pin 21): Positive Analog Input. VIN- (Pin 22): Negative Analog Input. CLK+ (Pin 36): Clock Input. The input sample starts on the positive edge. CLK- (Pin 37): Clock Complement Input. Conversion starts on the negative edge. Bypass to ground with a 0.1µF ceramic for a single-ended clock. DRVDD (Pins 47, 54, 62, 75, 83): 3.3V Digital Output Driver Supply. DRGND (Pins 48, 53, 61, 67, 74, 82): Digital Output Driver Ground. D0- (Pin 49): D0 Complement Output Bit (LSB). D0+ (Pin 50): D0 True Output Bit (LSB). D1- (Pin 51): D1 Complement Output Bit. D1+ (Pin 52): D1 True Output Bit. D2- (Pin 55): D2 Complement Output Bit. D2+ (Pin 56): D2 True Output Bit. D3- (Pin 57): D3 Complement Output Bit. D3+ (Pin 58): D3 True Output Bit. D4- (Pin 59): D4 Complement Output Bit. D4+ (Pin 60): D4 True Output Bit. DCO- (Pin 63): Data Clock Output Complement. DCO+ (Pin 64): Data Clock Output True. D5- (Pin 65): D5 Complement Output Bit. D5+ (Pin 66): D5 True Output Bit. D6- (Pin 68): D6 Complement Output Bit. D6+ (Pin 69): D6 True Output Bit. D7- (Pin 70): D7 Complement Output Bit. D7+ (Pin 71): D7 True Output Bit. D8- (Pin 72): D8 Complement Output Bit. D8+ (Pin 73): D8 True Output Bit. D9- (Pin 76): D9 Complement Output Bit. D9+ (Pin 77): D9 True Output Bit. D10- (Pin 78): D10 Complement Output Bit. D10+ (Pin 79): D10 True Output Bit. D11- (Pin 80): D11 Complement Output Bit (MSB). D11+ (Pin 81): D11 True Output Bit (MSB). OR- (Pin 84): Overrange Output Complement. OR+ (Pin 85): Overrange Output True. GND (Exposed Pads): The exposed pads on the bottom of the package need to be soldered to Analog Ground. TIMING DIAGRAM tH tD tC tL N – 5 N – 4 N – 3 N – 2 N – 1 tAP N + 1 N + 2 N + 4 N + 3 NANALOG INPUT CLK– CLK+ DCO– DCO+ D0-D11, OR
2220 TD01
Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamen- tal input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the fi rst fi ve harmonics and DC. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to Total Harmonic Distortion (THD). IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are ap- plied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula- tion distortion is defi ned as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. APPLICATIONS INFORMATION Lower and Upper –3dB Frequencies The input frequencies at which the amplitude of the re- constructed fundamental is reduced by 3dB for a full scale input signal. Note that the analog input has a bandpass response. Aperture Delay Time The time from when a rising CLK+ equals the CLK– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNR JITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION The LTM2220-AA is a CMOS pipelined multistep converter. The converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal AC perfor- mance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distor- tion. The clock input is differential for improved common mode noise immunity. The LTM2220-AA is pin compatible with the AD9430 when used with LVDS outputs, 2’s complement output format and the 1.536V PP input range. The LTM2220-AA package contains power supply bypass capacitors, which makes the part easy to use since it is insensitive to the PC board layout.
limiting the wideband noise at the converter input. common mode voltage of between 0V and 3.6V. order harmonics, especially the second. the encode signal quality as much as on the analog input. the logic threshold for single-ended drive circuits. Figure 1. Equivalent Input Circuit
2220 F01
2220 F02
Figure 2. Single-Ended to Differential
inherent ADC aperture jitter.
- Differential drive should be used.
- Use as large an amplitude as possible; if transformer
- If the ADC is clocked with a sinusoidal signal, fi lter the
encode signal to reduce wideband noise.
- Balance the capacitance and series resistance at both
driven from ground to VDD for single-ended drive. The maximum encode rate for the LTM2220-AA is 170Msps. settling time for proper operation. for the PLL to lock onto the input clock. frequency for the LTM2220-AA is 1Msps.
2220 F03
Figure 3. Transformer Driven CLK+/CLK–
2220 F04
2220 F05
Figure 5. CLK Drive Using a CMOS to PECL Translator Figure 4. Single-Ended CLK Drive,
an analog signal or underneath the ADC. come from quiet linear voltage regulators. pads and package leads onto the printed circuit board. to a ground plane of suffi cient area. Table 1. Output Codes vs Input Voltage traces should have about the same length. input voltage, the digital data bits and the overrange bit.
2220 F06
Figure 6. Digital Output
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 PRIMARY DATUM -Z- IS SEATING PLANE 6. DIMENSION (b) IS MEASURED AT THE MAXIMUM LAND WIDTH, PARALLEL TO PRIMARY DATUM -Z- 7. TOTAL NUMBER OF PADS: 104 TOTAL (100 PERIPHERAL + 4 COMMON CENTER) DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.03 1.93 – 2.13 DETAIL ADETAIL A SUBSTRATE PAD MOLD CAP 0.33 – 0.43 1.60 – 1.70 bbb Z Z 15.9 – 16.1 TOP VIEWDETAILED PAD LAYOUT 15.90 – 16.10
4 PAD 1
X Y aaa Z aaa Z 11.90 – 12.10 0.5 BASIC 11.90 – 12.10 0.05 – 0.15 DETAIL B COLUMNS 1 11 13 10 12 15 17 14 16 19 21 18 20 22 BOTTOM VIEW M YXeee 100 76 A C B E D G F J H L K N M R P T S V U Y W AB AA AD AF ROWS AC AE51 5026 24 26 10_10_06 (2X) (2X) 0.218 – 0.278 (b) 0.315 – 0.385 DETAIL B 1.120 – 1.180 1.313 – 1.383 6.000 5.500 5.000 4.500 4.000 3.500 3.000 2.500 2.000 2.000 1.500 1.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 2.500 1.000 1.000 0.500 0.500 0.000 6.000 5.500 5.000 4.500 4.000 3.500 3.000 2.500 2.000 2.000 1.500 1.500 3.000 3.500 4.000 4.500 5.000 5.500 6.000 2.500 1.000 1.000 0.500 0.500 0.000 3.1245 3.1245 1.045 1.045 3.1245 3.1245 1.045 3.1245 3.1245 1.045 1.045 3.1245 5026 100 3.1245 1.045 1.045 1.045 SiPLGA Package 100-Lead (16mm × 16mm) (Reference LTC DWG # 05-08-1802 Rev Ø)
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0107 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package LTC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN Package LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain