LTM2173-14

Linear Technology

14-Bit, 80Msps Low Power Quad ADC

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LTM2173-14 LINER

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 28

Technical content

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

14-Bit, 80Msps Low Power Quad ADC LTM2173-14, 80Msps, 2-Tone FFT, fIN = 70MHz and 75MHz The LTM®2173-14 is a 4- channel, simultaneous sam - pling 14-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the num- ber of data lines. Each channel outputs two bits at a time (2-lan e mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The ENC+ and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 4-Channel Simultaneous Sampling ADC n 73dB SNR n 88dB SFDR n Low Power: 96mW per Channel n Single 1.8V Supply n Serial LVDS Outputs: 1 or 2 Bits per Channel n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth S/H n Shutdown and Nap Modes n Serial SPI Port for Configuration n Internal Bypass Capacitance, No External Components n 140-Pin (11.25mm × 9mm) BGA Package n Automotive n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition n Nondestructive Testing All registered trademarks and trademarks are the property of their respective owners. FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90AMPLITUDE (dBFS) –50 –30 –40 –20 –10 10 20 30 40

217314 TA01b

1.8V VDD 1.8V OVDD OUT1A OUT1B OUT2A OUT2B OUT4A OUT4B DATA CLOCK OUT FRAME GNDGND

217314 TA01

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217314f For more information www.linear.com/LTM2173-14 LTM2173-14 http://www.linear.com/product/ LTM2173-14#orderinfo ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM2173HY-14#PBF LTM2173HY-14#PBF LTM2173Y14 140- Lead (11.25mm × 9mm × 2.72mm) BGA – 40°C to 105°C

De vice temperature grade is indicated by a label on the shipping container.
Pa d or ball finish code is per IPC/JEDEC J-STD-609.
Te rminal Finish Part Marking : www.linear.com/leadfree
Th is product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy
Re commended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbsssembly
BG A Package and Tray Drawings: www.linear.com/packaging
Th is product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy Supply Voltages Analog Input Voltage (AIN+, AIN–, 3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, 3V to 3.9V 3V to 3.9V 3V to (OVDD + 0.3V) Operating Temperature Range LTM2 C to 105°C C to 125°C P C D E F G H J K L M N A B 10 9 8 7 6 5 4 3 2 BGA PACKAGE 140-LEAD (11.25mm × 9.00mm × 2.72mm) TOP VIEW TJMAX = 150°C, θJA = 30°C/W, θJC = 25°C/W, θJB = 15°C/W, θJCbottom = 12°C/W

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5) PARAMETER CONDITIONS LTM2173-14 UNITSMIN TYP MAX Resolution (No Missing Codes) l 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l –2.75 ±1 2.75 LSB Differential Linearity Error Differential Analog Input l –0.8 ±0.3 0.8 LSB Offset Error (Note 7) l –12 ±3 12 mV Gain Error Internal Reference External Reference l –2.6 –1. –1.3 %FS %F S Of fset Drift ±20 µV/°C Full-Scale Drift Internal Reference External Reference ±35 ±25 ppm /°C ppm/°C Gai n Matching External Reference ±0.2 %FS Offset Matching ±3 mV Transition Noise External Reference 1.2 LSBRMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (A IN+ – AIN–) 1.7V < VDD < 1.9V l 1 to 2 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 80Msps 100 µA IIN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –6 6 µA tAP Sample-and-Hold Acquisition Delay Time 0 ns tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz

217314f For more information www.linear.com/LTM2173-14 LTM2173-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS LTM2173-14 UNITSMIN TYP MAX SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 0MHz Input l 69.7 72.9 72.5 dBF S dBFS dBFS SF DR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MH z Input 70MHz Input 0MHz Input l dBF S dBFS dBFS Sp urious Free Dynamic Range 4th Harmonic or Higher 5MH z Input 70MHz Input 0MHz Input l dBF S dBFS dBFS (N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input 0MHz Input l 69.6 72.9 7 2.6 dBF S dBFS dBFS Cr osstalk, Near Channel 10MHz Input (Note 12) –90 dBc Crosstalk, Far Channel 10MHz Input (Note 12) –105 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. AIN = –1dBFS. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V VCM Output Temperature Drift ±25 ppm/°C VCM Output Resistance –600µA < IOUT < 1mA 4 Ω VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V VREF Output Temperature Drift ±25 ppm/°C VREF Output Resistance –400µA < IOUT < 1mA 7 Ω VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC +, ENC– ) VID Differential Input Voltage (Note 8) l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.2 1. 6 V V VIN Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V RIN Input Resistance (See Figure 10) 10 kΩ CIN Input Capacitance 3.5 pF DIGITAL INPUTS ( CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance 3 pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used) ROL Logic Low Output Resistance to GND V DD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance 3 pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mo de l l 247 125 350 17 5 454 25 0 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mo de l l 1.125 1.125 1.2 1.250 1.3 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OV DD = 1.8V 100 Ω

217314f For more information www.linear.com/LTM2173-14 LTM2173-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTM2173-14 UNITSMIN TYP MAX VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 189 205 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mo de l l mA mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mo de l l 385 425 421 4 62 mW mW PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 85 mW PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled (No Decrease for Sleep Mode) 20 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTM2173-14 UNITSMIN TYP MAX fS Sampling Frequency (Notes 10,11) l 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 5.93 6.2 6.25 100 10 0 ns ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 5.93 6.2 6.25 100 10 0 ns ns tAP Sample-and-Hold Acquisition Delay Time 0 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (R TERM = 100Ω Differential, C L = 2pF to GND on Each Output) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-B it Serialization 2-Lanes, 12-B it Serialization 1-Lane, 16-B it Serialization 1-Lane, 14-B it Serialization 1-Lane, 12-B it Serialization 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) s s s s s s t FRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter t SER = 1ns 60 psP-P Pipeline Latency 6 Cycles

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8) tSCK SCK Period Write Mode Read Back Mode, C SDO = 20pF, RPULLUP = 2k l l 250 ns ns tS CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, C SDO = 20pF, RPULLUP = 2k l 125 ns TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode, differential ENC +/ENC– = 2VP-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: V DD = OVDD = 1.8V, fSAMPLE = 80MHz, 2-lane output mode, differential ENC +/ENC– = 2VP-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire device, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so t SER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.3, and Ch.2 to Ch.4.

217314f For more information www.linear.com/LTM2173-14 LTM2173-14 2-Lane Output Mode, 14- Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 N+1 N+2N

217314 TD02

D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 OUT#A– OUT#A+ FR– FR+ D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8OUT#B– OUT#B+ NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– TIMING DIAGRAMS 2-Lane Output Mode, 16- Bit Serialization* ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 *SEE THE DIGITAL OUTPUTS SECTION SAMPLE N-5 SAMPLE N-4 N+1 N

217314 TD01

D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 OUT#A– OUT#A+ FR– FR+ D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8OUT#B– OUT#B+

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 TIMING DIAGRAMS 2-Lane Output Mode, 12- Bit Serialization 1-Lane Output Mode, 16- Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSER tSER tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N

217314 TD03

D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 OUT#A– OUT#A+ FR+ FR– D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8OUT#B– OUT#B+ ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER

217314 TD04

D1 D0 0 0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED

217314f For more information www.linear.com/LTM2173-14 LTM2173-14 TIMING DIAGRAMS 1-Lane Output Mode, 14- Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER

217314 TD06

D3 D2 D1 D0 D13 D12 D11 D10 D12 D11 D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 12- Bit Serialization ANALOG INPUT ENC– ENC+ DCO– DCO+ tAP tENCH tENCL tSERtPD tDATAtFRAME SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 N+1N tSER tSER

217314 TD07

D5 D4 D3 D2 D13 D12 D11 D10 D12 D11D9 D8 D7 D6 D5 D4 D3 D2 D13 OUT#A– OUT#A+ FR– FR+ OUT#B+, OUT#B– ARE DISABLED

217314fFor more information www.linear.com/LTM2173-14 LTM2173-14 tS tDS A5 A4 A3 A2 A1 A0 XX D7 D6 D5 D4 D3 D2 D1 D0 XX XX XX XX XX XX XX CS SCK SDI R/W SDO HIGH IMPEDANCE SPI Port Timing (Readback Mode) SPI Port Timing (Write Mode) tDH tDO tSCK tH A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

217314 TD08

217314f For more information www.linear.com/LTM2173-14 LTM2173-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM2173-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –7dBFS per Tone, 80Msps LTM2173-14: Shorted Input Histogram LTM2173-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 80Msps LTM2173-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 80Msps LTM2173-14: 8k Point FFT, fIN = 140MHz, –1dBFS, 80Msps LTM2173-14: Integral Nonlinearity (INL) LTM2173-14: Differential Nonlinearity (DNL) LTM2173-14: 8k Point FFT, fIN = 5MHz, –1dBFS, 80Msps OUTPUT CODE –1.0 –0.4 –0.2 –0.6 –0.8 DNL ERROR (LSB) 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384