LTC1662_1 LINER
Document overview
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Technical content
Ultralow Power, Dual 10-Bit DAC in MSOP The LTC 1662 is an ultralow power, fully buffered volt- age output, dual 10-bit digital-to-analog converter (DAC). Each DAC channel draws just 1.7 mA (typ) total supply- plus-reference operating current, yet is capable of sup- plying DC output currents in excess of 1mA and reliably driving capacitive loads of up to 1000pF. A program- mable Sleep mode further reduces total operating cur- rent to 0.05mA. Linear Technology’s proprietary, inherently monotonic architecture provides excellent linearity and an exception- ally small external form factor. The double-buffered input logic provides simultaneous update capability and can be used to write to the DACs without interrupting Sleep mode. With its tiny operating current and exceptionally small size, the LTC1662 is ideal for use in the most power- constrained products. For most designs, there is no perceptible impact on the power budget; the LTC1662 draws many times less current than even a trimpot, while providing buffered, low impedance (0.5 W typical, V CC = 5V) rail-to-rail outputs. The LTC1662 is pin and software compatible with the LTC1661 dual, 60mA 10-bit DAC. It is available in 8-pin MSOP and PDIP packages and is specified over the industrial temperature range. n Ultralow Power: 1.5mA (Typ) ICC per DAC Plus 0.05mA Sleep Mode for Extended Battery Life n Tiny: Two 10-Bit DACs in an 8-Lead MSOP— Half the Size of an SO-8 n Wide 2.7V to 5.5V Supply Range n Double Buffered for Simultaneous DAC Updates n Rail-to-Rail Voltage Outputs Drive 1000pF n Reference Range Includes Supply for Ratiometric 0V-to-V CC Output n Reference Input Impedance Is Code-Independent (7.1MW Typ)—Eliminates External Buffers n 3-Wire Serial Interface with Schmitt Trigger Inputs n Differential Nonlinearity: –0.75LSB Max , LTC and LT are registered trademarks of Linear Technology Corporation. n Mobile Communications n Portable Battery-Powered Instruments n Remote or Inaccessible Adjustments n Digitally Controlled Amplifiers and Attenuators n Factory or Field Calibration CS/LD 1662 BD 1 4 10-BIT DAC A 10-BIT DAC B ADDRESS DECODER CONTROL LOGIC SHIFT REGISTER SDI REF VOUT A 8 5 GND VCC VOUT B LATCH LATCH LATCH LATCH SCK APPLICATIO SU FEATURES DESCRIPTIO U BLOCK DIAGRA W TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 ICC + IREF (µA)
1662 G02
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC CODE = 1023 5.5V VCC = 2.7V 4.5V 3.6V Total Supply-Plus-Reference Operating Current
A UGWA WU WARBSOLUTEX I T I S (Note 1) Operating Temperature Range ELECTRICAL C CHARA TERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Accuracy Resolution l 10 Bits Monotonicity (Note 2) l 10 Bits DNL Differential Nonlinearity (Note 2) l – 0.12 – 0.75 LSB INL Integral Nonlinearity (Note 2) l – 0.8 –4 LSB VOS Offset Error V CC = 5V, VREF = 4.096V, Measured at Code 20 l –5 – 25 mV VOS TC V OS Temperature Coefficient – 15 mV/°C GE Gain Error V CC = 5V, VREF = 4.096V l –1 –8 LSB GE TC Gain Error Temperature – 12 mV/°C Coefficient PSR Power Supply Rejection V REF = 2.5V 0.18 LSB/V Reference Input Input Voltage Range l 0V CC V Input Resistance Active Mode l 3.9 7.1 M W Sleep Mode 2.5 G W Input Capacitance 10 pF WU UPACKAGE/ORDER I FOR ATIO ORDER PART NUMBER MS8 PART MARKING ORDER PART NUMBER TJMAX = 125°C, qJA = 150°C/W CS/LD SCK SDI REF V OUT A GND VCC VOUT B TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP TOP VIEW CS/LD SCK SDI REF VOUT A GND VCC VOUT B N8 PACKAGE 8-LEAD PLASTIC DIP LTC1662CN8 LTC1662IN8 LTC1662CMS8 LTC1662IMS8 Consult factory for Military grade parts. TJMAX = 125°C, qJA = 100°C/W The l denotes the specifications which apply over the full operating temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF £ VCC, VOUT Unloaded unless otherwise noted. LTKB LTKC
The l denotes the specifications which apply over the full operatingELECTRICAL C CHARA TERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS The l denotes the specifications which apply over the full operating temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF £ VCC, VOUT Unloaded unless otherwise noted. Power Supply VCC Positive Supply Voltage For Specified Performance l 2.7 5.5 V ICC Supply Current V CC = 3V (Note 3) 3.0 4.0 mA VCC = 5V (Note 3) 3.5 4.5 mA VCC = 3V (Note 3) l 5.0 mA VCC = 5V (Note 3) l 5.5 mA Sleep Mode Operating Current Supply Plus Reference Current, V CC = VREF = 5V (Note 3) 0.05 0.10 mA l 0.18 mA DC Performance Short-Circuit Current Low V OUT = 0V, VCC = VREF = 5V, Code = 1023 (Note 7) l 51 2 7 0 m A Short-Circuit Current High V OUT = VCC = VREF = 5V, Code = 0 (Note 7) l 31 0 8 0 m A AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) 20 V/ms Falling (Notes 4, 5) 7 V/ms Voltage Output Settling Time Rising 0.1V FS to 0.9VFS –0.5LSB (Notes 4, 5) 0.40 ms Falling 0.9VFS to 0.1VFS –0.5LSB (Notes 4, 5) 0.75 ms Capacitive Load Driving 1000 pF Digital I/O VIH Digital Input High Voltage V CC = 2.7V to 5.5V l 2.4 V VCC = 2.7V to 3.6V l 2.0 V VIL Digital Input Low Voltage V CC = 4.5V to 5.5V l 0.8 V VCC = 2.7V to 5.5V l 0.6 V ILK Digital Input Leakage V IN = GND to VCC l –0.05 –1.0 mA CIN Digital Input Capacitance 1.5 pF TI I G CHARACTERISTICSUW The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 4.5V to 5.5V t1 SDI Setup Relative to SCK Positive Edge l 55 15 ns t2 SDI Hold Relative to SCK Positive Edge l 0– 1 0 n s t3 SCK High Time (Note 6) l 30 14 ns t4 SCK Low Time (Note 6) l 30 14 ns t5 CS/LD Pulse Width (Note 6) l 100 27 ns t6 LSB SCK High to CS/LD High (Note 6) l 30 2 ns t7 CS/LD Low to SCK High (Note 6) l 20 – 21 ns t9 SCK Low to CS/LD Low (Note 6) l 0– 5 n s t11 CS/LD High to SCK Positive Edge (Note 6) l 20 0 ns SCK Frequency Square Wave (Note 6) l 16.7 MHz VCC = 2.7V to 5.5V t1 SDI Setup Relative to SCK Positive Edge (Note 6) l 75 20 ns t2 SDI Hold Relative to SCK Positive Edge (Note 6) l 0– 1 0 n s t3 SCK High Time (Note 6) l 50 15 ns t4 SCK Low Time (Note 6) l 50 15 ns
TYPICAL PERFOR A CE CHARACTERISTICSUW CODE 0 256 512 768 1023 INTEGRAL NONLINEARITY (LSB)
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DIFFERENTIAL NONLINEARITY (LSB)
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0.60 0.40 0.20 –0.20 –0.40 –0.60 0.75 –0.75 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See Figure 2. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kW in parallel with 100pF. codes k = 102 and k = 922. Note 6: Guaranteed by design, not subject to test. Note 7: One DAC output loaded. TI I G CHARACTERISTICSUW The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. t5 CS/LD Pulse Width (Note 6) l 150 30 ns t6 LSB SCK High to CS/LD High (Note 6) l 50 3 ns t7 CS/LD Low to SCK High (Note 6) l 30 – 14 ns t9 SCK Low to CS/LD Low (Note 6) l 0– 5 n s t11 CS/LD High to SCK Positive Edge (Note 6) l 30 0 ns SCK Frequency Square Wave (Note 6) l 10 MHz SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 ICC (µA)
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5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC CODE = 1023 5.5V 4.5V 3.6V VCC = 2.7V TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 125 ICC + IREF (µA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC CODE = 1023 5.5V VCC = 2.7V 4.5V 3.6V FREQUENCY (Hz) ICC (µA) 100 10 100 1k 10k 100k 1M 10M 100M
1662 G03
VCC = 5V VCC = 3V CS/LD = LOGIC LOW CODE = 0 LOGIC INPUT VOLTAGE (V) ICC (mA)
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1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 5V ALL DIGITAL INPUTS SHORTED TOGETHER Supply Current vs Temperature Total Supply-Plus-Reference Operating Current Supply Current vs Clock Frequency Supply Current vs Logic Input Voltage
VREF (V) 0123456 PEAK INL (LSB)
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VCC = 5.5V MAX POS INL MAX NEG INL PEAK DNL (LSB)
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0.75 0.50 0.25 –0.25 –0.50 –0.75 VCC = 5.5V VREF (V) 0123456 MAX POS DNL MAX NEG DNL TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 OFFSET ERROR (mV)
1662 G09
VCC = 5V VREF = 4.096V TEMPERATURE (°C) –55 –35 –15 5 25 45 65 85 105 GAIN ERROR (mV)
1662 G10
VCC = 5V VREF = 4.096V IOUT (mA) – 5 – 4 – 3 – 2 – 1 012345 ∆VOUT (LSB)
1662 G11
1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 VREF = VCC = 5V VOUT = 2.5V CODE = 512 T A = 25°C SOURCE SINK IOUT (mA) ∆VOUT (LSB)
1662 G12
1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 –1.0 VREF = VCC = 3V VOUT = 1.5V CODE = 512 T A = 25°C SOURCE SINK OUTPUT SOURCE CURRENT (A) 1µ 10µ 100µ 1m 10m 100m VOUT (V)
1662 G13
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC CODE = 512 TA = 25°C VCC = 5.5V VCC = 5V VCC = 4.5V VCC = 3.6V VCC = 3V VCC = 2.7V OUTPUT SINK CURRENT (A) 1µ 10µ 100µ 1m 10m 100m VOUT (V)
1662 G14
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC CODE = 512 TA = 25°C VCC = 5.5V VCC = 5V VCC = 4.5V VCC = 3.6V VCC = 3V VCC = 2.7V OUTPUT SOURCE/SINK CURRENT (mA) VOUT (V)
1662 G15
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VREF = VCC TA = 25°C CODE = 1023 CODE = 0 TYPICAL PERFOR A CE CHARACTERISTICSUW Integral Nonlinearity (INL) vs Reference Voltage Differential Nonlinearity (DNL) vs Reference Voltage Offset Voltage vs Temperature Gain Error vs Temperature Load Regulation vs Output Current at 5V Load Regulation vs Output Current at 3V Output Amplifier Current Sourcing Capability (Midscale) Output Amplifier Current Sinking Capability (Midscale) Max/Min Output Voltage vs Source/ Sink Output Current (VCC = 5V)
OUTPUT SOURCE/SINK CURRENT (mA) VOUT (V)
1662 G16
3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 VREF = VCC TA = 25°C CODE = 1023 CODE = 0 TIME (0.5ms/DIV) VOUT (V)
1662 G17
VREF = VCC = 5V 10% TO 90% STEP CAPACITANCE (F) 100p 1000p 0.01 µ 0.1µ 1µ 10µ 100µ MINIMUM SERIES RESISTANCE (Ω )
1662 G18
TYPICAL PERFOR A CE CHARACTERISTICSUW Max/Min Output Voltage vs Source/ Sink Output Current (VCC = 3V) Large-Signal Step Response Output Minimum Series Resistance vs Load Capacitance CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is pulled high, SCK is disabled and the operation(s) specified in the Control code, A3-A0, is (are) performed. CMOS and TTL compat- ible. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 3): Serial Interface Data Input. Input word data on the SDI pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. REF (Pin 4): Reference Voltage Input. 0V £ V REF £ VCC. VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs. The output range is 0 1023 1024££ æ Łç ö ł÷VV VOUTA OUTB REF, VCC (Pin 6): Supply Voltage Input. 2.7V £ VCC £ 5.5V. GND (Pin 7): System Ground. PI FU CTIO S UU U Gain Error (GE): The deviation from the slope of the ideal DAC transfer function, expressed in LSBs at full scale. Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = ( DV OUT – LSB)/LSB where DVOUT is the measured voltage difference between two adjacent codes. Full-Scale Error (FSE): The deviation of the actual full- scale voltage from ideal. FSE includes the effects of offset and gain errors (see Figure 2). DEFI ITIO SUU
1662 F01
Figure 1. Register Loading Sequence between two successive codes. cannot go below zero (see Figure 2).
code D9-D0 and VREF is the voltage at REF (Pin 4). Table 1. DAC Control Functions
1000 N o C hange Update Outputs Wake Load Both DAC Regs with Existing Contents of Input
Note: All control codes other than those shown are undefined and not subject to test. Control code, the 10-bit Input code and two don’t-care bits. Table 2. LTC1662 Input Word
Alternatively, one DAC may be loaded with a new input code during Sleep; then with just one command, the other DAC is loaded, the part is awakened and both outputs are updated. For example, control code 0001 b is used to load DAC A during Sleep. Then Control code 0101 b loads DAC B, wakes the part and simultaneously updates both DAC outputs. Voltage Outputs Each of the rail-to-rail output amplifiers contained in the LTC1662 can typically source or sink at least 1mA (VCC␣ =␣ 5V). The outputs swing to within a few millivolts of either supply when unloaded and have an equivalent output resistance of 130W (typical) when driving a load to the rails. The output amplifiers are stable driving capacitive loads of up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. Please see the Output Minimum Resistance vs Load Capaci- tance curve in the Typical Performance Characteristics section. Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 2b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE = VOS + GE) is positive, the output for the highest codes limits at V CC as shown in Figure 2c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. The first of these, the Input Register, is used for loading new input codes. The second buffer, the DAC Register, is used for updating the DAC outputs. Each DAC has its own 10-bit Input Register and 10-bit DAC Register. By selecting the appropriate 4-bit Control code (see Table␣ 1) it is possible to perform single operations, such as loading one DAC or changing Power-Down status (Sleep/Wake). In addition, some Control codes perform two or more operations at the same time. For example, one such code loads DAC A, updates both outputs and Wakes the part up. The DACs can be loaded separately or together, but the outputs are always updated together. Register Loading Sequence See Figure 1. With CS/LD held low, data on the SDI input is shifted into the 16-bit Shift Register on the positive edge of SCK. The 4-bit Control code, A3-A0, is loaded first, then the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each case. Two don’t-care bits, X1 and X0, are loaded last. When the full 16-bit Input word has been shifted in, CS/LD is pulled high, causing the system to respond according to Table␣ 1. The clock is disabled internally when CS/LD is high. Note: SCK must be low when CS/LD is pulled low. Sleep Mode DAC control code 1110 b is reserved for the special Sleep instruction (see Table 1). In this mode, static power consumption is greatly reduced. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence using control code 1110 b (the DAC input code D9-D0 is ignored). To save instruction cycles, the DACs may be prepared with new input codes during Sleep (control codes 0001 b and 0010b); then, a single command (1000b) can be used both to wake the part and to update the output values. OPERATIOU
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
1662 F02
46 V CCREF
1662 F04
0.1µF Li-Ion BATTERY INPUT VIN ‡ 4.3V LTC1258-4.1 1 4.096V REF SDI SCK CS/LD V OUT A GND VCC LTC1662 VOUT B 0V TO 4.096V (4mV/BIT) 0V TO 4.096V (4mV/BIT)
1662 F03
0.1µF PACKAGE DESCRIPTIO U Dimensions in inches (millimeters) unless otherwise noted. 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) MSOP (MS8) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 0.021 – 0.006 (0.53 – 0.015) 0° – 6° TYP SEATING PLANE 0.007 (0.18) 0.040 – 0.006 (1.02 – 0.15) 0.012 (0.30) REF 0.006 – 0.004 (0.15 – 0.102) 0.034 – 0.004 (0.86 – 0.102) 0.0256 (0.65) BSC 12 3 4 0.193 – 0.006 (4.90 – 0.15) 8 7 6 5 0.118 – 0.004* (3.00 – 0.102) 0.118 – 0.004** (3.00 – 0.102) 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) N8 1098 0.100 (2.54) BSC 0.065 (1.651) TYP 0.045 – 0.065 (1.143 – 1.651) 0.130 – 0.005 (3.302 – 0.127) 0.020 (0.508) MIN0.018 – 0.003 (0.457 – 0.076) 0.125 (3.175) MIN 0.009 – 0.015 (0.229 – 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.325 +0.035 –0.015 +0.889 –0.3818.255() 12 3 4 87 6 5 0.255 – 0.015* (6.477 – 0.381) 0.400* (10.160) MAX *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) TYPICAL APPLICATIO SU Using the LTC1258 and the LTC1662 In a Portable Application Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2mA Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PART NUMBER DESCRIPTION COMMENTS LTC1661 Dual 10-Bit V OUT DAC in 8-Lead MSOP Package V CC = 2.7V to 5.5V, 60mA per DAC, Rail-to-Rail Output LTC1663 Single 10-Bit V OUT DAC with 2-Wire Interface in SOT-23 Package V CC = 2.7V to 5.5V, Internal Reference, 60mA LTC1664 Quad 10-Bit V OUT DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, 60mA per DAC, Rail-to-Rail Output LTC1665/LTC1660 Octal 8/10-Bit V OUT DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, 60mA per DAC, Rail-to-Rail Output LTC1446/LTC1446L Dual 12-Bit V OUT DACs in SO-8 Package with Internal Reference LTC1446: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 Dual 12-Bit V OUT DAC in SO-8 Package V CC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454/LTC1454L Dual 12-Bit V OUT DACs in SO-16 Package with Added Functionality LTC1454: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: V CC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1659 Single Rail-to-Rail 12-Bit V OUT DAC in 8-Lead MSOP Package Low Power Multiplying V OUT DAC. Output Swings from VCC: 2.7V to 5.5V GND to REF. REF Input Can Be Tied to V CC ª LINEAR TECHNOLOGY CORPORATION 2000 1662f LT/LCG 1000 4K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear-tech.com TYPICAL APPLICATIO U RELATED PARTS Ultralow Power DAC Optimizes Mixer Performance 3.3V VOUT A VOUT B 1CS/LD SDI SCK 4 6V CCREF GND7 0.1µF 560k LTC1662 DAC A DAC B 560k I + Q MIXER II P Q QQ P II P Q LO RF QP 3.9k 0.1% 3.9k 0.1% 3.3V 0.1µF LTC1258-2.5 2.5V
1662 TA01
3.9k 0.1% 3.9k 0.1% 3.9k 0.1% 3.9k 0.1% 3.9k, 0.1% 3.9k, 0.1%