LTC1871-7 LINER
Document overview
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Technical content
FEATURES
APPLICATIONS
DESCRIPTION
High Input Voltage, Current Mode Boost, Flyback and SEPIC Controller The L TC®1871-7 is a current mode, boost, fl yback and SEPIC controller optimized for driving 6V-rated MOSFETs in high voltage applications. The L TC1871-7 works equally well in low or high power applications and requires few components to provide a complete power supply solution. The switching frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 6V and a low shutdown quiescent current of 10μA make the L TC1871-7 well suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using the MODE/SYNC pin. The L TC1871-7 is available in the 10-lead MSOP package. Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply L, L T , L TC, L TM and Burst Mode are registered trademarks of Linear Technology Corporation. property of their respective owners.
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (Note 2) (Note 1) RUN I TH FB FREQ MODE/ SYNC SENSE V IN INTVCC GATE GND TOP VIEW MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T1871EMS-7#PBF L T1871EMS-7#TRPBF L TG4 10-Lead Plastic MSOP –40°C to 85°C L T1871IMS-7#PBF L T1871IMS-7#TRPBF L TBTR 10-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L T1871EMS-7 L T1871EMS-7#TR L TG4 10-Lead Plastic MSOP –40°C to 85°C L T1871IMS-7 L T1871IMS-7#TR L TBTR 10-Lead Plastic MSOP –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop V IN(MIN) Minimum Input Voltage 6 V I-Grade (Note 2) ● 6V IQ Input Voltage Supply Current (Note 4) Continuous Mode V MODE/SYNC = 5V , VFB = 1.4V , VITH = 0.75V 550 1000 μA VMODE/SYNC = 5V , VFB = 1.4V , VITH = 0.75V , I-Grade (Note 2)
- 600 1100 μA Burst Mode Operation, No Load V MODE/SYNC = 0V , VITH = 0.2V (Note 5) 280 500 μA VMODE/SYNC = 0V , VITH = 0.2V (Note 5), I-Grade (Note 2)
- 280 600 μA Shutdown Mode V RUN = 0V 12 25 μA VRUN = 0V , I-Grade (Note 2) ● 12 25 μA ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 8V , VRUN = 1.5V , RFREQ = 80k, VMODE/SYNC = 0V , unless otherwise specifi ed.
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 8V , VRUN = 1.5V , RFREQ = 80k, VMODE/SYNC = 0V , unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRUN+ Rising RUN Input Threshold Voltage 1.348 V VRUN– Falling RUN Input Threshold Voltage 1.223 1.198 1.248 1.273 1.298 V V VRUN(HYST) RUN Pin Input Threshold Hysteresis 50 100 150 mV I-Grade (Note 2) ● 35 100 175 mV IRUN RUN Input Current 56 0 n A VFB Feedback Voltage V ITH = 0.2V (Note 5) 1.218 1.212 1.230 1.242 1.248 V V VITH = 0.2V (Note 5), I-Grade (Note 2) ● 1.205 1.255 V IFB FB Pin Input Current V ITH = 0.2V (Note 5) 18 60 nA ΔVFB ΔVIN Line Regulation 6V ≤ V IN ≤ 30V 0.002 0.02 %/V 6V ≤ VIN ≤ 30V , I-Grade (Note 2) ● 0.002 0.02 %/V ΔVFB ΔVITH Load Regulation V MODE/SYNC = 0V , VITH = 0.5V to 0.9V (Note 5) ● – 1 –0.1 % VMODE/SYNC = 0V , VITH = 0.5V to 0.9V (Note 5) I-Grade (Note 2)
- – 1 –0.1 % ΔVFB(OV) ΔFB Pin, Overvoltage Lockout V FB(OV) – VFB(NOM) in Percent 2.5 6 10 % gm Error Amplifi er T ransconductance I TH Pin Load = ±5μA (Note 5) 600 μmho VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling I TH Voltage (Note 5) 0.3 V VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV Duty Cycle < 20%, I-Grade (Note 2) ● 100 200 mV ISENSE(ON) SENSE Pin Current (GATE High) V SENSE = 0V 35 70 μA ISENSE(OFF) SENSE Pin Current (GATE Low) V SENSE = 30V 0.1 5 μA Oscillator fOSC Oscillator Frequency R FREQ = 80k 250 300 350 kHz RFREQ = 80k, I-Grade (Note 2) ● 250 300 350 kHz Oscillator Frequency Range 50 1000 kHz I-Grade (Note 2) ● 50 1000 kHz DMAX Maximum Duty Cycle 87 92 97 % I-Grade (Note 2) ● 87 92 98.5 % fSYNC/fOSC Recommended Maximum Synchronized Frequency Ratio fOSC = 300kHz (Note 6) 1.25 1.30 fOSC = 300kHz (Note 6), I-Grade (Note 2) ● 1.25 1.30 tSYNC(MIN) MODE/SYNC Minimum Input Pulse Width V SYNC = 0V to 5V 25 ns tSYNC(MAX) MODE/SYNC Maximum Input Pulse Width V SYNC = 0V to 5V 0.8/f OSC ns VIL(MODE) Low Level MODE/SYNC Input Voltage 0.3 V I-Grade (Note 2) ● 0.3 V VIH(MODE) High Level MODE/SYNC Input Voltage 1.2 V I-Grade (Note 2) ● 1.2 V RMODE/SYNC MODE/SYNC Input Pull-Down Resistance 50 kΩ VFREQ Nominal FREQ Pin Voltage 0.62 V Low Dropout Regulator V INTVCC INTVCC Regulator Output Voltage V IN = 8V 6.5 7 7.5 V VIN = 8V , I-Grade (Note 2) ● 6.5 7 7.5 V
FB Voltage vs Temp FB Voltage Line Regulation FB Pin Current vs Temperature ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 8V , VRUN = 1.5V , RFREQ = 80k, VMODE/SYNC = 0V , unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS UVLO INTVCC Undervoltage Lockout Threshold Rising INTV CC Falling INTVCC UVLO Hysteresis 5.6 4.6 1.0 V V V ΔV INTVCC ΔVIN1 INTVCC Regulator Line Regulation 8V ≤ V IN ≤ 15V 8 25 mV ΔVINTVCC ΔVIN2 INTVCC Regulator Line Regulation 15V ≤ V IN ≤ 30V 70 200 mV VLDO(LOAD) INTVCC Load Regulation 0 ≤ I INTVCC ≤ 20mA, VIN = 8V – 2 –0.2 % VDROPOUT INTVCC Regulator Dropout Voltage V IN = 6V , INTVCC Load = 20mA 280 mV GATE Driver t r GATE Driver Output Rise Time C L = 3300pF (Note 7) 17 100 ns tf GATE Driver Output Fall Time C L = 3300pF (Note 7) 8 100 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC1871E-7 is guaranteed to meet performance specifi cations from 0°C to 70°C junction temperature. Specifi cations over the – 40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC1871I-7 is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: T J is calculated from the ambient temperature TA and power dissipation PD according to the following formula: T J = TA + (PD • 120°C/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG • fOSC). See Applications Information. Note 5: The L TC1871-7 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V). Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a signifi cantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels. TYPICAL PERFORMANCE CHARACTERISTICS TEMPERATURE (°C) –50 FB VOLTAGE (V) 1.23 1.24 150
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1.22 1.21 0 50 100–25 25 75 125 1.25 VIN (V)
1.229 FB VOLTAGE (V)
1.230 1.231 51 0 1 5 2 0
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TEMPERATURE (°C) –50 FB PIN CURRENT (nA) –25 250 50 100 75
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TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Mode IQ vs VIN Shutdown Mode IQ vs Temperature Burst Mode IQ vs VIN Burst Mode IQ vs Temperature Dynamic I Q vs Frequency Gate Drive Rise and Fall Time vs CL RUN Thresholds vs VIN RUN Thresholds vs Temperature R T vs Frequency VIN (V) SHUTDOWN MODE IQ (μA) 10 20 30 40
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TEMPERATURE (°C) –50 SHUTDOWN MODE IQ (μA) –25 0 25 50
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VIN = 8V VIN (V) Burst Mode IQ (μA) 100 200 300 400 600 10 20
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TEMPERATURE (°C) –50 Burst Mode IQ (μA) 200 500 0 50 75
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–25 25 100 125 150 FREQUENCY (kHz) IQ (mA) 800
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CL = 3300pF IQ(TOT) = 600μA + Qg • f CL (pF) TIME (ns) 2000 4000 6000 8000
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VIN (V) 1.2 RUN THRESHOLDS (V) 1.3 1.4 10 20 30 40
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1.5 TEMPERATURE (°C) –50 RUN THRESHOLDS (V) 1.30 1.35 150
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1.25 1.20 0 50 100–25 25 75 125 1.40 FREQUENCY (kHz) 100 RT (kΩ) 300 1000
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200 1000 9008007006005004000
TYPICAL PERFORMANCE CHARACTERISTICS Frequency vs Temperature Maximum Sense Threshold vs Temperature SENSE Pin Current vs Temperature INTVCC Load Regulation INTV CC Line Regulation INTVCC Dropout Voltage vs Current, Temperature RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and pro- gramming the start-up threshold for the converter . The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the V IN supply current is kept to a low value (typ 10μA). The Absolute Maximum Rating for the voltage on this pin is 7V . ITH (Pin 2): Error Amplifi er Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V . FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulaton is 1.230V . FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V . PIN FUNCTIONS TEMPERATURE (°C) –50
275 GATE FREQUENCY (kHz)
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–25 25 100 125 150 TEMPERATURE (°C) –50
140 MAX SENSE THRESHOLD (mV)
–25 0 25 50
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TEMPERATURE (°C) –50 SENSE PIN CURRENT (μA) 0 50 75
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–25 25 100 125 150 GATE HIGH VSENSE = 0V INTVCC LOAD (mA) INTVCC VOLTAGE (V) 7.0 30 50 80
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6.9 6.8 10 20 40 60 70 VIN = 8V VIN (V) 6.9 INTVCC VOLTAGE (V) 7.0 7.1 10 20 30 40
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7.2 51 5 25 35 INTVCC LOAD (mA) DROPOUT VOLTAGE (mV) 150 200 250 500 350 5 10
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150°C 75°C 125°C 25°C –50°C 0°C
MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTV CC, or if an external logic-level synchronization signal is ap- plied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode. GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output. INTVCC (Pin 8): The Internal 7V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7μF low ESR tantalum or ceramic ca- pacitor . This 7V regulator has an undervoltage lockout circuit with 5.6V and 4.6V rising and falling thresholds, respectively. V IN (Pin 9): Main Supply Pin. Must be closely decoupled to ground. SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to a resistor in the source of the power MOSFET . Alternatively, the SENSE pin may be con- nected to the drain of the power MOSFET , in applications where the maximum V DS is less than 36V . Internal leading edge blanking is provided for both sensing methods. BLOCK DIAGRAM +1.230V 85mV OV 50k EA UV TO START-UP CONTROL BURST COMPARATOR S R Q LOGIC PWM LATCH CURRENT COMPARATOR 0.30V 1.230V +5.6V UP 4.6V DOWN 1.230V SLOPE 1.230V ILOOP FB ITH gm MODE/SYNC FREQ INTVCC
8 LDO
1.248V RUN 0.6V
resistor , as shown in Figure 2. current is typically only 10μA. the duration of an output overvoltage condition. the output voltage to the maximum rating for this pin (36V). voltages signifi cantly greater than 36V . MODE/SYNC pin should be connected to ground). ITH pin sets the current comparator C1 input threshold. maintaining output regulation. Figure 2. Using the SENSE Pin On the L TC1871-7
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lustrating Burst Mode operation are shown in Figure 3. of operation are shown in Figure 4. pense of overall system effi ciency of light loads. Figure 3. L TC1871-7 Burst Mode Operation Figure 4. L TC1871-7 Low Output Current Operation with
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rising edge of the external clock signal. frequency is shown in Figure 6. logic circuitry within the L TC1871-7, as shown in Figure 7. with a minimum of 4.7μF tantalum or ceramic capacitor . currents required by the MOSFET gate driver . used to drive the gate capacitance of the power MOSFET . Figure 5. MODE/SYNC Clock Input and Switching Figure 6. Timing Resistor (RT) Value
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As an example, consider a power supply with V IN =10V . performance devices being introduced almost yearly. as shown in Figure 1, allowing remote voltage sensing. Figure 7. Bypassing the LDO Regulator and Gate Driver Supply
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maximum value of R1 of about 250k). Figure 8. This allows users to accurately program an input 100mV of hysteresis to increase noise immunity. The resistor R1 is typically chosen to be less than 1M. as shown in Figure 8c, for “always on” operation.
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A basic L TC1871-7 application circuit is shown in Figure 9. (single-ended primary inductance converter). voltages from low input supply voltages. Figure 9. A High Effi ciency 42V , 1.5A Automotive Boost Converter
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15% greater than the average. range of 20% to 40% of the maximum average current. highest inductor current) and maximum output current. during the off-time of the switch, as shown in Figure 10. the drain voltage will settle to the input voltage. Figure 10. Discontinuous Mode Waveforms
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- IO(MAX) The VSENSE(MAX) term is typically 150mV at low duty cycle, and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 11. It is worth noting that the 1 – D MAX relationship between IO(MAX) and RSENSE can cause boost converters with a wide input range to experience a dramatic range of maximum input and output current. This should be taken into con- sideration in applications where it is important to limit the maximum current drawn from the input supply.
Figure 11. Maximum SENSE Threshold Votlage vs Duty Cycle
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in most high voltage L TC1871-7 applications. (not just on a lab breadboard!) for excessive ringing. MOSFET , the power dissipated by the device must be known. listed in the manufacturer’s data sheet.
- RDS(ON) •D• T +k•V O 2 • IO(MAX ) 1– D( )
- C RSS •f The fi rst term in the equation above represents the I 2R losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The ρ T term accounts for the temperature coeffi cient of the RDS(ON) of the MOSFET , which is typically 0.4%/°C. Figure 12 illustrates the variation of normalized R DS(ON) over temperature for a typical power MOSFET .
used in the iterative calculation process. must withstand is equal to the regulator output voltage. Figure 12. Normalized RDS(ON) vs Temperature
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2.0 The RTH(JA) to be used in this equation normally includes
the board to the ambient temperature in the enclosure. between the ESR step and the charging/discharging ΔV.
be used to supply the required bulk C. to meet size or height requirements in the design. RMS current handling requirements of the application. and high ripple current ratings. Figure 13. Switching Waveforms for a Boost Converter
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L is substantially less than I BURST. cycles for the current to ramp back up to I BURST(PEAK). Table 1. Recommended Component Manufacturers
During this inductor charging interval, the output capacitor must supply the load current and a signifi cant droop in the output voltage can occur . Generally, it is a good idea to choose a value of inductor ΔI L between 25% and 40% of IIN(MAX). The alternative is to either increase the value of the output capacitor or disable Burst Mode operation using the MODE/SYNC pin. Burst Mode operation can be defeated by connecting the MODE/SYNC pin to a high logic-level voltage (either with a control input or by connecting this pin to INTV CC). In this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduction mode (CCM) at full load, down into deep discontinuous conduction mode (DCM) at light load. Prior to skipping pulses at very light load (i.e., <5% of full load), the control- ler will operate with a minimum switch on-time in DCM. Pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. Effi ciency Considerations The effi ciency of a switching regulator is equal to the out- put power divided by the input power (¥100%). Percent effi ciency can be expressed as: % Effi ciency = 100% – (L1 + L2 + L3 + …), where L1, L2, etc. are the individual loss components as a percentage of the input power . It is often useful to analyze individual losses to determine what is limiting the effi ciency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in L TC1871-7 application circuits: 1. The supply current into V IN. The VIN current is the sum of the DC supply current IQ (given in the Electrical Char- acteristics) and the MOSFET driver and control currents. The DC supply current into the V IN pin is typically about 650μA and represents a small power loss (much less than 1%) that increases with V IN. The driver current results from switching the gate capacitance of the power MOSFET ; this current is typically much larger than the DC current. Each time the MOSFET is switched on and then off, a packet of gate charge Q G is transferred from INTVCC to ground. The resulting dQ/dt is a current that must be supplied to the INTVCC capacitor through the VIN pin by an external supply. If the IC is operating in CCM: I Q(TOT) ≈ IQ = f • QG P IC = VIN • (IQ + f • QG) 2. Power MOSFET switching and conduction losses: PFET = IO(MAX ) 1– DMAX
- RDS(ON) •DMAX • T + k•V O 2 • IO(MAX ) 1– DMAX
- C RSS •f 3. The I2R losses in the sense resistor can be calculated almost by inspection. PR(SENSE) = IO(MAX ) 1– DMAX
- R SENSE •DMAX 4. The losses in the inductor are simply the DC input cur- rent squared times the winding resistance. Expressing this loss as a function of the output current yields: PR(WINDING)= IO(MAX ) 1– DMAX
- R W 5. Losses in the boost diode. The power dissipation in the boost diode is: P DIODE = IO(MAX) • VD The boost diode can be a major source of power loss in a boost converter . For 13.2V input, 42V output at 1.5A example given in Figure 9, a Schottky diode with a 0.4V forward voltage would dissipate 600mW , which represents about 1% of the input power . Diode losses can become signifi cant at low output voltages where the forward voltage is a signifi cant percentage of the output voltage. 6. Other losses, including C IN and CO ESR dissipation and inductor core losses, generally account for less than 2% of the total losses.
Checking T ransient Response The regulator loop response can be verifi ed by looking at the load transient response at minimum and maximum V IN. Switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. When the load step occurs, V O immediately shifts by an amount equal to ( ΔILOAD)(ESR), and then C O begins to charge or discharge (depending on the direction of the load step) as shown in Figure 14. The regulator feedback loop acts on the resulting error amp output signal to return V O to its steady-state value. During this recovery time, VO can be monitored for overshoot or ringing that would indicate a stability problem. A second, more severe transient can occur when con- necting loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C O, causing a nearly instantaneous drop in VO. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. Boost Converter Design Example The design example given here will be for the circuit shown in Figure 9. The input voltage is 8V to 28V , and the output is 42V at a maximum load current of 1.5A. 1. The maximum duty cycle is: D = VO + VD –VIN VO + VD = 42 + 0.4 – 8 42 + 0.4 = 81.1% 2. Pulse-skip operation is chosen so the MODE/SYNC pin is shorted to INTVCC. 3. The operating frequency is chosen to be 250kHz to reduce the size of the inductor . From Figure 5, the resistor from the FREQ pin to ground is 100k. 4. An inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: IIN(PEAK) = 1+ IO(MAX ) 1– DMAX = 1.2 • 1.5 1– 0.81= 9.47A The inductor ripple current is: IL = • IO(MAX ) 1– DMAX = 0.4 • 1.5 1– 0.81= 3.2A And so the inductor value is: L = VIN(MIN) IL • f •DMAX = 8 3.2 • 250k • 0.81= 8.1μH Figure 14a. Load T ransient Response for the Circuit in Figure 9 Figure 14b. Load T ransient Response for the Circuit in Figure 9 VOUT 500mV/DIV IOUT 0.5A/DIV 0.5A 250μs/DIV
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1.5A VIN = 8V VOUT 500mV/DIV IOUT 0.5A/DIV 0.5A 250μs/DIV
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1.5A VIN = 28V
tion current of greater than 13.3A.
- Because the duty cycle is 81%, the maximum SENSE
- 1.5 •IO(MAX) A 1W , 5mΩ resistor is used in this design. 6. The MOSFET chosen is a Vishay/Siliconix Si7370DP , which has a BVDSS of greater than 60V and an RDS(ON) of less than 13mΩ at a VGS of 6V . 7. The diode for this design must handle a maximum DC output current of 1.5A and be rated for a minimum reverse voltage of V OUT, or 42V . A 3A, 60V diode from Diodes Inc. (B360B) is chosen. 8. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 50mV , the bulk C needs to be greater than: COUT IOUT(MAX) 0.01• VOUT • f = 1.5 0.01• 42 • 250k = 14μF The RMS ripple current rating for this capacitor needs to exceed: IRMS(COUT) IO(MAX )• VO –VIN(MIN) VIN(MIN) 1.5 • 42 – 8 8 = 3.09A T o satisfy the low ESR, high frequency decoupling requirements, two 10μF , 50V , X5R ceramic capacitors are used (TDK part number C5750X5R1H106M). In parallel with these, two 68μF , 100V electrolytic ca- pacitors are used (Sanyo part number 100CV68FS). Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents fl ow. 9. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup a 560μF , 50V Sanyo electrolytic (50MV560AXL), in parallel with two 10μF , 100V TDK ceramic capacitors (C5750X5R1H106M) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 10A!). As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals.
Figure 15. Switching Waveforms for the Converter
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- In order to minimize switching noise and improve out-
possible to minimize series resistance and inductance.
- Beware of ground loops in multiple layer PC boards. T ry
the small-signal components. and ESL 4.7μF ceramic capacitor works well here.
- The high di/dt loop from the bottom terminal of the
the power MOSFET and increase HF noise on the output.
- Check the stress on the power MOSFET by measur-
equal (some are more equal than others).
- Place the small-signal components away from high fre-
Figure 16. Switching Waveforms for the Figure 17. Effi ciency vs Load Current and Input Voltage
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- Minimize the capacitance between the SENSE pin trace
- For optimum load regulation and true remote sens-
connection), staying away from any high dV/dt traces. to keep the high impedance FB node short. Figure 18. L TC1871-7 Boost Converter Suggested Layout Figure 19. L TC1871-7 Boost Converter Layout Diagram
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- For applications with multiple switching power convert-
this could interfere with the operation of the L TC1871-7. suffi cient to prevent current sharing problems. SEPIC converter shown in Figure 20 uses two inductors. output is short-circuit protected. follows assumes L1 = L2 = L. Figure 20. SEPIC Topolgy and Current Flow Figure 21. SEPIC Converter Switching Waveforms
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The maximum output voltage for a SEPIC converter is: VO(MAX )= VIN + VD() DMAX 1– DMAX –V D 1– DMAX The maximum duty cycle of the L TC1871-7 is typically 92%. SEPIC Converter: The Peak and Average Input Currents The control circuit in the L TC1871-7 is measuring the input current (using a sense resistor in the MOSFET source), so the output current needs to be refl ected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power , the maximum input current for a SEPIC converter is: IIN(MAX) =IO(MAX )• DMAX 1– DMAX The peak input current is: IIN(PEAK) = 1+
- IO(MAX )• DMAX 1– DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. The constant ‘χ’ represents the fraction of ripple current in the inductor relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30 and the peak current is 15% greater than the average. It is worth noting here that SEPIC converters that operate at high duty cycles (i.e., that develop a high output volt- age from a low input voltage) can have very high input currents, relative to the output current. Be sure to check that the maximum load current will not overload the input supply. SEPIC Converter: Inductor Selection For most SEPIC applications the equal inductor values will fall in the range of 10μH to 100μH. Higher values will reduce the input ripple voltage and reduce the core loss. Lower inductor values are chosen to reduce physical size and improve transient response. Like the boost converter , the input current of the SEPIC converter is calculated at full load current and minimum input voltage. The peak inductor current can be signifi cantly higher than the output current, especially with smaller in- ductors and lighter loads. The following formulas assume CCM operation and calculate the maximum peak inductor currents at minimum V IN: IL1 (PEAK)= 1+
- IO(MAX )• VO + VD VIN(MIN) IL2(PEAK) = 1+
- IO(MAX )• VIN(MIN)+ VD VIN(MIN) The ripple current in the inductor is typically 20% to 40% (i.e., a range of ‘ χ’ from 0.20 to 0.40) of the maximum average input current occurring at VIN(MIN) and IO(MAX) and ΔIL1 = ΔIL2. Expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: L = VIN(MIN) IL • f •DMAX where IL = •IO(MAX )• DMAX 1– DMAX By making L1 = L2 and winding them on the same core, the value of inductance in the equation above is replace by 2L due to mutual inductance. Doing this maintains the same ripple current and energy storage in the inductors. For example, a Coiltronix CTX10-4 is a 10μH inductor with two windings. With the windings in parallel, 10μH inductance is obtained with a current rating of 4A (the number of turns hasn’t changed, but the wire diameter has doubled). Split- ting the two windings creates two 10μH inductors with a current rating of 2A each. Therefore, substituting 2L yields the following equation for coupled inductors: L1=L2 = VIN(MIN) 2• IL • f •DMAX Specify the maximum inductor current to safely handle IL(PK) specifi ed in the equation above. The saturation current
rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor cur- rent) and maximum output current. SEPIC Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BV DSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate- to-source voltage, the gate-to-source and gate-to-drain charges (Q GS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET’s thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 7V INTVCC low dropout regulator . Consequently, 6V rated threshold MOSFETs are required in most L TC1871-7 applications. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages (V O + VIN). As a result, careful attention must be paid to the BV DSS specifi cations for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less. Check the switching waveforms directly across the drain and source terminals of the power MOSFET to ensure the V DS remains below the maximum rating for the device. Sense Resistor Selection During the MOSFET’s on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor cur- rent is therefore limited to 150mV/R SENSE. The relationship between the maximum load current, duty cycle and the sense resistor is: RSENSE VSENSE(MAX) IO(MAX)
- 1
- 1 VO + VD VIN(MIN) + 1 The V SENSE(MAX) term is typically 150mV at low duty cycle and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 11. The constant ‘χ’ in the denominator represents the ripple current in the inductors relative to their maximum cur- rent. For example, if 30% ripple current is chosen, then χ = 0.30. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET , the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself. As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (load, line and temperature) and for the worst-case specifi cations for V SENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer’s data sheet. The power dissipated by the MOSFET in a SEPIC converter is: PFET = IO(MAX )• D 1– D
- RDS(ON) •D• T + k• V IN + VO() 2 •IO(MAX )• D 1– D •C RSS •f The fi rst term in the equation above represents the I 2R losses in the device and the second term, the switching losses. The constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The ρT term accounts for the temperature coeffi cient of the RDS(ON) of the MOSFET , which is typically 0.4%/°C. Figure 12 illustrates the variation of normalized R DS(ON) over temperature for a typical power MOSFET .
From a known power dissipated in the power MOSFET , its junction temperature can be obtained using the following formula: T J = TA + PFET •RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. This value of T J can then be used to check the original assumption for the junction temperature in the iterative calculation process. SEPIC Converter: Output Diode Selection To maximize effi ciency, a fast-switching diode with low forward drop and low reverse leakage is desired. The output diode in a SEPIC converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to V IN(MAX) + V O. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ID(PEAK) = 1+
- IO(MAX )• VO + VD VIN(MIN) + 1 The power dissipated by the diode is: P D = IO(MAX) • VD and the diode junction temperature is: T J = TA + PD • RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. SEPIC Converter: Output Capacitor Selection Because of the improved performance of today’s electro- lytic, tantalum and ceramic capacitors, engineers need to consider the contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL, and bulk C) on the output voltage ripple waveform are illustrated in Figure 21 for a typical coupled-inductor SEPIC converter . The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging ΔV. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging ΔV . This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modifi ed. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the fol- lowing equation: ESRCOUT 0.01• VO ID(PEAK) where: ID(PEAK) = 1+
- IO(MAX )• VO + VD VIN(MIN) + 1 For the bulk C component, which also contributes 1% to the total ripple: COUT IO(MAX ) 0.01• VO • f For many designs it is possible to choose a single capacitor type that satisfi es both the ESR and bulk C requirements for the design. In certain demanding applications, however , the ripple voltage can be improved signifi cantly by con- necting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform
should be verifi ed on a dedicated PC board (see Board Layout section for more information on component place- ment). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look signifi cantly worse than they would be on a properly designed PC board. The output capacitor in a SEPIC regulator experiences high RMS ripple currents, as shown in Figure 21. The RMS output capacitor ripple current is: IRMS(COUT) =IO(MAX )• VO VIN(MIN) Note that the ripple current ratings from capacitor manu- facturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. SEPIC Converter: Input Capacitor Selection The input capacitor of a SEPIC converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. The input voltage source impedance determines the size of the input capacitor which is typi- cally in the range of 10μF to 100μF . A low ESR capacitor is recommended, although it is not as critical as for the output capacitor . APPLICATIONS INFORMATION The RMS input capacitor ripple current for a SEPIC con- verter is: IRMS(CIN)= 1
- IL Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! SEPIC Converter: Selecting the DC Coupling Capacitor The coupling capacitor C1 in Figure 20 sees nearly a rectan- gular current waveform as shown in Figure 21. During the switch off-time the current through C1 is I O(VO/VIN) while approximately –IO fl ows during the on-time. This current waveform creates a triangular ripple voltage on C1: VC1 (PP) = IO(MAX ) C1• f • VO VIN + VO + VD The maximum voltage on C1 is then: VC1 (MAX)= VIN + VC1 (PP) which is typically close to V IN(MAX). The ripple current through C1 is: IRMS(C1 )=IO(MAX )• VO + VD VIN(MIN) The value chosen for the DC coupling capacitor normally starts with the minimum value that will satisfy 1) the RMS current requirement and 2) the peak voltage requirement (typically close to V IN). Low ESR ceramic and tantalum capacitors work well here.
Output Effi ciency at 3.3V Output A 48V Input Flyback Converter Confi gurable to 3.3V or 5V Outputs Output Effi ciency at 5V Output 100k 100k VIN 36V TO 72V 10V 26.7k 82.5k 12.4k R2* 21k *R2 = 38.3k FOR VOUT = 5V 604k 1nF 0.1μF 2.2μF 100V 100μF 6.3V V OUT 3.3V 3A MAXT1B UPS840 CTX-002-15242 T1A FDC2512 ALL CAPACITORS ARE CERAMIC X5R TYPER3 0.1Ω 4.7μF
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V FB VIN GATE SENSE INTVCC GND L TC1871-7 MMBTA42 ILOAD (A) EFFICIENCY (%) 1 234
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ILOAD (A) EFFICIENCY (%) 1 234
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1.2A Automotive LED Headlamp Boost Converter Dual Output Cell Phone Base Station Flyback Converter RUN ITH FB FREQ MODE/SYNC SENSE V IN INTVCC GATE GND L TC1871-7 33V 33VD6 5V
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4.7MR6 V IN GND RUN INPUT 0V TO 5V DIMMING INPUT 47μF 20V 187k 1% C8 100nF R10 300k R15 0.20Ω 0.5W R13 17.8k 4.7μF X5R C5: SANYO OS-CON 20SP47M C7: ITW PAKTRON 106K100CS4 L1: MAGNETICS INC 58206-A2 WITH 29T 18AWG C10 4.7μF R14 R12 4.02k R11 0.006Ω SILICONIX SUP75N08-9L 10μF 100V TO LEDS FROM LEDS USE 68V OR 75V SINGLE ZENER IRF12CW10L1 RUN ITH FB FREQ MODE/SYNC SENSE V IN INTVCC GATE GND L TC1871-7 33k 75Ω 150k R13 0.082Ω R10 64.9k
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C3, C11: TDK C3225X5R0J107M C4: SANYO POSCAP 10 TPB33M C7: TDK C4532X7R1H335M C13, C13A: SANYO POSCAP 4TPB470M L1: COILCRAFT DO1608 103 T1: COIL TRONICS VP4-0047 C13 470μF 20.5k 43.2k 12.5k 5.5V 500mA 3.3V R14 ISO1 MOC207 R12 80k R11 12.5k 33k Si4482DY C15 4.7μF C13A 470μF C11 100μF 100pF 200V C12 15nF C10 330nF 33k C16 10nF 1kV 100μF 33μF 123 TAB C17 1μF C14 1nF BAT54 VP4-0047 1A 40V UPS840 1nF 1C6 1μF 35V V IN 18V TO 33V SYNC SIGNAL 320kHz 0V TO 2.5V 22μF 50V 3.3μF 50V 10V 10μH COL COMP V RTOP REF RMID GNDF GNDS L T1431 SHDN IN GND GND L T1963 OUT ADJ
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. TYPICAL APPLICATIONS 10-Lead Plastic MSOP (Reference L TC DWG # 05-08-1661) Automotive SEPIC Converter PACKAGE DESCRIPTION MSOP (MS) 0307 REV E 0.53 ± 0.152 (.021 ± .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 ± 0.152 (.193 ± .006) 0.497 ± 0.076 (.0196 ± .003) REF8910 7 6 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ± 0.038 (.0120 ± .0015) TYP 0.50 (.0197) BSC 0.1016 ± 0.0508 (.004 ± .002) RUN ITH FB FREQ MODE/SYNC SENSE INTV CC GATE L TC1871-7 V IN FMMT451 VP5-0155 GND R47 133k R59 0.005Ω Si4486EY SO-8 R61 12.4k R60 124k CR22 1N4148 CR21 MBR10100 C47 6800pF C49 4.7μF C50 4μF X7R C46 100pF VBATT 8V TO 25V R45 33.2k R43 13.3k R37 75k R46 47k CR4 BZX84C15V 11 2
- 9 21 1
- 8 31 0
- 7 C51 150μF 35V
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4.7μF X7R C53 22μF 16V X5R C57 10μF X5R (OPTIONAL HF FIL TER) C55 4.7μF 16V X7R V OUT 13.5V 150Ω 3A BEAD 1B (OPTIONAL HF FIL TER)
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2002 LT 0108 REV C • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION A Small, Nonisolated 12V Flyback Telecom Housekeeping Supply PART NUMBER DESCRIPTION COMMENTS LT
1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
L TC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V L TC1700 No R SENSE Synchronous Step-Up Controller Up to 95% Effi ciency, Operation as Low as 0.9V Input L TC1871 Wide Input Range, No R SENSE Controller Operation as Low as 2.5V Input, Boost Flyback,SEPIC L TC1872 SOT-23 Boost Controller Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode L T1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V ≤ V IN ≤ 16V , Miniature Design L T1931 Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Conversion, Miniature Design L TC3401/L TC3402 1A/2A 3MHz Synchronous Boost Converters Up to 97% Effi ciency, Very Small Solution, 0.5V ≤ V IN ≤ 5V L TC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, Current Mode 200kHz Operation L TC3806 Synchronous Flyback Controller High Effi ciency, Improves Cross Regulation in Multiple Output Designs, Current Mode, 3mm × 4mm 12-Pin DFN Package RUN ITH FB FREQ MODE/SYNC SENSE V IN INTVCC GATE GND L TC1871-7 RT 120k f = 200kHz T1: COIL TRONICS VP1-0076 M1: FAIRCHILD FDC2512 (150V , 0.5Ω) Q1: ZETEX FMMT625 (120V) 4.7μF X5R C IN 2.2μF 100V X7R R S 0.12Ω 1, 2, 3 (SERIES) VIN 36V TO 72V 4, 5, 6 (PARALLEL) RC 3.4k CC1 2.2nF CC2 47pF 1nF OPTIONAL 26.7k COUT 47μF X5R VOUT 12V 0.4AR1 604k 12.4k 100k 10Ω 9.1VUV+ = 31.8V UV– = 29.5V D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V) D2: ON SEMICONDUCTOR MMSD4148T11 D3: INTERNATIONAL RECTIFIER 10BQ060 110k 0.1μF X5R