LTDCJ

LT3580 LINER

Document overview

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

Converter with 2A Switch, Soft-Start, and Synchronization The LT®3580 is a PWM DC/DC converter containing an internal 2A, 42V switch. The LT3580 can be confi gured as either a boost, SEPIC or inverting converter. Capable of generating 12V at 550mA or –12V at 350mA from a 5V input, the LT3580 is ideal for many local power supply designs. The LT3580 has an adjustable oscillator, set by a resistor from the RT pin to ground. Additionally, the LT3580 can be synchronized to an external clock. The free running or synchronized switching frequency range of the part can be set between 200kHz and 2.5MHz. The LT3580 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjust- able undervoltage lockout function. Additional features such as frequency foldback and soft- start are integrated. The LT3580 is available in tiny 3mm × 3mm 8-lead DFN and 8-lead MSOP packages. 1.2MHz, 5V to 12V Boost Converter Achieves over 88% Effi ciency n 2A Internal Power Switch n Adjustable Switching Frequency n Single Feedback Resistor Sets VOUT n Synchronizable to External Clock n High Gain SHDN Pin Accepts Slowly Varying Input Signals n Wide Input Voltage Range: 2.5V to 32V n Low V CESAT Switch: 300mV at 1.5A (Typical) n Integrated Soft-Start Function n Easily Confi gurable as a Boost or Inverting Converter n User Confi gurable Undervoltage Lockout (UVLO) n Tiny 8-Lead 3mm × 3mm DFN and 8-Lead MSOP Packages n VFD Bias Supplies n TFT-LCD Bias Supplies n GPS Receivers n DSL Modems n Local Power Supply Effi ciency and Power Loss L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 10μF VOUT 12V 550mA 4.2μH 130k VIN VIN SW

3580 TA01

1nF0.1μF2.2μF LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 400

3580 TA01b

(Note 1) TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1 FB VC V IN SW SYNC SS RT SHDN TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB FB VC V IN SW SYNC SS RT SHDN TOP VIEW MS8E PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 35°C/W TO 40°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3580EDD#PBF LT3580EDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3580IDD#PBF LT3580IDD#TRPBF LCXY 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT3580EMS8E#PBF LT3580EMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –40°C to 125°C LT3580IMS8E#PBF LT3580IMS8E#TRPBF LTDCJ 8-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ Operating Junction Temperature Range

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3580E is guaranteed to meet performance specifi cations from 0°C to 125°C junction temperature. Specifi cations over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3580I is guaranteed over the full –40°C to 125°C operating junction temperature range. ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range l 2.5 32 V Positive Feedback Voltage l 1.195 1.215 1.230 V Negative Feedback Voltage l 05 1 2 m V Positive FB Pin Bias Current V FB = Positive Feedback Voltage, Current Into Pin l 81 83.3 85 μA Negative FB Pin Bias Current V FB = Negative Feedback Voltage, Current Out of Pin l 81 83.3 85.5 μA Error Amplifi er Transconductance 230 μmhos Error Amplifi er Voltage Gain 70 V/V Quiescent Current V SHDN = 2.5V, Not Switching 1 1.5 mA Quiescent Current in Shutdown V SHDN = 0V 0 1 μA Reference Line Regulation 2.5V ≤ V IN ≤ 32V 0.01 0.05 %/V Switching Frequency, f OSC RT = 45.3k RT = 464k l l 1.8 180 200 2.2 220 MHz kHz Switching Frequency in Foldback Compared to Normal f OSC 1/4 Ratio Switching Frequency Set Range SYNCing or Free Running l 200 2500 kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.4 V SYNC Clock Pulse Duty Cycle V SYNC = 0V to 2V 35 65 % Recommended Minimum SYNC Ratio f SYNC/fOSC 3/4 Minimum Off-Time 60 nS Minimum On-Time 100 nS Switch Current Limit Minimum Duty Cycle (Note 3) Maximum Duty Cycle (Notes 3, 4) l l 2.2 1.6 2.5 1.9 2.8 2.6 A A Switch VCESAT ISW = 1.5A 300 mV Switch Leakage Current V SW = 5V 0.01 1 μA Soft-Start Charging Current V SS = 0.5V l 468 μ A SHDN Minimum Input Voltage High Active Mode, SHDN Rising Active Mode, SHDN Falling l l 1.27 1.24 1.32 1.29 1.38 1.33 V V SHDN Input Voltage Low Shutdown Mode l 0.3 V SHDN Pin Bias Current V SHDN = 3V VSHDN = 1.3V VSHDN = 0V 9.7 11.6 13.4 0.1 μA μA μA Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: Current limit measured at equivalent switching frequency of 2.5MHz. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability.

TYPICAL PERFORMANCE CHARACTERISTICS Switch Current Limit at 1MHz Switch Saturation Voltage Switch Current Limit at Minimum Duty Cycle Switch Current Limit at Minimum Duty Cycle Positive Feedback Voltage Switching Waveforms for Figure 14 Circuit Oscillator Frequency Oscillator Frequency During Soft-Start Internal UVLO TA = 25°C unless otherwise specifi ed DUTY CYCLE (%) SWITCH CURRENT LIMIT (A)0.5 1.0 1.5 2.0 30 50 70 90

3580 G01

2.5 20 40 60 80 SWITCH CURRENT (A) SATURATION VOL TAGE (mV) 200 250 300

3580 G02

0.5 1 1.5 400 350 SS VOL TAGE (mV) SWITCH CURRENT (A) 0.5 1.0 1.5 2.0 200 400 600 800

3580 G03

2.5 TEMPERATURE (°C) –50 SWITCH CURRENT LIMIT (A) 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100

3580 G04

TEMPERATURE (°C) –50 –25

1.19 FB VOLTAGE (V)

1.21 1.24 0 50 75

3580 G05

1.20 1.23 1.22 25 100 125 VOUT 50mV/DIV AC COUPLED VSW 10V/DIV IL 0.5A/DIV 200ns/DIV

3580 G06

TEMPERATURE (°C) –50 FREQUENCY (MHz) 1.9 2.1 2.3

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1.7 1.5 1.1 0 50 100 1.3 2.7 RT = 35.7k 2.5 RT = 75k FB VOLTAGE (V) NORMALIZED OSCILLATOR FREQUENCY (F/FNOM) TA = 35°C TA = 25°C TA = 100°C 0.2 0.4 INVERTING CONFIGURATIONS BOOSTING CONFIGURATIONS 0.6 0.8

3580 G08

1.0 1.2 TEMPERATURE (°C) –50

2.20 VIN VOLTAGE (V)

2.22 2.26 2.28 2.30 2.40 2.34 0 50

3580 G09

2.24 2.36 2.38 2.32 100

TYPICAL PERFORMANCE CHARACTERISTICS SHDN Pin Current SHDN Pin Current Active/Lockout Threshold TA = 25°C unless otherwise specifi ed PIN FUNCTIONS FB (Pin 1): Positive and Negative Feedback Pin. For a boost or inverting converter, tie a resistor from the FB pin to V OUT according to the following equations: RFB = VOUT 1.215() 83.3 • 106 ; Boost or SEPIC Converter RFB = VOUT + 5mV() 83.3 • 106 ; Inverting Converter VC (Pin 2): Error Amplifi er Output Pin. Tie external com- pensation network to this pin. VIN (Pin 3): Input Supply Pin. Must be locally bypassed. SW (Pin 4): Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area con- nected to this pin to minimize EMI. SHDN (Pin 5): S h u t d o w n P i n . I n c o n j u n c t i o n w i t h t h e U V L O ( u n d e r v o l t a g e l o c k o u t ) c i r c u i t , t h i s p i n i s u s e d to enable/disable the chip and restart the soft-start sequence. Drive below 1.24V to disable the chip. Drive above 1.38V to activate chip and restart the soft-start sequence. Do not fl oat this pin. RT (Pin 6): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency to a fi xed free running level. Do not fl oat this pin. SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 275k resistor to about 2.2V. SYNC (Pin 8): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. Exposed Pad (Pin 9): Ground. Must be soldered directly to local ground plane. SHDN VOLTAGE (V) SHDN PIN CURRENT (μA) 0.5 1 –50°C 1.5 2

3580 G10

100°C 20°C SHDN VOLTAGE (V) SHDN PIN CURRENT (μA) 200 250 –50°C 20°C 100°C 300 15 25

3580 G11

TEMPERATURE (°C) –50

1.20 SHDN VOLTAGE (V)

1.22 1.26 1.28 1.30 1.40 1.34 0 50

3580 G12

1.24 1.36 1.38 1.32 100 SHDN RISING SHDN FALLING

3 1.215V REFERENCE ADJUSTABLE OSCILLATOR FREQUENCY FOLDBACK RAMP GENERATOR COMPARATOR DISCHARGE DETECT SS VC 275k SR2 R S 14.6k 14.6k Q SR1 A4A1 SYNC RT SHDN FB 1.3V VC SW 0.01Ω GND RT RFB DRIVER ILIMIT VIN VOUT CSS CC CIN RC VIN SOFT- START SYNC BLOCK UVLO R S Q 3580 BD

into the positive terminal of the PWM comparator A3. of A3, the SR latch is reset, turning off the power switch. noninverting amplifi cation from FB to VC. when the circuit is in shutdown. on-time of the LT3580 switch. Figure 1. SEPIC Topology Allows for the Input to Span can be used. Follow noted phasing if coupled. Figure 2. Dual Inductor Inverting Topology Results in can be used. Follow noted phasing if coupled.

3580 F01

3580 F02

Several functions are provided to enable a very clean start-up for the LT3580.

• First, the SHDN pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. An external resistor (or resistor divider) can be connected from the input power supply to the SHDN pin to provide a user-programmable undervoltage lockout function.
• Second, the soft-start circuitry provides for a gradual ramp-up of the switch current. When the part is brought out of shutdown, the external SS capacitor is fi rst d i s c h a r g e d ( p r o v i d i n g p r o t e c t i o n a g a i n s t SHDN pin glitches and slow ramping), then an integrated 275k resistor pulls the SS pin up to ~2.2V. By connecting an external capacitor to the SS pin, the voltage ramp rate on the pin can be set. Typical values for the soft-start capacitor range from 100nF to 1μF.
• Finally, the frequency foldback circuit reduces the switch- ing frequency when the FB pin is in a nominal range of 350mV to 900mV. This feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. Current Limit and Thermal Shutdown Operation The LT3580 has a current limit circuit not shown in the Block Diagram. The switch current is consistently moni- tored and not allowed to exceed the maximum switch current at a given duty cycle (see the Electrical Charac- teristics table). If the switch current reaches this value, the SR latch (SR1) is reset regardless of the state of the comparator (A1/A2). Also not shown in the Block Diagram is the thermal shutdown circuit. If the temperature of the part exceeds approximately 165°C, the SR2 latch is set regardless of the state of the comparator (A1/A2). A full soft-start cycle will then be initiated. The current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the LT3580. OPERATION

The output voltage is set by connecting a resistor (R FB) from V OUT t o t h e F B p i n . RFB i s d e t e r m i n e d f r o m t h e following equation: RFB = |VOUT VFB | 83.3μA where VFB is 1.215V (typical) for non-inverting topologies (i.e., boost and SEPIC regulators) and 5mV (typical) for inverting topologies (see the Electrical Characteristics). Power Switch Duty Cycle In order to maintain loop stability and deliver adequate current to the load, the power NPN (Q1 in the Block Dia- gram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by: DCMAX = (TP Min Off Time) TP

• 100% where TP is the clock period and Min Off Time (found in the Electrical Characteristics) is typically 60ns. The application should be designed so that the operating duty cycle does not exceed DCMAX. Duty cycle equations for several common topologies are given below, where VD is the diode forward voltage drop and VCESAT is typically 300mV at 1.5A. For the boost topology: DC VOUT VIN + VD VOUT + VD VCESAT For the SEPIC or dual inductor inverting topology (see Figures 1 and 2): DC VD+|VOUT | VIN + |VOUT | + VD VCESAT The LT3580 can be used in confi gurations where the duty cycle is higher than DC MAX, but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. APPLICATIONS INFORMATION Inductor Selection General Guidelines: The high frequency operation of the LT3580 allows for the use of small surface mount inductors. For high effi ciency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. To improve effi ciency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper wire resistance) to reduce I 2R losses, and must be able to handle the peak inductor current without saturat- ing. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology, where each inductor only carries a frac- tion of the total switch current. Molded chokes or chip inductors usually do not have enough core area to sup- p o rt p ea k i n d u ct o r c u r r e nts i n t h e 2A t o 3 A ra n g e . T o minimize radiated noise, use a toroidal or shielded induc- tor. Note that the inductance of shielded types will drop more as current increases, and will saturate more easily. See Table 1 for a list of inductor manufacturers. Table 1.Inductor Manufacturers Coilcraft DO3316P, MSS7341 and LPS4018 Series www.coilcraft.com Coiltronics DR, LD and CD Series www.coiltronics.com Murata LQH55D and LQH66S Series www.murata.com Sumida CDRH5D18B/HP, CDR6D23MN, CDRH6D26/HP, CDRH6D28, CDR7D28MN and CDRH105R Series www.sumida.com TDK RLF7030 and VLCF4020 Series www.tdk.com Würth WE-PD and WE-PD2 Series www.we-online.com Minimum Inductance: Although there can be a tradeoff with effi ciency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation. Adequate Load Current : Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to a load (I OUT). In order to provide adequate load current, L should be at least: L > DC • VIN 2(f) I LIM |VOUT |• I OUT VIN •

for boost, coupled inductor SEPIC and coupled inductor inverting topologies, or: L1 L2 > DC • VIN 2(f) I LIM VOUT •I OUT VIN • IOUT for the uncoupled inductor SEPIC and uncoupled inductor inverting topologies. where: DC = switch duty cycle (see previous section) I LIM = switch current limit, typically about 2.4A at 50% duty cycle (see the Typical Performance Characteristics section). η = power conversion effi ciency (typically 88% for boost and 75% for dual inductor topologies at high currents). f = switching frequency N e g a t i v e v a l u e s o f L MIN1 indicate that the output load current IOUT exceeds the switch current limit capability of the LT3580. Avoiding Subharmonic Oscillations: The LT3580’s internal slope compensation circuit will prevent subharmonic oscil- lations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with dut y cycles greater than 50%, the inductance must be at least: L > VIN •2 • D C – 1() (1D C )•(f)•0.8 for boost, coupled inductor SEPIC, and coupled inductor inverting topologies, or: L1 L2 > VIN •2 • D C – 1() (1D C )•(f)•0.8 for the uncoupled inductor SEPIC and uncoupled inductor inverting topologies. Maximum Inductance: Excessive inductance can reduce current ripple to levels that are diffi cult for the current com- parator (A3 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = VIN –VCESAT IMINRIPPLE

• DC f where LMAX is L1||L2 for dual inductor topologies and a good choice for IMIN-RIPPLE is 300mA. Current Rating: Finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in effi ciency loss. In steady state, the peak input inductor current (continuous conduction mode only) is given by: IL1PEAK = VOUT •IOUT VIN • + VIN •D C 2•L 1 •f for the boost, uncoupled inductor SEPIC and uncoupled inductor inverting topologies, or: IL1PEAK |VOUT •IOUT | VIN • •DC + VIN •D C 2•L 1 •f for the coupled inductor SEPIC and coupled inductor inverting topology. For dual inductor topologies, the peak output inductor current is given by: IL2PEAK =IOUT + VOUT •1 – D C() 2•L 2• f for the uncoupled inductor topologies, or IL2PEAK IOUT 1–DC + VOUT •1 – D C() 2•L 2• f for the coupled inductor topologies Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wider voltage

contribution of the various elements in the loop is critical. proportional to the VC voltage. able with proper external component selection. Figure 4. Boost Converter Equivalent Model

3580 F04

Figure 5. Note that R2 is 14.6k ||14.6k = 7.3k which is the Table 3. Bode Plot Parameters LT3580. The Microsemi UPS120 is a very good choice. handle an average forward current of 1A. the switching operation of the LT3580 will stop. Figure 5. Bode Plot for Example Boost Converter

3580 F05

the free-running oscillator. be less than 25% below fOSC . any noise, therefore switching above 600kHz is desired. inductor and fi lter capacitors go down in value and size. proportionally with frequency. as possible, which results in large peak currents. external capacitor (typically 100nF to 1μF) to the SS pin. fi nal value while limiting the start-up current. the soft-start occurs after every reactivation of the chip. resulting in extremely low quiescent current. or below the shutdown threshold. long as the SHDN voltage is limited to less than 32V. Figure 6. Chip States vs SHDN Voltage

3580 F06

typical thresholds of 1.32V (rising) and 1.29V (falling). Figure 7. Confi gurable UVLO start capacitor will begin charging. and into a copper plane with as much area as possible. turned off and the soft-start capacitor will be discharged. has dropped by ~5°C (nominal).

3580 F07

tion, so they should not be used for calculating effi ciency in discontinuous mode or at light load currents. Average Switch Current : ISW = VOUT •IOUT VIN • Switch I2R Loss: P SW =(DC)(ISW)2(RSW) Base Drive Loss (AC): PBAC = 13n(ISW)(VOUT)(f) Base Drive Loss (DC): PBDC = (VIN)(ISW)(DC) Input Power Loss: P INP = 7mA(VIN) where: RSW = switch resistance (typically 200m Ω at 1.5A) DC = duty cycle (see the Power Switch Duty Cycle section for formulas) η = power conversion effi ciency (typically 88% at high currents) Example: boost confi guration, VIN = 5V, VOUT = 12V, IOUT = 0.5A, f = 1.25MHz, VD = 0.5V: I SW = 1.36A DC = 61.5% P SW = 228mW P BAC = 270mW P BDC = 84mW P INP = 35mW Total LT3580 power dissipation (P TOT) = 617mW Thermal resistance for the LT3580 is infl uenced by the pres- ence of internal, topside or backside planes. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: T J = TA + θJA • PTOT where TJ = junction temperature, TA = ambient tempera- ture, θJA = 43°C/W for the 3mm × 3mm DFN package and 35°C/W to 40°C/W for the MSOP Exposed Pad package. P TOT is calculated above. VIN Ramp Rate While initially powering a switching converter application, the VIN ramp rate should be limited. High VIN ramp rates can cause excessive inrush currents in the passive components of the converter. This can lead to current and/or voltage overstress and may damage the passive components or the chip. Ramp rates less than 500mV/μs, depending on component parameters, will generally prevent these issues. Also, be careful to avoid hotplugging. Hotplugging occurs when an active voltage supply is “instantly” connected or switched to the input of the converter. Hotplugging results in very fast input ramp rates and is not recommended. Finally, for more information, refer to Linear application note AN88, which discusses voltage overstress that can occur when an inductive source impedance is hotplugged to an input pin bypassed by ceramic capacitors. Layout Hints As with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. One will not get advertised performance with a careless layout. For maximum effi - ciency, switch rise and fall times are typically in the 5ns to 10ns range. To prevent noise, both radiated and conducted, the high speed switching current path, shown in Figure 8, must be kept as short as possible. This is implemented in the suggested layout of a boost confi guration in Figure 9. Shortening this path will also reduce the parasitic trace inductance. At switch-off, this parasitic inductance pro- duces a fl yback spike across the LT3580 switch. When operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the LT3580 that may exceed its absolute maximum rating. A ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. The VC and FB components should be kept as far away as practical from the switch node. The ground for these co m p o n e nts s h o u l d be se pa rat ed f ro m th e s witc h c u r - rent path. Failure to do so can result in poor stability or subharmonic oscillation.

into the system ground plane at the C3 ground terminal. Figure 8. High Speed “Chopped” Switching Path for Boost Topology for the boost and SEPIC confi gurations, respectively. tor, C1, should be placed close to the LT3580, as shown.

3580 F08

Figure 9. Suggested Component Placement for Boost Topology ground planes will improve thermal performance. Figure 10. Suggested Component Placement for SEPIC Topology ground planes will improve thermal performance. Figure 11. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale). for adequate thermal performance. Multiple vias to additional ground planes will improve thermal performance.

3580 F10VOUT

3580 F11VOUT

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Figure 12. Switch-On Phase of an Inverting Converter . L1 and L2 Have Positive dI/dt. Figure 13. Switch-Off Phase of an Inverting Converter . L1 and L2 Currents Have Negative dI/dt. Figure 14. 1.2MHz, 5V to 12V Boost Converter

3580 F12

3580 F13

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750kHz, 5V to 40V , 150mA Boost Converter Wide Input Range SEPIC Converter with 5V Output Switches at 2.5MHz T ransient Response with 400mA to 500mA Output Load Step 2.2μF VOUT 40V 150mA 47μH D1 464k VIN VIN SW

3580 TA02

4.7nF0.1μF 47pFC1 2.2μF C1, C2: 2.2μF , 25V , X5R, 1206 D1: MICROSEMI UPS140 L1: SUMIDA CDRH105R-470 10μF V OUT 5V, 600mA (VIN = 5V OR HIGHER) 500mA (V IN = 4V) 400mA (V IN = 3V) 300mA (V IN = 2.6V) 4.7μH 1μF 4.7μH 46.4k VIN 2.6V TO 12V OPERATING 12V TO 32V TRANSIENT VIN SW

3580 TA03a

35.7k 10k SHDN GND FB VC SYNC SS RT 1nF 22pF0.1μFC1 2.2μF C1: 2.2μF , 35V , X5R, 1206 C2: 10μF , 10V , X5R, 1206 C3: 1μF , 50V , X5R, 0805 D1: MICROSEMI UPS140 L1, L2: TDK VLCF4020T-4R7N1R2 VOUT 100mV/DIV AC COUPLED IL1 +IL2 0.5A/DIV 100μs/DIVVIN = 12V 3580 TA03b

VFD (Vacuum Flourescent Display) Power Supply Switches at 2MHz to Avoid AM Band Danger High Voltage! Operation by High Voltage T rained Personnel Only 1μF 1μF 1μF 10μH 383k VIN 9V TO 16V 3.3V VIN SW VOUT2 95V 80mA VOUT1 64V 40mA

3580 TA04

10Ω 10Ω 45.3k 10k SHDN GND FB VC SYNC SS RT 1μF 1μF 2.2nF0.1μF 47pF 4.7μF 4.7μF C1, C2: 4.7μF , 25V , X5R, 1206 C3-C7: 1μF , 50V , X5R, 0805 D1-D4: ON SEMICONDUCTOR MBR0540 D5: MICROSEMI UPS140 L1: SUMIDA CDR6D28MNNP-100 R1, R2: 0.5W

High Voltage Positive Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm T ransformer and Switches at 200kHz Danger High Voltage! Operation by High Voltage T rained Personnel Only Start-Up Waveforms Switching Waveforms 68nF FOR ANY VOUT BETWEEN 50V TO 350V, CHOOSE RFB ACCORDING TO FOR 5V INPUT, KEEP MAXIMUM OUTPUT POWER AT 1.58W FOR 3.3V INPUT, KEEP MAXIMUM OUTPUT POWER AT 0.88W *MAY REQUIRE MUL TIPLE SERIES RESISTORS TO COMPL Y WITH MAXIMUM VOL TAGE RATINGS V OUT 350V 4.5mA (VIN = 5V) 2.5mA (VIN = 3.3V) 1:10.4 RFB 4.22M* VIN 3.3V TO 5V VIN SW

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7, 8 5, 6 FB VC SYNC SS RT 10nF 100pF0.47μFC1 2.2μF C1: 2.2μF , 25V , X5R, 1206 C2: TDK C3225X7R2J683M D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR0540 T1: TDK LDT565630T-041 VOUT – 1.215 83.3μARFB = 4.7μH IPRIMARY 1A/DIV VOUT 50V/DIV 2ms/DIV5V INPUT NO LOAD

3580 TA05b

2μs/DIV5V INPUT 4.5mA LOAD

3580 TA05c

High Voltage Negative Power Supply Uses Tiny 5.8mm × 5.8mm × 3mm T ransformer and Switches at 200kHz Danger High Voltage! Operation by High Voltage T rained Personnel Only 68nF FOR ANY VOUT BETWEEN –50V TO –350V , CHOOSE RFB ACCORDING TO FOR 5V INPUT , KEEP MAXIMUM OUTPUT POWER AT 1.58W FOR 3.3V INPUT , KEEP MAXIMUM OUTPUT POWER AT 0.88W *MAY REQUIRE MUL TIPLE SERIES RESISTORS TO COMPL Y WITH MAXIMUM VOL TAGE RATINGS V OUT –350V 4.5mA (VIN = 5V) 2.5mA (VIN = 3.3V) 1:10.4 RFB 4.22M* VIN 3.3V TO 5V VIN SW

3580 TA06

7, 8 5, 6 FB VC SYNC SS RT 10nF 100pF0.47μFC1 2.2μF C1: 2.2μF , 25V , X5R, 1206 C2: TDK C3225X7R2J683M D1: VISHAY GSD2004S DUAL DIODE CONNECTED IN SERIES D2: ON SEMICONDUCTOR MBR0540 T1: TDK LDT565630T-041 VOUT 83.3μARFB = 4.7μH

5V to 12V Boost Converter Switches at 2.5MHz and Uses a Tiny 4mm × 4mm × 1.7mm Inductor Effi ciency and Power Loss vs Load Current T ransient Response with 400mA to 500mA to 400mA Output Load Step Start-Up Waveforms 4.7μF VOUT 12V 500mA 3.3μH D1 130k VIN VIN SW

3580 TA07a

35.7k 10k SHDN GND FB VC SYNC SS RT 2.2nF0.1μF 47pFC1 4.7μF C1, C2: 4.7μF , 25V , X5R, 1206 D1: MICROSEMI UPS120 L1: COILCRAFT LPS4018-332ML LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 400

3580 TA07b

0.5A/DIV VOUT 0.5V/DIV AC COUPLED 100μs/DIV 3580 TA07c IL 1A/DIV VOUT 5V/DIV VSHDN 1V/DIV 2ms/DIV500mA LOAD 3580 TA07d

–5V Output Inverting Converter Switches at 2.5MHz and Accepts Inputs Between 3.3V to 12V Effi ciency and Power Loss vs Load Current 10μF VOUT –5V 800mA (VIN = 12V) 620mA (VIN = 5V) 450mA (VIN = 3.3V) 4.7μH 1μF 60.2k VIN 3.3V TO 12V VIN SW

3580 TA08a

35.7k 10k SHDN GND FB VC SYNC SS RT 2.2nF 100pF 0.1μFC1 2.2μF C1: 2.2μF , 25V , X5R, 1206 C2: 10μF , 25V , X5R, 1206 C3: 1μF , 50V , X5R, 0805 D1: CENTRAL SEMI CMMSH1-40 L1, L2: COILCRAFT LSP4018-472ML 4.7μH LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 400

3580 TA08b

VIN = 5V

8-Lead Plastic DFN (3mm × 3mm) (Reference L TC DWG # 05-08-1698) 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN 1203 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05 0.50 BSC 0.675 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05

0.50 BSC

Information furnished by Linear Technology Corpor ation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . PACKAGE DESCRIPTION 8-Lead Plastic MSOP (Reference L TC DWG # 05-08-1662) MSOP (MS8E) 0307 REV D 0.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 12 3 4 4.90 ± 0.152 (.193 ± .006) BOTTOM VIEW OF EXPOSED PAD OPTION 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF 1.83 ± 0.102 (.072 ± .004) 2.06 ± 0.102 (.081 ± .004) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 2.083 ± 0.102 (.082 ± .004) 2.794 ± 0.102 (.110 ± .004) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 0.1016 ± 0.0508 (.004 ± .002)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0508 REV C • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT1310 2A (I SW), 40V, 1.2MHz High Effi ciency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT TM Package LT1613 550mA (I SW), 1.4MHz High Effi ciency Step-Up DC/DC Converter VIN: 0.9V to 10V, VOUT(MAX) = 34V, IQ = 3mA, ISD < 1μA, ThinSOT Package LT1618 1.5A (I SW), 1.25MHz High Effi ciency Step-Up DC/DC Converter V IN: 1.6V to 18V, VOUT(MAX) = 35V, IQ = 1.8mA, ISD < 1μA, LT1930/LT1930A 1A (I SW), 1.2MHz/2.2MHz High Effi ciency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, I SD < 1μA, ThinSOT Package LT1931/LT1931A 1A (I SW), 1.2MHz/2.2MHz High Effi ciency Inverting DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, I SD < 1μA, ThinSOT Package LT1935 2A (I SW), 40V, 1.2MHz High Effi ciency Step-Up DC/DC Converter VIN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1μA, ThinSOT Package LT1944/LT1944-1 (Dual) Dual Output 350mA (I SW), Constant Off-Time, High Effi ciency Step-Up DC/DC Converter VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20μA, ISD < 1μA, LT1945 (Dual) Dual Output Pos/Neg 350mA (I SW), Constant Off-Time, High Effi ciency Step-Up DC/DC Converter VIN: 1.2V to 15V, VOUT(MAX) = ±34V, IQ = 20μA, ISD < 1μA, LT1946/LT1946A 1.5A (I SW), 1.2MHz/2.7MHz High Effi ciency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1μA, LT1961 1.5A (I SW), 1.25MHz High Effi ciency Step-Up DC/DC Converter V IN: 3V to 25V, VOUT(MAX) = 35V, IQ = 0.9mA, ISD < 6μA, LT3436 3A (I SW), 800kHz, 34V Step-Up DC/DC Converter V IN: 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6μA, LT3467 1.1A (I SW), 1.3MHz High Effi ciency Step-Up DC/DC Converter V IN: 2.6V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD < 1μA, ThinSOT, 2mm × 3mm DFN Packages LT3477 42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver V IN: 2.5V to 25V, VOUT(MAX) = 40V, Analog/PWM, I SD < 1μA, QFN, TSSOP20E Packages LT3479 3A Full-Featured DC/DC Converter with Soft-Start and Inrush Current Protection VIN: 2.5V to 24V, VOUT(MAX) = 40V, Analog/PWM, I SD < 1μA, DFN, TSSOP Packages 2MHz Inverting Converter Generates –12V from a 5V to 12V Input Effi ciency and Power Loss vs Load Current 10μF VOUT –12V 500mA (VIN = 12V) 350mA (VIN = 5V) 10μH 1μF 147k VIN 5V TO 12V VIN SW

3580 TA09a

45.3k 10k SHDN GND FB VC SYNC SS RT 2.2nF 47pF 0.1μFC1 2.2μF C1: 2.2μF , 25V , X5R, 1206 C2: 10μF , 25V , X5R, 1206 C3: 1μF , 50V , X5R, 0805 D1: CENTRAL SEMI CMMSH1-40 L1: SUMIDA CDRH6D28NP-100NC L2: SUMIDA CDRH3D28NP-220NC 22μH LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mw) 400

3580 TA09b

VIN = 5V