LTC4040

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2.5A Battery Backup Power Manager

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Selected specification: Linear Technology

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LTC4040_15 LINER

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 26

Technical content

For more information www.linear .com/L TC4040 Typical applicaTion FeaTures DescripTion 2.5A Battery Backup Power Manager The LT C®4040 is a complete 3.5V to 5.5V supply rail battery backup system. It contains a high current step-up DC/DC regulator to back up the supply from a single-cell Li-Ion or LiFePO 4 battery. When external power is available, the step-up regulator operates in reverse as a step-down battery charger. The LTC4040’s adjustable input current limit function reduces charge current to protect the main supply from overload while an external disconnect switch isolates the external supply during backup. When the input supply drops below the adjustable PFI threshold, the 2.5A boost regulator delivers power from the battery to the system output. An optional input overvoltage protection (OVP) circuit protects the LTC4040 from high voltage damage at the V IN pin. One logic input selects either the Li-Ion or the LiFePO4 battery option, and two other logic inputs program the battery charge voltage to one of four levels suitable for backup applications. The LTC4040 is available in a low profile (0.75mm) 24-Lead 4mm × 5mm QFN package. 4.5V Backup Application with 4.22V PFI Threshold (Charge Current Setting: 1A, Input Current Limit Setting: 2A) Normal to Backup Mode T ransition Waveform

applicaTions

n Step-Up Backup Supply and Step-Down Battery Charger n 6.5A Switches for 2.5A Backup from 3.2V Battery n Input Current Limit Prioritizes Load Over Charge Current n Input Disconnect Switch Isolates Input During Backup n Automatic Seamless Switch-Over to Backup Mode n Input Power Loss Indicator n System Power Loss Indicator n Pin Selectable Battery: Li-Ion (3.95V/4.0V/4.05V/4.1V) or LiFePO n Optional OVP Circuitry Protects Device to >60V n Constant Frequency Operation n Low Profile (0.75mm) 24-Lead 4mm × 5mm QFN Package n Fleet and Asset T racking n Automotive GPS Data Loggers n Automotive Telematics Systems n Toll Collection Systems n Security Systems n USB Powered Devices L, LT, LT C, LT M, Linear Technology, the Linear logo and Burst Mode are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6522118, 6570372, 6700364, 8139329. 324k 2.2µH VSYS PROGBSTOFFCHGOFF F2 F1 F0 IGATE L TC4040 VIN CLN 1500k 4.5V12m/uni03A9 10µF 100µF2.2µF SYSTEM LOAD BSTFB RSTFB 4.5V INPUT SUPPL Y SW BAT NTC NTC VSYS LiFePO4 3.6V

4040 TA01a

60.4k V SYS V IN I BAT V BAT = 3.3V R PROG = 2k I SYS = 1A C SYS = 100µF TIME (ms) –0.4 0.4 0.8 1.2 VOL TAGE (V) CURRENT (A) Waveform (LiFePO App.) Normal to Backup Mode T ransition

4040 TA01b

For more information www.linear .com/L TC4040 pin conFiguraTionabsoluTe MaxiMuM raTings VIN (Steady State), BAT, CLN, VSYS, BSTFB, NTC, OVSNS, 0.3V to 6V F0, F1, F2, BSTOFF, RSTFB, 0.3V to Max (VIN, VBAT, VSYS) + 0.3V Operating Junction Temperature Range 40 to 125°C 65 to 125°C (Notes 1, 2) 8 9 TOP VIEW GND UFD PACKAGE 24-LEAD (4mm × 5mm) PLASTIC QFN 10 11 12 24 23 22 21 20 1VSYS PROG CLPROG CHGOFF BSTOFF VIN CLN PFI BSTFB NTC OVSNS IGATE VSYS BAT SW SW PF0 CHRG FAULT RSTFB RST TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4040EUFD#PBF LTC4040EUFD#TRPBF 4040 24-Lead (4mm × 5mm × 0.75mm) Plastic QFN –40°C to 125°C LTC4040IUFD#PBF LTC4040IUFD#TRPBF 4040 24-Lead (4mm × 5mm × 0.75mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult L TC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

For more information www.linear .com/L TC4040 elecTrical characTerisTics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 5V, VBAT = 3.6V, RPROG = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range l 3.5 5.5 V VBAT Battery Voltage Range (Backup Boost Input) 2.7 5 V IINQ VIN Quiescent Current Normal Mode (VPFI = 2V), Battery Charger Timed Out Shutdown (BSTOFF = CHGOFF=1) 570 3.5 µA µA IBATQ BAT Quiescent Current Normal Mode (VPFI = 2V), Battery Charger Timed Out Backup Mode (VIN = VPFI = 0V), No System Load Shutdown (BSTOFF = CHGOFF = 1) l 1.5 µA µA µA Battery Charger V CHG BAT Regulated Output Voltage for LiFePO4 Option (F2 = 0) F2 = 0, F1 = 0, F0 = 0 F2 = 0, F1 = 0, F0 = 1 F2 = 0, F1 = 1, F0 = 0 F2 = 0, F1 = 1, F0 = 1 l l l l 3.42 3.47 3.52 3.57 3.45 3.50 3.55 3.60 3.48 3.53 3.58 3.63 V V V V BAT Regulated Output V oltage for Li-Ion Option (F2 = 1) F2 = 1, F1 = 0, F0 = 0 F2 = 1, F1 = 0, F0 = 1 F2 = 1, F1 = 1, F0 = 0 F2 = 1, F1 = 1, F0 = 1 l l l l 3.92 3.97 4.02 4.07 3.95 4.00 4.05 4.10 3.98 4.03 4.08 4.13 V V V V I CHG Regulated Battery Charge Current RPROG = 2k 950 1000 1050 mA VSYS-to-VBAT Differential Undervoltage Lockout Threshold (Falling) 40 50 60 mV VSYS-to-BAT Differential Undervoltage Lockout Threshold (Rising) 125 145 165 mV VPROG PROG Pin Servo Voltage 800 mV hPROG Ratio of Battery Current to PROG Pin Current 2500 mA/ mA ITRKL T rickle Charge Current VBAT = 2.5V, RPROG = 2k 125 mA PROG Pin Servo Voltage at T rickle Charge V BAT = 2.5V, RPROG = 2k 100 mV Input Current Limit Threshold Voltage V IN – VCLN l 23.5 25 26.5 mV ACLPROG Input Current Limit Amplifier Gain Ratio of CLPROG Voltage to (VIN – VCLN) 32 V/V CLN Input Bias Current VCLN = VIN 300 nA VRECHG Recharge Battery Threshold Voltage Threshold Voltage Relative to VCHG if F2 = 0 and F1 = 1 Threshold Voltage Relative to VCHG All Other Cases 94.2 96.7 97.5 95.8 98.3 t TERMINATE Safety Timer Termination Period Timer Starts When VBAT = VCHG F2 = 1 (Li-Ion) F2 = 0 (LiFePO 3.7 1.85 4.25 2.13 2.5 Hours Hours V LOWBAT Low Battery Threshold Voltage for T rickle ChargeVBAT Rising 2.75 2.85 2.95 V VLOWBAT Low Battery Hysteresis 150 mV tBADBAT Bad-Battery Termination Time VBAT < (VLOWBAT − ΔVLOWBAT) 0.47 0.54 0.64 Hours VC/8 End-of-Charge Indication PROG Pin Average Voltage 90 100 110 mV fOSC(BUCK) Step-Down (Buck) Converter Switching Frequency Normal Mode (V PFI > 1.21V) 1.96 2.25 2.65 MHz RP(BUCK) High Side Switch On-Resistance Normal Mode (VPFI > 1.21V) 130 mΩ RN(BUCK) Low Side Switch On-Resistance Normal Mode (VPFI > 1.21V) 120 mΩ ILIM(BUCK) PMOS Switch Current Limit 3 4.3 A

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NTC VCOLD Cold Temperature Fault Threshold Voltage Rising Voltage Threshold Hysteresis 75.0 76.5 1.5 78 %V IN %VIN VHOT Hot Temperature Fault Threshold Voltage Falling Voltage Threshold Hysteresis 33.4 34.9 1.73 36.4 %VIN %VIN VDIS NTC Disable Threshold Voltage Falling Threshold Hysteresis 0.7 1.7 2.7 %VIN mV INTC NTC Leakage Current –20 20 nA Backup Mode Boost Switching Regulator VBSTFB BSTFB Reference Voltage l 0.78 0.8 0.82 V IBSTFB BSTFB Input Bias Current –20 20 nA VSYS Step-up (Boost) Converter Output Voltage Range 3.5 5 V fOSCBST Step-Up Converter Switching Frequency Backup Mode (V PFI < 1.17V) 0.98 1.125 1.33 MHz ILIMBST NMOS Switch Current Limit 5.5 6.5 7.5 A RPBST Boost High Side Switch On-Resistance 75 mΩ RNBST Boost Low Side Switch On-Resistance 70 mΩ VOVSD VSYS Overvoltage Shutdown Threshold V SYS Rising 5.3 5.5 5.7 V Overvoltage Shutdown Hysteresis 100 mV VUVLO BAT Pin Undervoltage Lockout VBAT Falling 2.45 2.6 V BAT Pin Undervoltage Lockout Hysteresis 150 mV DMAX Maximum Boost Duty Cycle 88 91 % NMOS Switch Leakage BSTOFF = 1, CHGOFF = 1 1 µA PMOS Switch Leakage BSTOFF = 1, CHGOFF = 1 1 µA Reset Comparator RSTFB Threshold (Falling) l 0.72 0.74 0.76 V RSTFB Hysteresis 20 mV RSTFB Pin Leakage Current VRSTFB = 0.9V –50 50 nA RST Delay (RSTFB Rising) 232 ms Power-Fail Comparator PFI Input Threshold (Falling Edge) Initiates Backup Mode l 1.17 1.19 1.21 V PFI Input Hysteresis 30 mV PFI Pin Leakage Current VPFI = 1.3V –100 100 nA PFI Delay to PFO PFI Falling 0.5 µs PFO Pin Leakage Current VPFO = 5V 10 µA PFO Pin Output Low Voltage IPFO = 5mA 65 mV Logic Input (CHGOFF, BSTOFF, F0, F1, F2) VIL Logic Low Input Voltage l 0.4 V VIH Logic High Input Voltage l 1.2 V IIL Logic Low Input Leakage –1 1 µA IIH Logic High Input Leakage –1 1 µA

For more information www.linear .com/L TC4040 The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 5V, VBAT = 3.6V, RPROG = 2k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Open-Drain Output (CHRG, RST, FAULT) Pin Leakage Current V = 5V 1 µA Pin Output Low Voltage I = 5mA 65 mV Overvoltage Protection VOV(CUTOFF) Overvoltage Protection Threshold Rising Threshold, ROVSNS = 6.2k 6.1 6.4 6.7 V VOVGT IGATE Output Voltage Active Input Voltage < VOV(CUTOFF) 1.88 • VOVSNS 12 V VOVGT(LOAD) IGATE Voltage Under Load 5V Through 6.2k Into OVSNS, IIGATE = 1µA 8 8.6 V IOVSNSQ OVSNS Quiescent Current VOVSNS = 5V 40 µA OVSNS Quiescent Current at Shutdown BSTOFF = H, CHGOFF = H 25 µA IGATE Time to Reach Regulation CIGATE = 2.2nF 3.5 ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The LTC4040E is tested under pulsed load conditions such that T J ≈ TA. The LTC4040E is guaranteed to meet performance specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process control. The LTC4040I is guaranteed over the full –40°C to 125°C operating junction temperature range. The junction temperature (T J in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD • θJA) where the package thermal impedance θJA = 43°C/W. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.

For more information www.linear .com/L TC4040 Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. R PROG = 2k V SYS = 5V F2 = 1, F1 = 0, F0 = 0 F2 = 1, F1 = 0, F0 = 1 F2 = 1, F1 = 1, F0 = 0 F2 = 1, F1 = 1, F0 = 1 V BAT (V) 2.7 3.3 3.6 3.9 4.2 200 400 600 800 1000 I BAT (mA) Different Charge Voltage Settings I BAT vs V BAT (Li–Ion) with

4040 G01

R PROG = 2k V SYS = 5V F2 = 0, F1 = 0, F0 = 0 F2 = 0, F1 = 0, F0 = 1 F2 = 0, F1 = 1, F0 = 0 F2 = 0, F1 = 1, F0 = 1 V BAT (V) 2.7 2.9 3.1 3.3 3.5 3.7 200 400 600 800 1000 I BAT (mA) Different Charge Voltage Settings I BAT vs V BAT (LiFePO ) with

4040 G02

VBAT (V) 2.8 3.0 3.2 3.4 3.6 3.8 4.0 100 EFFICIENCY (%) vs VBAT Step–Down Charger Efﬁciency

4040 G03

RPROG = 4k RPROG = 2k RPROG = 1.33k RPROG = 1k RPROG = 0.8k V SYS = 5V F2 = F1 = F0 = 1 R PROG = 0.8k R PROG = 1k R PROG = 1.33k R PROG = 2k R PROG = 4K V SYS = 5V F2, F1, F0 = 1 V BAT (V) 2.7 3.0 3.3 3.6 3.9 4.2 500 1000 1500 2000 2500 3000 I BAT (mA) Different PROG Resistor Values I BAT vs V BAT (Li–Ion) with

4040 G04

V SYS = 5V F2 = 0, F1 = F0 = 0 R PROG = 0.8k R PROG = 1k R PROG = 1.33k R PROG = 2k R PROG = 4k V BAT (V) 2.7 2.9 3.1 3.3 3.5 3.7 500 1000 1500 2000 2500 3000 I BAT (mA) Different PROG Resistor Values I BAT vs V BAT (LiFePO ) with

4040 G05

VSYS = 5V F2 = F1 = F0 = 1 TEMPERATURE (°C) –50 –30 –10 110 130 3.70 3.75 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 4.20 VBAT (V) vs Temperature Battery Charge Voltage (Li-Ion)

4040 G06

V BAT = 3.2V V IN = 5.5V V IN = 5.0V V IN = 3.6V TEMPERATURE (°C) –45 –10 130 1.80 1.90 2.00 2.10 2.20 2.30 FREQUENCY (MHz) Frequency vs Temperature Step–Down Charger Oscillator

4040 G07

130°C 90°C 60°C 25°C –10°C –45°C V SYS (V) 3.6 3.8 4.2 4.4 4.6 4.8 5.0 100 120 140 160 180 200 RESISTANCE (mΩ) vs V SYS over Temperature Step–Down Charger PMOS R ds(ON)

4040 G08

130°C 90°C 60°C 25°C –10°C –45°C V SYS (V) 3.6 3.8 4.2 4.4 4.6 4.8 5.0 100 120 140 160 180 200 RESISTANCE (m/uni03A9) vs V SYS over Temperature Step–Down Charger NMOS R DS(ON)

4040 G09

Step-Down Charger Efficiency vs VBAT IBAT vs VBAT (Li-Ion) with Different PROG Resistor Values IBAT vs VBAT (LiFePO4) with Different PROG Resistor Values Battery Charge Voltage (Li-Ion) vs Temperature Step-Down Charger Oscillator Frequency vs Temperature Step-Down Charger PMOS On-Resistance vs V SYS over Temperature Step-Down Charger NMOS On-Resistance vs V SYS over Temperature IBAT vs VBAT (Li-Ion) with Different Charge Voltage Settings IBAT vs VBAT (LiFePO4) with Different Charge Voltage Settings

For more information www.linear .com/L TC4040 Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. TIME (h) 3.00 3.20 3.40 3.60 3.80 4.00 4.20 200 400 600 800 1000 1200 BATTERY VOL TAGE (V) CHARGE CURRENT (mA) Li–Ion Battery Charging Proﬁle

4040 G10

V SYS = 5V R PROG = 2k F2 = F1 = F0 = 1 VBAT IBAT V SYS = 5V R PROG = 2k F2 = 0, F1 = F0 = 1 TIME (h) 0.5 1.5 2.5 3.5 4.5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 200 400 600 800 1000 1200 BATTERY VOL TAGE (V) CHARGE CURRENT (mA) LiFePO Battery Charging Proﬁle

4040 G11

SYSTEM LOAD CURRENT (mA) 500 1000 1500 2000 2500 500 1000 1500 2000 2500 CURRENT (mA) Input Current Limit Set by R S Charge Current Reduction Due to

4040 G12

V SYS = 5V R PROG = 2k R S = 12 m/uni03A9 I BAT V IN V SYS I BAT V BAT = 3.6V I SYS = 1A R PROG = 2k C SYS = 100µF TIME (µs) –500 –250 250 500 750 1000 VOL TAGE (V) CURRENT (A) T ransition Waveform (Li–Ion) Normal to Backup Mode

4040 G13

TIME (ms) –200 –100 100 200 300 400 500 600 700 VOL TAGE (V) CURRENT (A) T ransition Waveform Backup to Normal Mode

4040 G14

VBAT = 3.7V RPROG = 2k ISYS = 1A TIME (µs) 200 400 600 800 1000 1200 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 PROG VOL TAGE (V) CURRENT (A) to System Step Load PROG Voltage T ransient Response

4040 G15

V PROG I SYS V BAT = 3.7V R PROG = 2k R S = 12m/uni03A9 I BAT Li-Ion Battery Charging Profile LiFePO4 Battery Charging Profile Charge Current Reduction Due to Input Current Limit Set by RS Normal to Backup Mode T ransition Waveform (Li-Ion) Backup to Normal Mode T ransition Waveform PROG Voltage T ransient Response by System Step Load

For more information www.linear .com/L TC4040 VBAT = 3.2V VBAT = 3.7V VBAT = 4.1V LOAD CURRENT (mA) 100 100 EFFICIENCY (%) vs Load Current Backup Boost Efﬁciency

4040 G19

V SYS SET TO 5V 130°C 90°C 25°C –10°C 60°C –45°C V SYS (V) 3.5 3.8 4.1 4.4 4.7 5.0 100 110 RESISTANCE (m/uni03A9) vs V SYS over Temperature Backup Boost NMOS R DS(ON)

4040 G20

130°C 90°C 60°C 25°C –10°C –45°C V SYS (V) 3.5 3.8 4.1 4.4 4.7 5.0 100 110 RESISTANCE (m/uni03A9) vs V SYS over Temperature Backup Boost PMOS R DS(ON)

4040 G21

V BAT = 4.1V V BAT = 3.6V V BAT = 2.7V TEMPERATURE (°C) –45 –10 130 CURRENT (µA) I BATQ vs Temperature SLEEP Mode (Backup)

4040 G22

Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. V SYS = Set to 5V V BAT = 3.6V I SYS = 1mA TEMPERATURE (°C) –45 –10 130 4.50 4.60 4.70 4.80 4.90 5.00 5.10 V SYS (V) SYS ) vs Temperature Back–Up Boost Output Voltage

4040 G16

V SYS = 5V V BAT = 4.1V V BAT = 3.6V V BAT = 2.7V TEMPERATURE (°C) –45 –10 130 0.90 0.95 1.00 1.05 1.10 1.15 FREQUENCY (MHz) Frequency vs Temperature Backup Boost Oscillator

4040 G17

V BAT = 3.6V TEMPERATURE (°C) –45 –10 130 MAX DUTY CYCLE (%) Duty Cycle vs Temperature Backup Boost Maximum

4040 G18

Back-Up Boost Output Voltage (VSYS) vs Temperature Backup Boost Oscillator Frequency vs Temperature Backup Boost Maximum Duty Cycle vs Temperature Backup Boost Efficiency vs Load Current Backup Boost NMOS On-Resistance vs V SYS over Temperature Backup Boost PMOS On-Resistance vs V SYS over Temperature SLEEP Mode (Backup) I BATQ vs Temperature

For more information www.linear .com/L TC4040 Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. V BAT = 3.6V C SYS = 100µF L = 2.2µH V SYS I SYS TIME (ms) –0.4 0.0 0.4 0.8 1.2 1.6 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 VOL TAGE (V) LOAD CURRENT (A) Response to Load Step Backup Boost T ransient

4040 G23

V BAT = 3.6V C SYS = 100µF L = 2.2µH I SYS V SYS TIME (ms) –0.4 0.0 0.4 0.8 1.2 1.6 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 VOL TAGE (V) LOAD CURRENT (A) Mode T ransition Waveform Burst Mode to Constant Frequency

4040 G24

TEMPERATURE (°C) –45 –10 130 6.20 6.25 6.30 6.35 6.40 6.45 6.50 VOL TAGE (V) (Through 6.2k) vs Temperature OVP Module Shutdown Voltage

4040 G25

TEMPERATURE (°C) –45 –10 130 CURRENT (µA) vs Temperature OVSNS Pin Quiescent Current

4040 G26

INPUT = 5V Backup Boost T ransient Response to Load Step Burst Mode to Constant Frequency Mode T ransition Waveform OVP Module Shutdown Voltage (Through 6.2k) vs Temperature OVSNS Pin Quiescent Current vs Temperature

For more information www.linear .com/L TC4040 pin FuncTions VSYS (Pins 1, 24): System Voltage Output Pin. This pin is used to provide power to an external load from either the primary input supply or the backup battery if the primary input supply is not available. In addition to supplying power to the load, this pin provides power to charge the battery when input power is available. V SYS should be bypassed with a low ESR ceramic capacitor of at least 100µF to GND. PROG (Pin 2): Charge Current Program Pin. An external resistor from the PROG pin to ground programs the full- scale charge current. At full scale, the PROG pin servos to 0.8V. The ratio of BAT pin current to PROG pin current is internally set to 2500. CLPROG (Pin 3): V SYS Current Monitoring Pin. The ratio between the CLPROG pin voltage and the differential voltage between VIN and CLN is internally set to 32. Charge current is reduced when the CLPROG pin voltage reaches 0.8V. CHGOFF (Pin 4): Disable Pin for the Battery Charger. Tie this pin to GND to enable the charger or to a voltage above 1.2V to disable it. Do not leave this pin unconnected. BSTOFF (Pin 5): Disable Pin for the Backup Boost Con - verter. Tie this pin to GND to enable the boost backup or to a voltage above 1.2V to disable backup. Do not leave this pin unconnected. VIN (Pin 6): Input Pin. Power can be applied directly to this pin if the optional overvoltage protection (OVP) fea- ture is not used. For applications where the OVP feature is required, connect an external N-channel FET between the power supply output VPWR and this pin. CLN (Pin 7): Negative terminal pin for an external cur - rent limit sense resistor connected between VIN and this pin. This resistor is used to monitor the current from VIN to VSYS. The LT4040 reduces charge current in order to maintain 25mV across this sense resistor. However, it does not limit the system current if the drop exceeds 25mV. CHRG (Pin 8): Open-Drain Charge Status Output; typi - cally pulled up through a resistor to a reference voltage. During a battery charging cycle, CHRG is pulled low until the charge current drops below C/8 when the CHRG pin becomes high impedance. FAULT (Pin 9): Open-Drain Fault Status Output; typically pulled up through a resistor to a reference voltage. This pin indicates charge cycle fault conditions during a battery charging cycle. A temperature fault or a bad-battery fault causes this pin to be pulled low. If no fault conditions exist, the FAULT pin remains high impedance. RSTFB (Pin 10): Reset Comparator Input. High Imped - ance input to an accurate comparator with a 0.74V falling threshold and 20mV hysteresis. This pin controls the state of the RST output pin. An external resistor divider is used between V SYS, RSTFB and GND. It can be the same resistor divider as the BSTFB divider to monitor the system output voltage V SYS. See the Applications Information section. RST (Pin 11): Open-Drain Status Output of the Reset Comparator. This pin is pulled to ground by an internal N-channel MOSFET whenever the RSTFB pin falls below 0.74V. Once the RSTFB pin voltage recovers, the pin be- comes high impedance after a 232ms delay. (Pin 12): Logic Input to Select Battery Chemistry. A logic high on this pin selects Li-Ion and a logic low selects LiFePO4. Do not leave this pin unconnected. F1, F0 (Pins 13, 14): Logic inputs to select one of the four possible charge voltage settings for each battery chemistry. Do not leave these pins unconnected. F0 F1 F2 = 1: Li-Ion (V) F2 = 0: LiFePO 4 (V) 0 0 3.95 3.45 1 0 4.00 3.50 0 1 4.05 3.55 1 1 4.10 3.60 IGATE (Pin 15): Gate Pin for the External N-Channel FETs. This pin is driven by an internal charge pump to develop sufficient overdrive to fully enhance the pass transistors. The first pass transistor is connected between the supply output V PWR and VIN and is part of the optional overvolt- age protection module. The second pass transistor, con- nected between V IN and VSYS, is mandatory and is used to disconnect the system from the input supply during backup mode.

For more information www.linear .com/L TC4040 pin FuncTions OVSNS (Pin 16): Overvoltage Protection Sense Input. If the overvoltage feature is used, the OVSNS pin should be connected through a 6.2k resistor to an input power con- nector and the drain of an N-channel MOS pass transistor. If not, this pin should be shorted to VIN. When voltage is detected on OVSNS, it draws a small amount of current to power a charge pump which then provides gate drive to IGATE to energize the external transistor. When the voltage on this pin exceeds typically 6V, IGATE is pulled to GND to disable the pass transistor and protect the LTC4040 from high voltage. NTC (Pin 17): Input to the Thermistor Monitoring Circuits. The NTC pin connects to a battery’s thermistor to deter - mine if the battery is too hot or too cold to charge. If the battery’ s temperature is out of range, charging is paused until it re-enters the valid range. A low drift bias resistor is required from V IN to NTC and a thermistor is required from NTC to ground. If the NTC function is not desired, the NTC pin should be grounded. BSTFB (Pin 18): Feedback Input for the Backup Boost Regulator. During steady-state backup operation, voltage on this pin servos to 0.8V. PFI (Pin 19): Power-Fail Input. High impedance input to an accurate comparator (power-fail) with a 1.19V falling threshold and 30mV hysteresis. PFI controls the state of the PFO output pin and sets the input voltage threshold below which the boost backup is initiated. This threshold voltage also represents the minimum voltage above which the step-down battery charger is enabled and the part al- lows power to flow from the input to the output through the external pass transistors. PFO (Pin 20): Open-Drain Power-Fail Status Output. This pin is pulled to ground by an internal N-channel MOSFET when the PFI input is below the falling threshold of the power-fail comparator. Once the PFI input rises above the rising threshold, this pin becomes high impedance. SW (Pins 21, 22): Power T ransmission Pin for the Buck Switching Charger and the Boost Switching Backup Converter. A 1µH to 2.2µH inductor should be connected from SW to BAT. BAT (Pin 23): Single Cell Li-Ion or LiFePO 4 Battery Pin. Depending on the availability of input power, the battery will either deliver power to V SYS via the boost converter or be charged from VSYS via the buck charger. BAT should be bypassed with a low ESR ceramic capacitor of at least 10µF to GND. GND (Exposed Pad Pin 25): The exposed pad must be soldered to the PCB to provide a low electrical and ther - mal impedance connection to the printed circuit board’s ground. A continuous ground plane on the second layer of a multilayer printed circuit board is strongly recommended.

For more information www.linear .com/L TC4040 block DiagraM CHARGE VOL TAGE SELECTOR BAT PROGCHGOFF RPROG RFB2 CBAT RFB1 325

4040 F01

0.8VBAD-BATTERY DETECTOR 6.4k NTC FAULT RBIAS VIN RNTC VIN PFI CLPROGGND + –A4 0.8V 0.8V BUCK/BOOST CHARGER CTRL BOOST CTRL BUCK CHARGER BOOST BACKUP + –A3 0.8V +–A2 PWM BSTFB RSTFB VSYS 1, 24 SYSTEM RST BSTOFF5 SW L1 21, 22 0.74V MN2 MN1 CLN IGATE RS VIN 232ms DELAY –+ – 2.85V BAT C/8 DETECTOR PROG 0.1V 1.19V AV = 32 CHARGER LOGIC NTC ENABLE OVERTEMP UNDERTEMP 0.1V CHRG8 OVSNS 6.2k INPUT PFO20RPF1 RPF2 CP1 OVERVOL TAGE PROTECTION Li-Ion/ LiFePO4 BATTERY VPWR POWER-FAIL COMPARATOR

For more information www.linear .com/L TC4040 operaTion The LTC4040 is a complete battery backup system manager for a 3.5V to 5.5V supply rail. The system has three prin- cipal circuit components: a full-featured step-down (buck) battery charger , a step-up (boost) backup converter with automatic burst feature to deliver power to the system load when external input power is lost and a power-fail com - parator to decide which one to activate. The LTC4040 has several other auxiliary components: an input current limit (CLPROG) amplifier, an optional input overvoltage protec- tion (OVP) circuit and a reset comparator. The LT C4040 has three modes of operation: normal, backup and shutdown. If the input supply is above an externally programmable PFI threshold voltage, the part is considered to be in normal mode in which power flows from input to output (V SYS) while the step-down switch- ing regulator charges the battery to one of eight charge voltage settings programmed by the F0, F1, and F2 digital inputs. Please refer to the Block Diagram. The total system load is monitored by the CLPROG amplifier via an external series resistor, R S, connected between the V IN and CLN pins. This amplifier can reduce the charge current from its programmed value (set by the PROG pin external resis - tor R PROG) if the external load demand increases beyond a programmable level set by R S. When the input supply falls below the PFI threshold, backup mode disconnects the switches (MN1 and MN2) to isolate the system (V SYS) from the input while the boost converter powers the system load from the battery using the same external inductor, L1. THE BATTERY CHARGER The LTC4040 includes a full-featured constant-current (CC)/constant-voltage (CV) battery charger with automatic recharge, automatic termination by safety timer, low volt- age trickle charging, bad-battery detection and thermis - tor sensor input for out-of-temperature charge pausing. The batter y charger is a high efficiency buck switching converter used to transfer charge from V SYS to BAT via the SW pin. The charger can be disabled by pulling the CHGOFF pin above 1.2V. Buck Switching Charger The LTC4040 battery charger is a constant frequency (2.25MHz) synchronous buck converter capable of directly charging the battery to its charge voltage with an externally programmable charge current up to 2.5A from an input supply as high as 5.5V. A zero current comparator monitors the inductor current and shuts off the NMOS synchronous rectifier once the current reduces to approximately 250mA. This prevents the inductor current from reversing and improves efficiency for low charging current. Battery Preconditioning (T rickle Charge) and Bad-Battery Fault When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below VLOWBAT, typically 2.85V, an automatic trickle charge feature sets the charge current to 1/8th or 12.5% of the programmed value. To improve charge current accuracy at this low level, the buck switch- ing charger is turned off and a secondary linear charger is used to deliver charge to the battery . If the low voltage persists for more than half an hour, the battery charger automatically terminates and indicates, via the CHRG and FAULT pins, that the battery is in bad-battery fault. Constant-Current Mode Charging Once the battery voltage is above V LOWBAT, the charger begins charging in full power constant-current mode. The current delivered to the battery will try to reach 2000V/ R PROG. Depending on the external load condition, the battery charger may or may not be able to charge at the full programmed rate. The external load will always be prioritized over the battery charge current. The battery charger will charge at the full programmed rate only if the sum of the external load and the charger input current is less than or equal to the input current limit set by R

automatic recharge threshold. Table 1. Charge Status Indication due to insufficient power available to the battery charger. pulled low, indicating that the charging has been terminated. until the temperature returns to the safe charging range. thermistor gain value ß25/85.

For more information www.linear .com/L TC4040 operaTion Differential Undervoltage Lockout An undervoltage lockout circuit monitors the differential volt- age between VSYS and BAT and shuts off the charger if the BAT voltage reaches within 50mV of the VSYS voltage. Charging does not resume until this difference increases to 145mV. BACKUP BOOST CONVERTER To supply the system load from the battery in backup mode, the LTC4040 contains a 1.125MHz constant-frequency current-mode synchronous boost switching regulator with output disconnect and automatic Burst Mode features. The regulator can provide a maximum load of 2.5A from a battery as low as 3.2V and the system output voltage SYS) can be programmed up to a maximum of 5V via the BSTFB pin. See the Applications Information section for details. The converter can be disabled by pulling the BSTOFF pin high. The boost regulator includes safety features like short-circuit current protection , input un - dervoltage lockout, and output overvoltage protection. Zero Current Comparator The LT C4040 boost converter includes a zero current comparator which monitors the inductor current and shuts off the PMOS synchronous rectifier once the current drops to approximately 250mA. This prevents the induc- tor current from reversing in polarity thereby improving efficiency at light loads. PMOS Synchronous Rectifier T o prevent the inductor current from running away, the PMOS synchronous rectifier is only enabled when VSYS > (VBAT – 200mV). Additionally, if the current through the synchronous FET (PMOS) ever exceeds 8A, the con- verter skips the next two clock cycles so that the inductor current has a chance to discharge safely below this level. Short-Circuit Protection The output disconnect feature enables the LTC4040 boost converter to survive a short circuit at its output. It incorpo- rates internal features such as current limit foldback and thermal shutdown for protection from excessive power dissipation during short circuit. V BAT Undervoltage Lockout To prevent the battery from discharging too deeply, the LTC4040 incorporates an undervoltage lockout circuit which shuts down the boost regulator when V BAT drops below 2.45V. Boost Overvoltage Protection If the BSTFB node were inadvertently shorted to ground, then the boost converter output would increase indefinitely with the maximum current that could be sourced from BAT. The LTC4040 protects against this by shutting off both switches if the output voltage exceeds 5.5V. Burst Mode Operation To improve battery life during backup, the LTC4040 boost converter provides automatic Burst Mode operation which increases the efficiency of power conversion at very light loads. Burst Mode operation is initiated if the output load current falls below an internally set threshold. Once Burst Mode operation is initiated, only the circuitry required to monitor the output is kept alive. This is referred to as the sleep state in which the backup boost consumes only 40µA from the battery. When the V SYS pin voltage drops by about 1% from its nominal value, the part wakes up and commences normal PWM operation. The output capacitor recharges and causes the part to re-enter the sleep state if the output load remains less than the Burst Mode threshold. The frequency of this intermittent PWM or Burst Mode operation depends on the load current; that is, as the load current drops further below the burst threshold, the boost converter turns on less frequently. When the load current increases above the burst thresh- old, the converter seamlessly resumes continuous PWM operation. Thus, Burst Mode operation maximizes the efficiency at very light loads by minimizing switching and quiescent losses. However, the output ripple typically increases to about 2% peak-to-peak. Burst Mode ripple can be reduced, in some circumstances, by placing a small phase-lead capacitor (C PL) between the VSYS and BSTFB pins. However, this may adversely affect the efficiency and the quiescent current at light loads. Typical values of C PL range from 15pF to 100pF.

For more information www.linear .com/L TC4040 operaTion VBAT > VSYS Operation The LTC4040 boost converter will maintain voltage regula- tion even if its input voltage is above the output voltage. This is achieved by terminating the switching of the syn- chronous PMOS and applying V BAT voltage statically on its gate. This ensures that the slope of the inductor current will reverse during the time current is flowing to the out- put. Since the PMOS no longer acts as a low impedance switch in this mode, there will be more power dissipation within the IC. This will cause a sharp drop in the efficiency. The maximum output current should be limited in order to maintain an acceptable junction temperature. INPUT CURRENT LIMIT AND CLPROG MONITOR The LTC4040 contains an input current limit circuit which monitors the total system current (the external load plus the charger input current) via an external series resistor, R S, connected between the pins V IN and CLN. The part does not actually limit the external load but as the exter- nal load demand increases, it reduces charge current, if necessary, in an attempt to maintain a maximum of 25mV across the VIN and CLN pins. Please refer to Programming the Input Current Limit and CLPROG Monitor section in Applications Information. However, if the external load demand exceeds the limit set by R S, the part does not reduce the load current but the charge current will drop to zero. In all scenarios, the voltage on the CLPROG pin will correctly represent the total system current. 800mV on the CLPROG pin represents the full-scale current set by the external series resistor, R POWER-FAIL COMP ARATOR AND MODE SWITCHING The LTC4040 contains a fast power-fail comparator which switches the part from normal to backup mode in the event the input supply voltage falls below an externally programmed threshold voltage. This threshold voltage is programmed by an external resistor divider via the PFI pin. See the Applications Information section for details of how to choose values for the resistor divider. The output of the power-fail comparator also directly drives the gate of an open-drain NMOS to report the status of the avail - ability of input power via the PFO pin. If input power is available, the PFO pin is high impedance; otherwise, the pin is pulled down to ground. At the onset of backup mode, the battery charger shuts off, the external NMOS pass transistors (MN1 and MN2 in Block Diagram) are quickly turned off by discharging IGATE to ground thereby disconnecting the system output V SYS from the input and the backup boost converter activates promptly to deliver load from the battery. Although the power-fail comparator has a hysteresis of approximately 30mV, it may not be able to overcome the input voltage spike resulting from the sudden collapse of the forward current from the input to V SYS. To prevent repeated un- wanted mode switching, once activated, the backup boost stays on for at least half a second . During this time, the power-fail comparator output is ignored and an internal switch of approximately 270Ω pulls down the OVSNS pin to help discharge the input. After the half-second timer expires, if the power-fail comparator output indicates that power is still not available, the backup boost continues to deliver the load but the pull-down on the OVSNS pin is released. When the power-fail comparator detects that input power is available, the OVP charge pump starts to charge up the IGATE pin but the backup boost converter continues to deliver system load until IGATE is approximately 8V. This ensures that the forward conduction path through the external NFET pass transistors has been established. At this point, the backup boost gets deactivated and the charger turns back on to charge the battery while the system load gets delivered directly from the input to V SYS through the pass transistors. RESET COMP ARATOR The LTC4040 contains a reset comparator which moni - tors VSYS under all operating modes via the RSTFB pin and reports the status via an open-drain NMOS transistor on the RST pin. At any time, if V SYS falls 7.5% from its programmed value, the RST pin pulls low almost instan- taneously. However, the comparator waits approximately 232ms after V SYS rises above the threshold before making the RST pin high impedance. Please refer to Programming the Reset Comparator Threshold section in Applications Information.

For more information www.linear .com/L TC4040 OPTIONAL INPUT OVERVOL TAGE PROTECTION (OVP) The LTC4040 can protect itself from the inadvertent application of excessive voltage with just two external components: an N-channel FET (MN1) and a 6.2k resis - tor as shown in the Block Diagram. The maximum safe overvoltage magnitude will be determined by the choice of external NMOS and its associated drain breakdown voltage. The optional overvoltage protection (OVP) module consists of two pins. The first, OVSNS, is used to measure the applied voltage through an external resistor. The second, IGATE, is an output used to drive the gate pins of two external N- channel FETs, MN1 and MN2 (Block Diagram). The voltage at the OVSNS pin will be lower than the OVP input voltage by about 250mV due to the OVP circuit’ s quiescent cur- rent flowing through the OVSNS resistor. When OVSNS is below 6V, an internal charge pump will drive IGATE to ap- proximately 1.88 • VOVSNS. This will enhance the N-channel FET s and provide a low impedance connection to VSYS and power the chip. If OVSNS should rise above 6V due to a operaTion fault, IGATE will be pulled down to ground, disabling the external FETs to protect downstream circuitry. At the same time, the backup boost converter will be activated to supply the system load from the battery. When the voltage drops below 6V again, the external FETs will be re-enabled. If the OVP feature is not desired, remove MN1, short OVSNS to VIN and apply external power directly to VIN. SHUTDOWN MODE OPERATION The LTC4040 can be shutdown almost entirely by pulling both CHGOFF and BSTOFF pin above 1.2V. In this mode, the internal charge pump is shutdown and IGATE is pulled to ground disconnecting the forward path from input to output via the external FETs. Only the internal OVP shunt regulator remains active to monitor the input supply for any possible overvoltage condition and consumes about 25µA via the OVSNS pin. Total current draw from the BAT pin drops to below 3µA during shutdown.

Figure 1. Battery Cycle Life and Capacity degrades even faster when batteries remain fully charged. cycles and battery-capacity levels. tor during the transition to backup mode. the battery capacity drops to 80% of the rated capacity. cell capacity and cycle life for a typical Li-Ion battery cell. more than three times to 1800 charge/ discharge cycles.

For more information www.linear .com/L TC4040 PROGRAMMING THE INPUT CURRENT LIMIT AND CLPROG MONITOR The input current limit is programmed by connecting a series resistor between the VIN and CLN pins. To limit the total system current to ISYSLIM, the value of the required resistor can be calculated using the following equation: RS = 25mV ISYSLIM For example, to set the current limit to 2A, the se- ries resistor should be 12.5mΩ. As discussed in the Operations section, the part does not limit the system current but reduces the charge current to zero in case the system load exceeds this limit. The voltage on the CLPROG pin always represents the total system current I SYS through the external series resistance, RS. 800mV on CLPROG represents the full-scale current set by RS. The system current can be calculated from the CLPROG pin voltage by using the following equation: ISYS = VCLPROG 32•RS For example, if the CLPROG pin voltage is 600mV and R S is 12.5mΩ, then the total system current is 1.5A. As shown in the block diagram, the CLPROG pin is not buff- ered internally. So it is important to isolate this pin before connecting to an ADC or any other monitoring device . Failure to do so would degrade the accuracy of this cir cuit. PROGRAMMING THE BOOST OUTPUT VOL TAGE The boost converter output voltage in backup mode can be programmed for any voltage from 3.5V to 5V by using a resistor divider from the VSYS pin to GND via the BSTFB pin such that: VSYS = VBSTFB • 1+ RFB1 RFB2 RFB2 VBSTFB is 0.8V. See the Block Diagram. Typical values for RFB1 and RFB2 are in the range of 40k to 2M. Too small a resistor will result in a large quiescent current whereas too large a resistor coupled with any parasitic BSTFB pin capacitance will create an additional pole and may cause loop instability. P ROGRAMMING THE RESET COMP ARATOR THRESHOLD The threshold for the reset comparator can be programmed by using a resistor divider from the VSYS pin to GND via the RSTFB pin such that: VSYS(RST) = VRSTFB • 1+ RFB1 RFB2 RFB2 VRSTFB is 0.74V. See the Block Diagram. Typical values for RFB1 and RFB2 are in the range of 40k to 2M. In most applications, the BSTFB and RSTFB pins can be shorted together and only one resistor divider between VSYS and GND is needed to set the V SYS voltage during backup mode and the reset threshold 7.5% below the VSYS pro- grammed voltage. CHOOSING THE EXTERNAL RESISTOR FOR THE OVERVOL TAGE PROTECTION (OVP) MODULE In an overvoltage condition , the OVSNS pin will be clamped at 6V. The external 6.2k resistor must be sized appropriately to dissipate the resultant power. For example, a 1/8W 6.2k resistor can have at most PMAX •6.2kΩ = 28V applied across its terminals. With the 6V at OVSNS, the maximum overvoltage magnitude that this resistor can withstand is 34V. A 1/4W 6.2k resistor raises the value to 45V. The OVSNS pin’s absolute maximum current rating of 10mA imposes an upper limit of 68V protection. applicaTions inForMaTion

operation. See Table 2 for a list of recommended transistors. Table 2. Recommended NMOS FETs for Overvoltage Protection 2.2µH can be used to lower the inductor current ripple. order to prevent an inductor current runaway situation. Table 3. Recommended Inductors for the LTC4040

SYS pin should be at least 75µF.

D• 1 fOSC If the maximum allowable ripple is 20mV under 2.5A steady-state load while boosting from 3. 2V to 5V (D = 36%), the required capacitance at VSYS is calculated to be at least 40µF using the above equation. Please refer to Table 4 for recommended ceramic capacitor manufacturers.

Table 4. Recommended Ceramic Capacitor Manufacturers parallel with the actual battery at the BAT pin. should be inserted between the PROG pin and the device. hence the stability of the converter.

the RHP zero to shift downward and cause instability. and place the battery as close to the BAT pin as possible. trip point of 0°C, and a hot trip point of 39°C. Figure 2. NTC Connections

Even though the converter can operate in both step-

the ground plane through an array of vias.

4040 F03

Figure 3. Hot-Loop Illustration for the LTC4040 Switching Converter

To minimize parasitic inductance, the ground plane

4040 TA02

3586 F04

Figure 4. High Frequency Ground Currents Follow Their Incident Path.

The other important components that need to be placed

current limit (typ. 6.5A) in backup boost mode. path. The same is true for the PFI divider. has extremely limited drive current.

For more information www.linear .com/L TC4040 Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 ±0.10 (2 SIDES) 5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 23 24 BOTTOM VIEW—EXPOSED PAD 0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR C = 0.35 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD24) QFN 0506 REV A RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 2.65 ±0.052.00 REF

3.00 REF

4.10 ±0.05 5.50 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10

2.00 REF

3.65 ±0.10 3.65 ±0.05 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) package DescripTion

For more information www.linear .com/L TC4040 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 07/15 Added new Applications section, Charge Voltage Modified Figure 2 Re-assigned new figure numbers 22 – 23

For more information www.linear .com/L TC4040  LINEAR TECHNOLOGY CORPORATION 2015 LT 0715 REV A • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TC4040 relaTeD parTs Typical applicaTion 5V Backup Application with OVP Protection and Non-Backed Up Load Option (Charge Current Setting: 2.5A, Input Current Limit Setting: 4A) 324k 2.2µH VSYS PROGBSTOFF GNDCHGOFF F2 F1 F0 IGATE L TC4040 VIN CLN 1690kMN2 MN1 VSYS 4.35V TO 5V RS 6m/uni03A9 10µF RBIAS 100µF2.2µF TO BACKED-UP SYSTEM LOAD TO NON-BACKED-UP LOAD BSTFB RSTFB 4.35V TO 5V INPUT SUPPL Y (PROTECTED TO 40V) SW BAT NTC NTC 800/uni03A9 Li-Ion BATTERY 4.1V

4040 TA03

60.4k178k 6.2k 1/4W OVP OPT L1: COILCRAFT XAL-5030-222 MN1: VISHAY/SILICONIX SiS488DN MN2: VISHAY/SILICONIX SIR424DP-T1-GE3 VPWR PART NUMBER DESCRIPTION COMMENTS LTC3226 2-Cell Supercapacitor Charger with Backup PowerPath™ Controller 1x/2x Multimode Charge Pump Supercapacitor Charger, Internal 2A LDO Backup Supply LTC3350 High Current Supercapacitor Backup Controller and System Monitor High Efficiency Synchronous Step-Down CC-CV Charging of 1-4 Series Supercapacitors LTC3355 20V 1A Buck DC/DC with Integrated SCAP Charger and Backup Regulator 1A Main Buck Regulator, 5A Boost Backup Regulator LTC4089 USB Power Manager with High Voltage Switching Charger 1.2A Charger for Li-Ion from 6V to 86V Supply LTC4090 USB Power Manager with 2A High Voltage Bat-T rack Buck Regulator 2A Charger with Bat-T rack for Li-Ion Batteries LTC4110 Battery Backup System Manager Complete Manager for Li-Ion/Polymer, Lead Acid, NiMH/NiCd Batteries and Supercapacitors LTC4155/LTC4156 Dual Input Power Manager/3.5A Li-Ion Battery Charger with I2C Control and USB OTG 3.5A Charge Current for Li-Ion/Polymer, LTC4156 for LiFePO4 Batteries LTC4160 Switching Power Manager with USB On-The-Go and Overvoltage Protection 1.2A Charge Current

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Summary

2.5A Battery Backup Power Manager

Description

2.5A Battery Backup Power Manager

Source title LTC4040_15 Datasheet(PDF) - Linear Technology

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