LTC4009-1

Linear Technology

High Effi ciency, Multi-Chemistry Battery Charger

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LTC4009 LINER

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FEATURES

APPLICATIONS

DESCRIPTION

High Efﬁ ciency, Multi-Chemistry Battery Charger The L TC4009 is a constant-current/constant-voltage battery charger controller . It uses a synchronous quasi-constant frequency PWM control architecture that will not generate audible noise with ceramic bulk capacitors. Charge cur- rent is set by the combination of external sense, input and programming resistors. With no built-in termination, the L TC4009 family charges a wide range of batteries under external control. The L TC4009 features a fully adjustable output voltage, while the L TC4009-1 and L TC4009-2 can be pin-programmed for lithium-ion/polymer battery packs of 1-, 2-, 3- or 4-series cells. The L TC4009-1 provides output voltage of 4.1V/cell, and the L TC4009-2 is a 4.2V/cell version. The device includes AC adapter input current limiting which maximizes the charge rate for a ﬁ xed input power level. An external sense resistor programs the input current limit, and the ICL status pin indicates when the battery charge current is being reduced as a result of AC adapter current limiting. The CHRG status pin is active during all charging modes, including special indication for low charge current. n General Purpose Battery Charger Controller n Efﬁ cient 550kHz Synchronous Buck PWM Topology n ±0.5% Output Float Voltage Accuracy n Programmable Charge Current: 4% Accuracy n Programmable AC Adapter Current Limit: 3% Accuracy n No Audible Noise with Ceramic Capacitors n Wide Input Voltage Range: 6V to 28V n Wide Output Voltage Range: 2V to 28V n Indicator Outputs for AC Adapter Present, Charging, C/10 Current Detection and Input Current Limiting n Analog Charge Current Monitor n Micropower Shutdown n Thermally Enhanced 20-Pin 4mm × 4mm × 0.75mm n Notebook Computers n Portable Instruments n Battery Backup Systems Efﬁ ciency at DCIN = 20V L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5723970. CLP FROM ADAPTER 13V TO 20V CHARGE CURRENT MONITOR 0.1μF 5.1k 33mΩ 3.01k 0.1μF 6.8μH 33mΩ DCIN 0.1μF 2μF 0.1μF 14.3k 1.5k 6.04k 301k 32.8k 26.7k L TC4009 DCDIV CHRG ACP ICL SHDN ITH PROG CLN BOOST TGATE SW INTVDD BGATE TO/FROM MCU GND CSP CSN BAT FBDIV VFB 20μF POWER TO SYSTEM 4.7nF 20μF

4009 TA01a

12.3V Li-Ion BATTERY 3.01k + CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS (mW) 100 100 1000 10000 0.5 1.0 1.5 2.0

4009 TA01b

2.5 3.0 EFFICIENCY POWER LOSS VFLOAT = 12.3V RSENSE = 33mΩ RIN = 3.01k RPROG = 26.7k DIN = SSB44 L = IHLP-2525CZ 6.8μH

(Note 1) 20 19 18 17 16 6 7 8 TOP VIEW UF PACKAGE 20-LEAD (4mm s 4mm) PLASTIC QFN 9 10 15CLN CLP DCIN ICL DCDIV CSP CSN PROG ITH BAT BOOST TGATE SW INTV DD BGATE SHDN ACP CHRG FBDIV VFB TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 20 19 18 17 16 6 7 8 TOP VIEW UF PACKAGE 20-LEAD (4mm s 4mm) PLASTIC QFN 9 10 15CLN CLP DCIN ICL DCDIV CSP CSN PROG ITH BAT BOOST TGATE SW INTV DD BGATE SHDN ACP CHRG FVS0 FVS1 TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC4009CUF#PBF L TC4009CUF#TRPBF 4009 20-Lead (4mm × 4mm) Plastic QFN 0°C to 85°C L TC4009CUF-1#PBF L TC4009CUF-1#TRPBF 40091 20-Lead (4mm × 4mm) Plastic QFN 0°C to 85°C L TC4009CUF-2#PBF L TC4009CUF-2#TRPBF 40092 20-Lead (4mm × 4mm) Plastic QFN 0°C to 85°C Consult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. Consult L TC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/ L TC4009 L TC4009-1 L TC4009-2

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. DCIN = 20V , BAT = 12V , GND = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Charge Voltage Regulation V TOL VBAT Accuracy (See Test Circuits) L TC4009 l –0.5 –0.8 0.5 0.8 L TC4009-1/L TC4009-2 l –0.6 –0.8 0.6 0.8 IVFB VFB Input Bias Current V FB = 1.2V ±20 nA RON FBDIV On-Resistance I LOAD = 100μA l 85 190 Ω ILEAK-FBDIV FBDIV Output Leakage Current SHDN = 0V , FBDIV = 0V l –1 0 1 μA VBOV VFB Overvoltage Threshold L TC4009 l 1.235 1.281 1.32 V BAT Overvoltage Threshold L TC4009-1/L TC4009-2, Relative to Selected Output Voltage l 103 106 109 % Charge Current Regulation ITOL Charge Current Accuracy with RIN = 3.01k, 5V < BAT < 18V RPROG = 26.7k l VSENSE = 0mV , PROG = 1.2V –12.75 –11.67 –10.95 μA AI Current Sense Ampliﬁ er Gain (PROG ΔI) with RIN = 3.01k, 5V < BAT < 18V VSENSE Step from 0mV to 5mV , PROG = 1.2V VCS-MAX Maximum Peak Current Sense Threshold Voltage per Cycle (RIN = 3.01k) ITH = 2V ITH = 5V l l 140 185 325 235 430 mV mV VC10 C/10 Indicator Threshold Voltage PROG Falling 340 400 460 mV VREV Reverse Current Threshold Voltage PROG Falling 180 253 295 mV Input Current Regulation V CL Current Limit Threshold CLP – CLN l 100 100 103 104 mV mV ICLN CLN Input Bias Current CLN = CLP ±100 nA VICL ICL Indicator Threshold (CLP – CLN) – V CL –8 –5 –2 mV DCIN, CLP Supplies OVR Operating Voltage Range DCIN and CLP 6 28 V I DCO DCIN Operating Current No Gate Loads 1.5 2 mA ICLPO CLP Operating Current CLP = 20V , No Gate Loads 0.5 0.8 mA VCBT CLP Boost Threshold Voltage CLP – DCIN, CLP Rising l 10 25 60 mV VCNT CLP Normal Threshold Voltage (Note 5) DCIN – CLP , CLP Falling l 10 25 60 mV VOVP DCDIV Overvoltage Protection Threshold DCDIV Rising 1.75 1.825 1.9 V VOVP(HYST) DCDIV OVP Threshold Hysteresis 110 mV Shutdown VACP DCDIV AC Present Threshold Voltage DCDIV Rising l 1.145 1.2 1.255 V VACP(HYST) DCDIV ACP Threshold Hysteresis Voltage 50 mV IDCDIV DCDIV Input Current DCDIV = 1.2V –1 0 1 μA VIL SHDN Input Voltage Low l 300 mV VIH SHDN Input Voltage High l 1.4 V RIN SHDN Pull-Down Resistance 50 kΩ IDCS DCIN Shutdown Current SHDN = 0V 215 μA ICLPS CLP Shutdown Current CLP = 12V , SHDN = 0V or DCDIV = 0V l 91 8 μ A

ELECTRICAL CHARACTERISTICS The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. DCIN = 20V , BAT = 12V , GND = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ILEAK-BAT BAT Leakage Current SHDN = 0V or DCDIV = 0V , 0V ≤ CSP = CSN = BAT ≤ 20V l –1 0 1 μA ILEAK-CSN CSN Leakage Current SHDN = 0V or DCDIV = 0V , 0V ≤ CSP = CSN = BAT ≤ 20V l –1 0 1 μA ILEAK-CSP CSP Leakage Current SHDN = 0V or DCDIV = 0V , 0V ≤ CSP = CSN = BAT ≤ 20V l –1 0 1 μA ILEAK-SW SW Leakage Current SHDN = 0V or DCDIV = 0V , 0V ≤ SW ≤ 20V l –1 0 2 μA INTVDD Regulator INTVDD Output Voltage No Load l 4.85 5 5.15 V ΔVDD Load Regulation I DD = 20mA –0.4 –1 % IDD Short-Circuit Current (Note 6) INTV DD = 0V 50 85 120 mA Switching Regulator V CE Charge Enable Threshold Voltage CLP – BAT , CLP Rising l 65 100 135 mV IITH ITH Current ITH = 1.4V –40/+90 μA fTYP Typical Switching Frequency 467 550 633 kHz fMIN Minimum Switching Frequency C LOAD = 3.3nF 20 25 kHz DCMAX Maximum Duty Cycle C LOAD = 3.3nF 98 99 % tR-TG TGATE Rise Time C LOAD = 3.3nF , 10% – 90% 60 110 ns tF-TG TGATE Fall Time C LOAD = 3.3nF , 90% – 10% 50 90 ns tR-BG BGATE Rise Time C LOAD = 3.3nF , 10% – 90% 60 90 ns tF-BG BGATE Fall Time C LOAD = 3.3nF , 90% – 10% 60 110 ns tNO TGATE, BGATE Non-Overlap Time C LOAD = 3.3nF , 10% – 10% 110 ns Float Voltage Select Inputs (L TC4009-1/L TC4009-2 Only) V IL Input Voltage Low 0.5 V VIH Input Voltage High 3.5 V IIN Input Current 0V ≤ V IN ≤ 5V –10 10 μA Indicator Outputs VOL Output Voltage Low I LOAD = 100μA, PROG = 1.2V 500 mV ILEAK Output Leakage SHDN = 0V , DCDIV = 0V , VOUT = 20V l –10 10 μA IC10 CHRG C/10 Current Sink CHRG = 2.5V l 15 25 38 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC4009 is guaranteed to meet performance speciﬁ cations over the 0°C to 85°C operating temperature range. Note 3: Operating junction temperature T J (in °C) is calculated from the ambient temperature TA and the total continuous package power dissipation PD (in watts) by the formula TJ = TA + (θJA • PD). Refer to the Applications Information section for details. Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise speciﬁ ed. Note 5: This threshold is guaranteed to be satisﬁ ed if CLP = DCIN when the L TC4009 exits shutdown. Note 6: Output current may be limited by internal power dissipation. Refer to the Applications Information section for details.

TYPICAL PERFORMANCE CHARACTERISTICS Efﬁ ciency at DCIN = 20V , BAT = 8V VFB Line Regulation TEST CIRCUITS 1013 12 1.2085V 1.2085V TARGET PROG V FB ITH

4009 TC01

0.6V EA FROM ICL (CLP = CLN) L TC1055 1113 12 1.2085V TARGET VARIES WITH FVS0,1 PROG BAT ITH

4009 TC02

0.6V EA FROM ICL (CLP = CLN) L TC1055 CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS (mW) 100 100 1000 10000 0.5 1.0 1.5 2.0

4009 G01

2.5 3.0 POWER LOSS EFFICIENCY RSENSE = 33mΩ RIN = 3.01k Efﬁ ciency at DCIN = 20V , BAT = 12V CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS (mW) 100 100 1000 10000 0.5 1.0 1.5 2.0

4009 G02

2.5 3.0 POWER LOSS EFFICIENCY RSENSE = 33mΩ RIN = 3.01k Efﬁ ciency at DCIN = 20V , BAT = 16V CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS (mW) 100 100 1000 10000 0.5 1.0 1.5 2.0

4009 G03

2.5 3.0 POWER LOSS EFFICIENCY RSENSE = 33mΩ RIN = 3.01k CLP (V) VFB ERROR (%) 0.02 0.06 0.10

4009 G04

–0.02 –0.06 0.04 0.08 –0.04 –0.08 –0.10 10 15 20 30 L TC4009 TEST CIRCUIT BAT (V) RON (Ω) 100 150 175 200 10 20 25 300

4009 G05

CLP = BAT + 3V (CLP ≥ 6V) FBDIV RON vs BAT (TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8μH)

TYPICAL PERFORMANCE CHARACTERISTICS PWM Frequency vs Duty CycleGate Drive Non-Overlap Charge Current Line Regulation Input Current Limit Battery Load Dump BATTERY VOL TAGE (500mV/DIV) LOAD STATE TIME (1ms/DIV)CLP = 20V VFLOAT = 12.3V

4009 G06

12.1V 1A DCIN (V) –0.5 CHARGE CURRENT ERROR (%) –0.4 –0.2 –0.1 0.5 0.2 10 15

4009 G07

–0.3 0.3 0.4 0.1 20 25 ICHG = 1A ICHG = 2A ICHG = 3A BAT = 6V RSENSE = 33mΩ RIN = 3.01k Charge Current Load Regulation BAT (V) 11.0 CHARGE CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –0.5 12.6

4009 G08

11.4 11.8 12.2 13.0 ICHG = 3A ICHG = 2A ICHG = 1A DCIN = 20V RSENSE = 33mΩ RIN = 3.01k SYSTEM LOAD (A) CURRENT (A)0.5 1.0 1.5 1.5 2.5

4009 G09

–0.5 –1.0 0.5 1.0 2.0 2.0 2.5 3.0 IIN ICHG ICL STATE 2.5A BULK CHARGE 2.1A INPUT CURRENT LIMIT PWM Soft-Start ICHG 2A/DIV TIME (500μs/DIV)

4009 G10

TIME (80ns/DIV) EXTERNAL FET DRIVE (1V/DIV)

4009 G11

DUTY CYCLE (%) PWM FREQUENCY (kHz) 100 200 300 400 500 600 20 40 60 80

4009 G12

CLP = 6V CLP = 12V CLP = 20V CLP = 25V ICHG = 750mA (TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8μH) Charge Current Accuracy BAT (V) 12 20

4009 G15

48 1 621 4 2 261 0 1 8 2 4 CHARGE CURRENT ERROR (%) DCIN = 24V RPROG = 35.7k RSENSE = 33mΩ RIN = 3.01k DCIN = 12V R PROG = 26.7k

CLN (Pin 1): Adapter Input Current Limit Negative Input. The L TC4009 senses voltage on this pin to determine if the charge current should be reduced to limit total input current. The threshold is set 100mV below the CLP pin. An external ﬁ lter should be used to remove switching noise. This input should be tied to CLP if not used. Operating voltage range is (CLP – 110mV) to CLP. CLP (Pin 2): Adapter Input Current Limit Positive Input. The L TC4009 also draws power from this pin, including a small amount for some shutdown functions. Operating voltage range is GND to 28V . DCIN (Pin 3): DC Power Input. The L TC4009 draws power from this pin when an external DC power source is present. This pin is typically isolated from the CLP pin by a diode and should be bypassed with a capacitance of 0.1μF or more. Operating voltage range is GND to 28V . ICL (Pin 4): Active-Low Input Current Limit Indicator Out- put. This open-drain output pulls to GND when the charge current is reduced because of AC adapter input current limiting. This output should be left ﬂ oating if not used. DCDIV (Pin 5): AC Adapter Present Comparator Input. The L TC4009 senses voltage on this pin to determine when an adequate DC power source is present, or if an overvoltage condition exists. An external resistor divider programs these threshold levels relative to DCIN. Operating voltage range is GND to INTV DD. SHDN (Pin 6): Active-low Shutdown Input. Driving SHDN below 300mV unconditionally forces the L TC4009 into the shutdown state. This input has a 50kΩ internal pulldown to GND. Operating voltage range is GND to INTV DD. ACP (Pin 7): Active-Low AC Adapter Present Indicator Output. This open-drain output pulls to GND when adequate AC adapter (DC) voltage is present, based on the DCDIV input. This output should be left ﬂ oating if not used. CHRG (Pin 8): Active-Low Charge Indicator Output. This open-drain output provides three levels of information about charge status using a strong pull-down, 25μA weak pull-down or high impedance. Refer to the Operation and Applications Information sections for further details. This output should be left ﬂ oating if not used. FBDIV (Pin 9, L TC4009): Battery Voltage Feedback Resis- tor Divider Source. The L TC4009 connects this pin to BAT when charging is in progress. FBDIV is an open-drain PFET output to BAT with an operating voltage range of GND to BAT . Battery Shutdown CurrentPWM Frequency vs Charge Current CHARGE CURRENT (A) PWM FREQUENCY (kHz) 100 200 300 400 600 0.5 1.0 1.5 2.0

4009 G13

2.5 3.0 500 BAT = 14.5V BAT = 12V BAT = 5V CLP = 15V RSENSE = 33mΩ RIN = 3.01k BATTERY VOLTAGE (V) BATTERY CURRENT (μA)

4009 G14

TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C unless otherwise noted. DIN = SSB44, L = IHLP-2525 6.8μH)

FVS0 (Pin 9, L TC4009-1/L TC4009-2): Battery Voltage Select Input (LSB). This pin is one of two pins used on the L TC4009-1 or L TC4009-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTV DD. Operating voltage range is GND to INTVDD. VFB (Pin 10, L TC4009): Battery Voltage Feedback Input. An external resistor divider between FBDIV and GND with the center tap connected to V FB programs the charger output voltage. In constant voltage mode, this pin is nominally at 1.2085V . Refer to the Applications Information section for complete details on programming battery ﬂ oat voltage. Operating voltage range is GND to 1.25V . FVS1 (Pin 10, L TC4009-1/L TC4009-2): Battery Voltage Select Input (MSB). This pin is one of two pins used on the L TC4009-1 or L TC4009-2 to select one of four preset battery voltages. Selection is done by connecting to either GND or INTV DD. Operating voltage range is GND to INTVDD. BAT (Pin 11): Battery Pack Connection. The L TC4009 uses the voltage on this pin to control PWM operation when charging. Operating voltage range is GND to CLN. ITH (Pin 12): PWM Control Voltage and Compensation Node. The L TC4009 develops a voltage on this pin to control cycle-by-cycle peak inductor current. An external R-C network connected to ITH provides PWM loop com- pensation. Refer to the Applications Information section for further details on establishing loop stability. Operating voltage range is GND to INTV DD. PROG (Pin 13): Charge Current Programming and Monitor- ing Pin. An external resistance connected between PROG and GND, along with the current sense and PWM input resistors, programs the maximum charge current. The voltage on this pin can also provide a linearized indicator of charge current. Refer to the Applications Information section for complete details on current programming and monitoring. Operating voltage range is GND to INTV DD. CSN (Pin 14): Charge Current Sense Negative In- put. Place an external input resistor (R IN, Figure 1) between this pin and the negative side of the charge current sense resistor . Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV). CSP (Pin 15): Charge Current Sense Positive Input. Place an external input resistor (R IN, Figure 1) be- tween this pin and the positive side of the charge current sense resistor . Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV). BGATE (Pin 16): External Synchronous NFET Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used for synchronous rectiﬁ cation to increase efﬁ ciency in the step-down DC/DC converter . Operating voltage is GND to INTV DD. BGATE should be left ﬂ oating if not used. INTVDD (Pin 17): Internal 5V Regulator Output. This pin provides a means of bypassing the internal 5V regulator used to power the L TC4009 PWM FET drivers. This supply shuts down when the L TC4009 shuts down. Refer to the Application Information section for details if additional power is drawn from this pin by the application circuit. SW (Pin 18): PWM Switch Node. The L TC4009 uses the voltage on this pin as the source reference for its topside NFET (PWM switch) driver . Refer to the Applications In- formation section for additional PCB layout suggestions related to this critical circuit node. Operating voltage range is GND to CLN. TGATE (Pin 19): External NFET Switch Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used in the DC/DC converter . Operating voltage range is GND to (CLN + 5V). BOOST (Pin 20): TGATE Driver Supply Input. A bootstrap capacitor is returned to this pin from a charge network connected to SW and INTV DD. Refer to the Applications Information section for complete details on circuit topol- ogy and component values. Operating voltage ranges from (INTVDD – 1V) to (CLN + 5V). Exposed Pad (Pin 21): Ground. The package paddle provides a single-point ground for the internal voltage reference and other critical L TC4009 circuits. It must be soldered to a suitable PCB copper ground pad for proper electrical operation and to obtain the speciﬁ ed package thermal resistance.

BLOCK DIAGRAM (L TC4009) EA TO INTERNAL CIRCUITS CC CA 1.2085V REFERENCE REGULATOR PWM LOGIC BOOST AND OV DETECTION C/10 DETECTION OSCILLATORBAT SHUTDOWN CONTROL TO INTERNAL CIRCUITS SHUTDOWN OVERVOL TAGE CHARGE INPUT CURRENT LIMIT TGATE 20BOOST 12ITH 13PROG 14CSN 15CSP 18SW 21GND

4009 BD01

BLOCK DIAGRAM (L TC4009-1/L TC4009-2) EA TO INTERNAL CIRCUITS CC VFB CA 1.2085V REFERENCE REGULATOR PWM LOGIC BOOST AND OV DETECTION C/10 DETECTION OSCILLATOR OUTPUT VOL TAGE SELECT SHUTDOWN CONTROL TO INTERNAL CIRCUITS SHUTDOWN OVERVOL TAGE CHARGE INPUT CURRENT LIMIT TGATE 20BOOST 12ITH 13PROG 14CSN 15CSP 18SW 21GND

4009 BD02

The L TC4009 is a synchronous step-down (buck) current mode PWM battery charger controller . The maximum charge current is programmed by the combination of a charge current sense resistor (R SENSE), matched input resistors (R IN, Figure 1), and a programming resistor (RPROG) between the PROG and GND pins. Battery volt- age is programmed either with an external resistor divider between FBDIV and GND (L TC4009) or two digital battery voltage select pins (L TC4009-1/L TC4009-2). In addition, the PROG pin provides a linearized voltage output of the actual charge current. The L TC4009 family does not have any built-in charge termination and is ﬂ exible enough for charging any type of battery chemistry. These are building block ICs intended for use with an external circuit, such as a microcontroller , capable of managing the entire algorithm required for the speciﬁ c battery being charged. Each member of the L TC4009 family features a shutdown input and various state indicator outputs, allowing easy and direct management by a wide range of external (digital) charge controllers. Due to the popularity of rechargeable lithium-ion chemistries, the L TC4009-1 and L TC4009-2 also offer internal precision resistors that can be digitally selected to produce one of four preset output voltages for simpliﬁ ed design of those charger types. Shutdown The L TC4009 remains in shutdown until DCDIV exceeds 1.2V , and SHDN is driven above 1.4V . In shutdown, current drain from the battery is reduced to the lowest possible level, thereby increasing standby time. When in shutdown, the ITH pin is pulled to GND and the CHRG, ICL, FET gate drivers and INTV DD output are all disabled. The ACP status output indicates sensed adapter input voltage during all L TC4009 states. Charging can be stopped at any time by forcing SHDN below 300mV . Soft-Start Exiting the shutdown state enables the charger and releases the ITH pin. When enabled, switching will not begin until CLP exceeds BAT by 100mV and ITH exceeds a threshold that assures initial current will be positive (about 5% to 25% of the maximum programmed current). To limit inrush current, soft-start delay is created with the compensation values used on the ITH pin. Longer soft-start times can be realized by increasing the ﬁ lter capacitor on ITH, if reduced loop bandwidth is acceptable. The actual charge current at the end of soft-start will depend on which loop (current, voltage or adapter limit) is in control of the PWM. If this current is below that required by the ITH start-up threshold, the resulting charge current transient duration depends on loop compensation but is typically less than 100μs. Bulk Charge When soft-start is complete, the L TC4009 begins sourc- ing the current programmed by the external components connected to CSP, CSN and PROG. Some batteries may require a small conditioning trickle current if they are heavily discharged. As shown in the Applications Information sec- tion, the L TC4009 can address this need through a variety of low current circuit techniques on the PROG pin. Once a suitable cell voltage has been reached, charge current can be switched to a higher , bulk charge value. End-of-Charge and CHRG Output As the battery approaches the programmed output volt- age, charge current will begin to decrease. The open- drain CHRG output can indicate when the current drops to 10% of its programmed full-scale value by turning off the strong pull-down (open-drain FET) and turning on a weak 25μA pull-down current. This weak pull-down state is latched until the part enters shutdown or the sensed current rises to roughly C/6. C/10 indication will not be set if charge current has been reduced due to adapter input current limiting or DCIN/battery overvoltage. As the charge current approaches 0A, the PWM continues to operate in full continuous mode. This avoids generation of audible noise, allowing bulk ceramic capacitors to be used in the application.

accuracy speciﬁ ed in the Electrical Characteristics table. ming charge current for additional details. begin to assert control over the PWM loop. 85% of the programmed input adapter limit value. Figure 1. PWM Circuit Diagram

11 PWM

4009 F01

function of L TC4009 operation. Table 1. L TC4009 Open-Drain Indicator Outputs PWM operation references Figure 1. control voltage for one input of the PWM comparator CC. state of the RS latch at the appropriate time.

550 Repetitive, closed-loop waveforms for stable PWM opera- tion appear in Figure 2.

Figure 2. PWM Waveforms

4009 F02

As input and output conditions vary, the L TC4009 may need to utilize PWM duty cycles approaching 100%. In this case, operating frequency may be reduced well below 550kHz. An internal watchdog timer observes the activity on the TGATE pin. If TGATE is on for more than 40μs, the watchdog activates and forces the bottom NFET on (top NFET off) for about 100ns. This avoids a potential source of audible noise when using ceramic input or output capacitors and prevents the boost supply capacitor for the top gate driver from discharging. In low drop out operation, the actual charge current may not be able to reach the programmed full-scale value due to the watchdog function. Overvoltage Protection The L TC4009 also contains overvoltage detection that prevents transient battery voltage overshoots of more than about 6% above the programmed output voltage. When battery overvoltage is detected, both external MOSFETs are turned off until the overvoltage condition clears, at which time a new soft start sequence begins. This is useful for properly charging battery packs that use an internal switch to disconnect themselves for performing functions such as calibration or pulse mode charging. Reverse Charge Current Protection (Anti-Boost) Because the L TC4009 always attempts to operate synchro- nously in full continuous mode (to avoid audible noise from ceramic capacitors), reverse average charge current can occur during some invalid operating conditions. To avoid boosting a lightly loaded system supply during reverse operation, the L TC4009 monitors the voltage on CLP to determine if it rises 25mV above DCIN during charge. However , under heavier system loads, CLP may not boost above DCIN, even though reverse average current is ﬂ ow- ing. In this case a second circuit monitors indication of reverse average current on PROG. If the designer intends to replace the input diode with a MOSFET for improved efﬁ ciency, using the ACP signal of the L TC4009 to control the MOSFET is not recommended. In this case, the L TC4012 is strongly suggested, because it includes ideal diode control of the MOSFET , instead of driving it as a simple switch. This solution is the most ef- fective at detecting boost conditions and quickly shutting down the IC. If for some reason the L TC4012 solution is not acceptable, and a MOSFET with external control is used to replace the input diode, and there are conditions involving very low reverse current under no system load with an AC adapter that cannot sink current, it may still be possible to boost the DCIN input supply. To cover this case, the L TC4009 monitors the resistor divider attached to the DCDIV pin and sets an input overvoltage fault if that voltage exceeds 1.825V . If any of these circuits detects boost operation, The L TC4009 turns off both external MOSFETs until the reverse current condition clears. Once DCIN-CLP > 25mV , a new soft-start sequence begins. OPERATION

where IMAX is the desired maximum charge current ICHRG. reduction in current regulation accuracy. arbitrary number of pre-programmed current values. Figure 3. Programming 2-Level Charge Current

4009 F03

Figure 4. The value of R

of the PWM input on the gate of Q1. See Table 2 for approximate resistor values for R2. Table 2. Programming L TC4009 Output Voltage *To obtain required accuracy requires series resistors for R2. Figure 4. Programming PWM Current Figure 5. Programming L TC4009 Output Voltage

4009 F04

4009 F05

Table 3. L TC4009-1/L TC4009-2 Output Voltage Programming limit function with the following equation. some common RCL current limit programming values. CLP remains connected to power . Table 4. Common RCL Values Figure 6. Programming Input Current Limit

4009 F06

4009 F07

Figure 7. Adjusting Input Current Limit

effective at ﬁ ltering out any noise. on the value of R1. R3 should always be equal to R1. different power adapters or power sources to be used. LIM will drop to the lower set value. Figure 8. PROG Voltage Buffer

4009 F08

to satisfy other application design goals.

this, but low current indication will be lost. an external application circuit like the one shown in Figure 9. tion at start-up, the capacitor can be omitted. Figure 9. Digital C/10 Indicator Figure 10. Microprocessor Status Interface

4009 F09

4009 F10

Table 5. Digital Read Back State (IN, Figure 10)

Input and Output Capacitors In addition to typical input supply bypassing (0.1μF) on DCIN, the relatively high ESR of aluminum electrolytic capacitors is helpful for reducing ringing when hot plug- ing the charger to the AC adapter . Refer to L TC Application Note 88 for more information. The input capacitor between system power (drain of top FET , Figure 1) and GND is required to absorb all input PWM ripple current, therefore it must have adequate ripple current rating. Maximum RMS ripple current is typically one-half of the average battery charge current. Actual capacitance value is not critical, but using the highest possible voltage rating on PWM input capacitors will minimize problems. Consult with the manufacturer before use. The output capacitor shown across the battery and ground must also absorb PWM output ripple current. The general formula for this capacitor current is: I V V V LfRMS BAT BAT CLP PWM ⎠⎟02 9 1 .• •– For example, IRMS = 0.22A with: V BAT = 12.6V V CLP = 19V L1 = 10μH f PWM = 550kHz High capacity ceramic capacitors (20μF or more) available from a variety of manufacturers can be used for input/out- put capacitors. Other alternatives include OS-CON and POSCAP capacitors from Sanyo. Low ESR solid tantalum capacitors have high ripple cur- rent rating in a relatively small surface mount package, but exercise caution when using tantalum for input or output bulk capacitors. High input surge current can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger . Solid tan- talum capacitors have a known failure mechanism when subjected to very high surge currents. Select tantalum capacitors that have high surge current ratings or have been surge tested. EMI considerations usually make it desirable to minimize ripple current in battery leads. Adding Ferrite beads or inductors can increase battery impedance at the nominal 550KHz switching frequency. Switching ripple current splits between the battery and the output capacitor in inverse relation to capacitor ESR and the battery impedance. If the ESR of the output capacitor is 0.2 Ω and the battery impedance is raised to 4Ω with a ferrite bead, only 5% of the current ripple will ﬂ ow to the battery. Inductor Selection Higher switching frequency generally results in lower efﬁ ciency because of MOSFET gate charge losses, but it allows smaller inductor and capacitor values to be used. A primary effect of the inductor value L1 is the amplitude of ripple current created. The inductor ripple current ΔI L decreases with higher inductance and PWM operating frequency: ΔI V V V LfL BAT BAT CLP PWM ⎠⎟•– Accepting larger values of ΔIL allows the use of low in- ductance, but results in higher output voltage ripple and greater core losses. Lower charge currents generally call for larger inductor values. APPLICATIONS INFORMATION

L TC4009 circuits also imposes limits on ripple current. inductor value could also vary by 25% at IMAX. Table 6. Minimum Typical Inductor Values Figure 11. TGATE Boost Supply

4009 F11

where QG is the rated gate charge of the top external NFET with VGS = 4.5V . The maximum average diode current is then given by: I D = QG • 665kHz To improve efﬁ ciency by increasing VGS applied to the top FET , substitute a Schottky diode with low reverse leakage for D1. PWM jitter has been observed in some designs operating at higher V IN/VOUT ratios. This jitter does not substantially affect DC charge current accuracy. A series resistor with a value of 5Ω to 20Ω can be inserted between the cathode of D1 and the BOOST pin to remove this jitter if present. A resistor case size of 0603 or larger is recommended to lower ESL and achieve the best results. FET Selection T wo external power MOSFETs must be selected for use with the charger: an N-channel power switch (top FET) and an N-channel synchronous rectiﬁ er (bottom FET). Peak gate-to-source drive levels are internally set to about 5V . Consequently, logic-level FETs must be used. In addi- tion to the fundamental DC current, selection criteria for these MOSFETs also include channel resistance R DS(ON), total gate charge QG, reverse transfer capacitance C RSS, maximum rated drain-source voltage BVDSS and switching characteristics such as t d(ON/OFF). Power dissipation for each external FET is given by: P VI T R V kV DT O P BAT MAX DS ON CLP C ()•• +() 2 1 δΔ LLP MAX RSS DB O T CLP BAT M IC k H z P VVI 2 665•• • () = () AAX DS ON CLP TR V 2 1• ()+() δΔ where δ is the temperature dependency of R DS(ON), ΔT is the temperature rise above the point speciﬁ ed in the FET data sheet for R DS(ON) and k is a constant inversely related to the internal L TC4009 top gate driver . The term (1 + δΔT) is generally given for a MOSFET in the form of a normalized R DS(ON) curve versus temperature, but δ of 0.005/°C can be used as a suitable approximation for logic-level FETs if other data is not available. C RSS = QGD/dVDS is usually speciﬁ ed in the MOSFET character- istics. The constant k = 2 can be used in estimating top FET dissipation. The L TC4009 is designed to work best with external FET switches with a total gate charge at 5V of 15nC or less. For V CLP < 20V , high charge current efﬁ ciency generally improves with larger FETs, while for VCLP > 20V , top gate transition losses increase rapidly to the point that using a topside NFET with higher R DS(ON) but lower C RSS can actually provide higher efﬁ ciency. If the charger will be operated with a duty cycle above 85%, overall efﬁ ciency is normally improved by using a larger top FET . The synchronous (bottom) FET losses are greatest at high input voltage or during a short circuit, which forces a low side duty cycle of nearly 100%. Increasing the size of this FET lowers its losses but increases power dissipation in the L TC4009. Using asymmetrical FETs will normally achieve cost savings while allowing optimum efﬁ ciency. Select FETs with BV DSS that exceeds the maximum VCLP voltage that will occur . Both FETs are subjected to this level of stress during operation. Many logic-level MOSFETs are limited to 30V or less. APPLICATIONS INFORMATION

The L TC4009 uses an improved adaptive TGATE and BGATE drive that is insensitive to MOSFET inertial delays, t d(ON/OFF), to avoid overlap conduction losses. Switching characteristics from power MOSFET data sheets apply only to a speciﬁ c test ﬁ xture, so there is no substitute for bench evaluation of external FETs in the target application. In general, MOSFETs with lower inertial delays will yield higher efﬁ ciency. Diode Selection A Schottky diode in parallel with the bottom FET and/or top FET in an L TC4009 application clamps SW during the non-overlap times between conduction of the top and bottom FET switches. This prevents the body diode of the MOSFETs from forward biasing and storing charge, which could reduce efﬁ ciency as much as 1%. One or both diodes can be omitted if the efﬁ ciency loss can be tolerated. A 1A Schottky is generally a good size for 3A chargers due to the low duty cycle of the non-overlap times. Larger diodes can actually result in additional efﬁ ciency (transition) losses due to larger junction capacitance. Loop Compensation and Soft-Start The three separate PWM control loops of the L TC4009 can be compensated by a single set of components at- tached between the ITH pin and GND. As shown in the typical L TC4009 application, a 6.04k resistor in series with a capacitor of at least 0.1μF provides adequate loop compensation for the majority of applications. The L TC4009 can be soft-started with the compensation capacitor on the ITH pin. At start-up, ITH will quickly rise to about 0.25V , then ramp up at a rate set by the com- pensation capacitor and the 40μA ITH bias current. The full programmed charge current will be reached when ITH reaches approximately 2V . With a 0.1μF capacitor , the time to reach full charge current is usually greater than 1.5ms. This capacitor can be increased if longer start-up times are required, but loop bandwidth and dynamic response will be reduced. INTV DD Regulator Output Bypass the INTVDD regulator output to GND with a low ESR X5R or X7R ceramic capacitor with a value of 0.47μF or larger . The capacitor used to build the BOOST supply (C2 in Figure 11) can serve as this bypass. Do not draw more than 30mA from this regulator for the host system, governed by IC power dissipation. Calculating IC Power Dissipation The user should ensure that the maximum rated junction temperature is not exceeded under all operating conditions. The thermal resistance of the L TC4009 package (θ JA) is 37°C/W , provided the Exposed Pad is in good thermal contact with the PCB. The actual thermal resistance in the application will depend on forced air cooling and other heat sinking means, especially the amount of copper on the PCB to which the L TC4009 is attached. The following formula may be used to estimate the maximum average power dissipation P D (in watts) of the L TC4009, which is dependent upon the gate charge of the external MOSFETs. This gate charge, which is a function of both gate and drain voltage swings, is determined from speciﬁ cations or graphs in the manufacturer’s data sheet. For the equation below, ﬁ nd the gate charge for each transistor assuming 5V gate swing and a drain voltage swing equal to the maximum V CLP voltage. Maximum L TC4009 power dissipation under normal operating conditions is then given by: PD = DCIN(2.8mA + I DD + 665kHz(QTGATE + QBGATE)) – 5IDD where: I DD = Average external INTVDD load current, if any Q TGATE = Gate charge of external top FET in Coulombs Q BGATE = Gate charge of external bottom FET in Coulombs APPLICATIONS INFORMATION

PCB design priority list will help insure proper topology. Layout the PCB using this speciﬁ c order .

Input capacitors should be placed as close as possible
Place the L TC4009 close to the switching FET gate

side of the PCB from the switching FETs.

Place the inductor input as close as possible to the

from the switch node to any other trace or plane.

Place the charge current sense resistor immediately

that current sense traces to the L TC4009 are not long. not at the sense resistor location.

Place output capacitors adjacent to the sense resisitor
Output capacitor ground connections must feed into

ground before connecting back to system ground.

Connection of switching ground to system ground,

or any internal ground plane, should be single-point. star point to make the connection.

Route analog ground as a trace tied back to the L TC4009

GND paddle before connecting to any other ground.

A good rule of thumb for via count in a given high

Figure 12. High Speed Switching Path

4009 F12

Figure 13. Kelvin Sensing of Charge Current

4009 F13

If possible, place all the parts listed above on the same
Copper ﬁ lls or pours are good for all power connections

which further improves EMI performance.

For best current programming accuracy, provide a
It is important to minimize parasitic capacitance on

12.6V 2 Amp Charger CLP FROM ADAPTER 15V AT 2A BULK CHARGE 0.1μF R8 5.1k R14 100k D1 8 18 D3 R12 294k C10 10pF 50mΩ R9 3.01k 0.1μF 2μF 10μH R11 50mΩ 12.6V Li-Ion BATTERY DCIN CHRG 0.1μF 22.1k 2.43k R 6.04k 26.7k 53.6k L TC4009 DCDIV ACP ICL SHDN ITH PROG CLN BOOST TGATE SW INTV DD BGATETO/FROM MCU GND CSP CSN BAT FBDIV VFB 10μF POWER TO SYSTEM TO POWER SYSTEM LOAD WHEN ADAPTER IS NOT PRESENT , USE SCHOTTKY DIODE D5 OR THE COMBINATION OF R14, D6 AND Q4 18V ZENER PFET FDR858P 0.1μF 4.7nF 10μF R15 0Ω* R10 3.01k R13 31.2k

4009 TA02

D2, D4: MBR230LSFT1 D3:CMDSH-3 Q1: 2N7002 Q2, Q3: Si7212DN OR SiA914DJ OR Si4816BDY (OMIT D4) L1: IHLP-2525CZER100M11 *SEE TGATE BOOST SUPPL Y IN APPLICATIONS INFORMATION OR

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 4.00 ± 0.10 4.00 ± 0.10 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 2019 BOTTOM VIEW—EXPOSED PAD

2.00 REF

2.45 ± 0.10 0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UF20) QFN 01-07 REV A RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 2.00 REF 2.45 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 2.45 ± 0.10 2.45 ± 0.05 20-Lead Plastic QFN (4mm × 4mm) (Reference L TC DWG # 05-08-1710 Rev A)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0109 REV B • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TC1760 Smart Battery System Manager Autonomous Power Management and Battery Charging for T wo Smart Batteries, SMBus Rev 1.1 Compliant L TC1769 2A Switching Battery Charger Constant-Current/Constant-Voltage Switching Regulator , Input Current Limiting Maximizes Charge Current L TC1960 Dual Battery Charger/Selector with SPI 11-Bit V-DAC, 0.8% Voltage Accuracy, 10-Bit I-DAC, 5% Current Accuracy L TC4006 Small, High Efﬁ ciency, Fixed Voltage, Lithium-Ion Battery Chargers with Termination Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and Thermistor Sensor , 16-Pin SSOP Package L TC4007/L TC4007-1 High Efﬁ ciency, Programmable Voltage, Lithium-Ion Battery Charger with Termination Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs L TC4008/L TC4008-1 High Efﬁ ciency, Programmable Voltage/Current Battery Chargers Constant-Current/Constant-Voltage Switching Regulator , Resistor Voltage/Current Programming, Thermistor Sensor and Indicator Outputs, AC Adapter Current Limit (Omitted on 4008-1) L TC4010 High Efﬁ ciency Standalone Nickel Battery Charger Complete NiMH/NiCd Charger in a Small 16-Lead Package, Constant- Current Switching Regulator L TC4011 High Efﬁ ciency Standalone Nickel Battery Charger Complete NiMH/NiCd Charger in a Small 20-Lead Package, Constant- Current Switching Regulator , PowerPath TM Control and Indicators L TC4012/L TC4012-1 L TC4012-2 High Efﬁ ciency, Multichemistry Battery Chargers with PowerPath Control Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead Indicator Outputs L TC4060 Standalone Linear NiMH/NiCd Fast Charger Complete NiMH/NiCd Charger in a Small 16-Pin Package, No Sense Resistor or Blocking Diode Required L TC4100 Smart Battery Charger Controller Level 2 Charger Operates With or Without MCU Host, SMBus Rev 1.1 Compliant L TC4110 Battery Backup Manager Multi-Chemistry and Smart Battery Charge and Discharge Manager . Four Operating Modes: Battery Backup, Battery Charge, Battery Calibration, Shutdown. 5mm × 7mm QFN-38 Package L TC4150 Coulomb Counter/Battery Gas Gauge High Side Sense of Charge Quantity and Polarity in a 10-Pin MSOP L TC4411 2.6A Low Loss Idea Diode No External MOSFET , Automatic Switching Between DC Sources, 140mΩ On-Resistance in ThinSOT TM package L TC4412/L TC4412HV Low Loss PowerPath Controllers Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal External Complements, Operates Up to 28V (36V for HV) L TC4413 Dual 2.6A, 2.5V to 5.5V Ideal Diodes Low Loss Replacement for ORing Diodes, 100mΩ On-Resistance L TC4414 36V , Low Loss PowerPath Controller for Large PFETs Low Loss Replacement for ORing Diodes, Operates Up to 36V L TC4416 Dual Low Loss PowerPath Controllers Low Loss Replacement for ORing Diodes, Operates Up to 36V , Drives Large PFETs, Programmable, Autonomous Switching PowerPath and ThinSOT are trademarks of Linear Technology Corporation.

Selected Specification

Linear Technology LTC4009-1 overview.

Summary

High Effi ciency, Multi-Chemistry Battery Charger

Description

High Effi ciency, Multi-Chemistry Battery Charger

Source title LTC4009-1 Datasheet(PDF) - Linear Technology

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