LTC4000-1

Linear Technology

High Voltage High Current Controller for Battery Charging with Maximum Power Point Control

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Solar Panel Input Regulation, Achieves Max Power Point to Greater than 98% Typical applicaTion FeaTures DescripTion High Voltage High Current Controller for Battery Charging with Maximum Power Point Control The LT C®4000-1 is a high voltage, high performance controller that converts many externally compensated DC/DC power supplies into full-featured battery chargers with maximum power point control. In contrast to the LTC4000, the LTC4000-1 has an input voltage regulation loop instead of the input current regulation loop. Features of the LTC4000-1’s battery charger include: accurate (±0.25%) programmable float voltage, select- able timer or current termination, temperature qualified charging using an NTC thermistor, automatic recharge, C/10 trickle charge for deeply discharged cells, bad battery detection and status indicator outputs. The battery charger also includes precision current sensing that allows lower sense voltages for high current applications. The LTC4000-1 supports intelligent PowerPath control. An external PFET provides low loss reverse current protec- tion. Another external PFET provides low loss charging or discharging of the battery. This second PFET also facilitates an instant-on feature that provides immediate downstream system power even when connected to a heavily discharged or shorted battery. The LTC4000-1 is available in a low profile 28- lead 4mm × 5mm QFN and SSOP packages. 10.8V at 10A Charger for Three LiFePO4 Cells with a Solar Panel Input

applicaTions

n Maximum Power Control: Solar Panel Input Compatible n Complete High Performance Battery Charger When Paired with a DC/DC Converter n Wide Input and Output Voltage Range: 3V to 60V n Input Ideal Diode for Low Loss Reverse Blocking and Load Sharing n Output Ideal Diode for Low Loss PowerPath™ and Load Sharing with the Battery n Programmable Charge Current: ±1% Accuracy n ±0.25% Accurate Programmable Float V oltage n Programmable C/X or T imer Based Charge Termination n NTC Input for Temperature Qualified Charging n 28-Lead 4mm × 5mm QFN or SSOP Packages n Solar Powered Battery Charger Systems n Battery Charger with High Impedance Input Source, e.g., Fuel Cell or Wind T urbine n Battery Equipped Industrial or Portable Military Equipments L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. 1.13M 14.7k 127k 10k 10k 3-CELL LiFePO4 BATTERY PACK VBAT 10.8V FLOAT 10A MAX CHARGE CURRENT 1.15M 47nF 5m/uni03A9 V OUT 12V , 15ASOLAR PANEL INPUT <60V OPEN CIRCUIT VOL TAGE 17.6V PEAK POWER VOL TAGE Si7135DP 133k CSN CSP BGATE IGATE BAT OFB FBG BFB NTC CX L TC4000-1 ITH CC IID 5m/uni03A9 L T3845A 100µF OUT VC IN CLN IN IFB 22.1k TMRIIMON GND BIASCL 24.9k 1µF 332k 20k 1µF 10nF

40001 TA01a

0.1µF CHARGER OUTPUT CURRENT : IRCS (A) INPUT REGULATION VOL TAGE: VINREG (V) 5 6 7 8 9

40001 TA01b

TA = 25°C 98% TO 95% PEAK POWER 100% TO 98% PEAK POWER

0.3V to 62V to 2mA ax (VIID, VCSP) – 10V to Max (VIID, VCSP) ax (VBAT, VCSN) – 10V to Max (VBAT, VCSN) 0.3V to VBIAS 0.3V to Min (VBIAS, VCSP) 0.3V to 6V 0.3V to 62V to 2mA Operating Junction Temperature Range 5°C Lead Temperature (Soldering, 10 sec) SS 0°C 65°C to 150°C (Note 1) 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 GND 27 26 25 24 1VM RST IIMON IFB ENC IBMON CX CL IGATE OFB CSP CSN BGATE BAT BFB FBG GND IN CLN CC ITH IID TMR GND FLT CHRG BIAS NTC 8 15 TJMAX = 125°C, θJA = 43°C/W, θJC = 4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB TOP VIEW GN PACKAGE 28-LEAD PLASTIC SSOP ENC IBMON CX CL TMR GND FLT CHRG BIAS NTC FBG BFB BAT BGATE IFB IIMON RST VM GND IN CLN CC ITH IID IGATE OFB CSP CSN TJMAX = 125°C, θJA = 80°C/W, θJC = 25°C/W pin conFiguraTion orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4000EUFD-1#PBF LTC4000EUFD-1#TRPBF 40001 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC4000IUFD-1#PBF LTC4000IUFD-1#TRPBF 40001 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC4000EGN-1#PBF LTC4000EGN-1#TRPBF LTC4000GN-1 28-Lead Plastic SSOP –40°C to 125°C LTC4000IGN-1#PBF LTC4000IGN-1#TRPBF LTC4000GN-1 28-Lead Plastic SSOP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Supply Operating Range l 3 60 V IIN Input Quiescent Operating Current 0.4 mA IBAT Battery Pin Operating Current VIN ≥ 3V, VCSN = VCSP ≥ VBAT l 50 100 µA Battery Only Quiescent Current VIN = 0V, VCSN = VCSP ≤ VBAT l 10 20 μA Shutdown ENC Input Voltage Low l 0.4 V ENC Input Voltage High l 1.5 V ENC Pull-Up Current VENC = 0V –4 –2 –0.5 µA ENC Open Circuit Voltage VENC = Open l 1.5 2.5 V Voltage Regulation VIFB_REG Input Feedback Voltage l 0.985 1.000 1.010 V IFB Input Current VIFB = 1.0V ± 0.1 µA VBFB_REG Battery Feedback Voltage l 1.133 1.120 1.136 1.136 1.139 1.147 V V BFB Input Current V BFB = 1.2V ± 0.1 µA VOFB_REG Output Feedback Voltage l 1.176 1.193 1.204 V OFB Input Current VOFB = 1.2V ± 0.1 µA RFBG Ground Return Feedback Resistance l 100 400 Ω VRECHRG(RISE) Rising Recharge Battery Threshold Voltage % of V BFB_REG l 96.9 97.6 98.3 % VRECHRG(HYS) Recharge Battery Threshold Voltage Hysteresis % of V BFB_REG 0.5 % VOUT(INST_ON) Instant-On Battery Voltage Threshold % of V BFB_REG l 82 86 90 % VLOBAT Falling Low Battery Threshold Voltage % of V BFB_REG l 65 68 71 % VLOBAT(HYS) Low Battery Threshold Voltage Hysteresis % of V BFB_REG 3 % Current Monitoring and Regulation Ratio of Monitored-Current Voltage to Sense Voltage V IN,CLN ≤ 50mV, VIIMON/VIN,CLN VCSP,CSN ≤ 50mV, VIBMON/VCSP,CSN l 18.5 20 21 V/V VOS Sense Voltage Offset VCSP,CSN ≤ 50mV, VCSP = 60V or VIN,CLN ≤ 50mV, VIN = 60V (Note 4) –300 300 µV CLN, CSP, CSN Common Mode Range (Note 4) l 3 60 V CLN Pin Current ±1 µA CSP Pin Current VIGATE = Open, VIID = 0V 90 μA CSN Pin Current VBGATE = Open, VBAT = 0V 45 μA ICL Pull-Up Current for the Charge Current Limit Programming Pin l –55 –50 –45 μA ICL_TRKL Pull-Up Current for the Charge Current Limit Programming Pin in T rickle Charge Mode V BFB < VLOBAT l –5.5 –5.0 –4.5 μA Input Current Monitor Resistance to GND 40 90 140 kΩ Charge Current Monitor Resistance to GND 40 90 140 kΩ A5 Error Amp Offset for the Charge Current Loop (See Figure 1) V CL = 0.8V l –10 0 10 mV Maximum Programmable Current Limit Voltage Range l 0.985 1.0 1.015 V

elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Charge Termination CX Pin Pull-Up Current VCX = 0.1V l –5.5 –5.0 –4.5 µA VCX,IBMON(OS) CX Comparator Offset Voltage, IBMON Falling V CX = 0.1V l 0.5 10 25 mV VCX,IBMON(HYS) CX Comparator Hysteresis Voltage 5 mV TMR Pull-Up Current VTMR = 0V –5.0 μA TMR Pull-Down Current VTMR = 2V 5.0 μA TMR Pin Frequency CTMR = 0.01μF 400 500 600 Hz TMR Threshold for CX Termination l 2.1 2.5 V tT Charge Termination Time CTMR = 0.1μF l 2.3 2.9 3.5 h tT/tBB Ratio of Charge Terminate Time to Bad Battery Indicator Time CTMR = 0.1μF l 3.95 4 4.05 h/h VNTC(COLD) NTC Cold Threshold VNTC Rising, % of VBIAS l 73 75 77 % VNTC(HOT) NTC Hot Threshold VNTC Falling, % of VBIAS l 33 35 37 % VNTC(HYS) NTC Thresholds Hysteresis % of VBIAS 5 % VNTC(OPEN) NTC Open Circuit Voltage % of VBIAS l 45 50 55 % RNTC(OPEN) NTC Open Circuit Input Resistance 300 kΩ Voltage Monitoring and Open Drain Status Pins VVM(TH) VM Input Falling Threshold l 1.176 1.193 1.204 V VVM(HYS) VM Input Hysteresis 40 mV VM Input Current VVM = 1.2V ±0.1 µA IRST,CHRG,FLT(LKG) Open Drain Status Pins Leakage Current V PIN = 60V ±1 µA VRST,CHRG,FLT(VOL) Open Drain Status Pins Voltage Output Low I PIN = 1mA l 0.4 V Input PowerPath Control Input PowerPath Forward Regulation Voltage V IID,CSP, 3V ≤ VCSP ≤ 60V l 0.1 8 20 mV Input PowerPath Fast Reverse Turn-Off Threshold Voltage VIID,CSP, 3V ≤ VCSP ≤ 60V, VIGATE = VCSP – 2.5V, ∆IIGATE/∆ VIID,CSP ≥ 100μA/mV l –90 –50 –20 mV Input PowerPath Fast Forward Turn-On Threshold Voltage V IID,CSP, 3V ≤ VCSP ≤ 60V, VIGATE = VIID – 1.5V, ∆IIGATE/∆ VIID,CSP ≥ 100μA/mV l 40 80 130 mV Input Gate Turn-Off Current VIID = VCSP, VIGATE = VCSP – 1.5V –0.3 μA Input Gate Turn-On Current VCSP = VIID – 20mV, VIGATE = VIID – 1.5V 0.3 μA IIGATE(FASTOFF) Input Gate Fast Turn-Off Current VCSP = VIID + 0.1V, VIGATE = VCSP – 5V –0.5 mA IIGATE(FASTON) Input Gate Fast Turn-On Current VCSP = VIID – 0.2V, VIGATE = VIID – 1.5V 0.7 mA VIGATE(ON) Input Gate Clamp Voltage IIGATE = 2µA, VIID = 12V to 60V, VCSP = VIID – 0.5V, Measure VIID – VIGATE l 13 15 V Input Gate Off Voltage IIGATE = – 2μA, VIID = 3V to 59.5V, VCSP = VIID + 0.5V, Measure VCSP – VIGATE l 0.45 0.7 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC4000-1 is tested under conditions such that T J ≈ TA. The LTC4000E-1 is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC4000I-1 is guaranteed over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = VCLN = 3V to 60V unless otherwise noted (Notes 2, 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Battery PowerPath Control Battery Discharge PowerPath Forward Regulation Voltage VBAT,CSN, 2.8V ≤ VBAT ≤ 60V l 0.1 8 20 mV Battery PowerPath Fast Reverse Turn-Off Threshold Voltage V BAT,CSN, 2.8V ≤ VBAT ≤ 60V, Not Charging, VBGATE = VCSN – 2.5V, ∆IBGATE/∆VBAT,CSN ≥ 100μA/mV l –90 –50 –20 mV Battery PowerPath Fast Forward Turn-On Threshold Voltage V BAT,CSN, 2.8V ≤ VCSN ≤ 60V, VBGATE = VBAT – 1.5V, ∆IBGATE/∆ VBAT,CSN ≥ 100μA/mV l 40 80 130 mV Battery Gate Turn-Off Current VBGATE = VCSN – 1.5V, VCSN ≥ VBAT, VOFB < VOUT(INST_ON) and Charging in Progress, or VCSN = VBAT and Not Charging –0.3 μA Battery Gate Turn-On Current VBGATE = VBAT – 1.5V, VCSN ≥ VBAT, VOFB > VOUT(INST_ON) and Charging in Progress, or VCSN = VBAT – 20mV 0.3 μA IBGATE(FASTOFF) Battery Gate Fast Turn-Off Current VCSN = VBAT + 0.1V and Not Charging, VBGATE = VCSN – 5V –0.5 mA IBGATE(FASTON) Battery Gate Fast Turn-On Current VCSN = VBAT – 0.2V, VBGATE = VBAT – 1.5V 0.7 mA VBGATE(ON) Battery Gate Clamp Voltage IBGATE = 2μA, VBAT = 12V to 60V, VCSN = VBAT – 0.5V, Measure VBAT – VBGATE l 13 15 V Battery Gate Off Voltage IBGATE = – 2μA, VBAT = 2.8V to 59.5V, VCSN = VBAT + 0.5V and not Charging, Measure VCSN – VBGATE l 0.45 0.7 V BIAS Regulator Output and Control Pins VBIAS BIAS Output Voltage No Load l 2.4 2.9 3.5 V ∆VBIAS BIAS Output Voltage Load Regulation I BIAS = – 0.5mA –0.5 –10 % BIAS Output Short-Circuit Current VBIAS = 0V –20 mA T ransconductance of Error Amp CC = 1V 0.5 mA/V Open Loop DC Voltage Gain of Error Amp CC = Open 80 dB IITH(PULL_UP) Pull-Up Current on the ITH Pin VITH = 0V, CC = 0V –6 –5 –4 μA IITH(PULL_DOWN) Pull-Down Current on the ITH Pin VITH = 0.4V, CC = Open l 0.5 1 mA Open Loop DC Voltage Gain of ITH Driver ITH = Open 60 dB these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (T J, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the following formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. Note 3: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 4: These parameters are guaranteed by design and are not 100% tested.

Typical perForMance characTerisTics Battery Thresholds: Rising Recharge, Instant-On Regulation and Falling Low Battery As a Percentage of Battery Float Feedback Over Temperature CL Pull-Up Current Over Temperature Maximum Programmable Current Limit Voltage Over Temperature Input Quiescent Current and Battery Quiescent Current Over Temperature Battery Only Quiescent Current Over Temperature Input Voltage Regulation Feedback, Battery Float Voltage Feedback, Output Voltage Regulation Feedback and VM Falling Threshold Over Temperature TEMPERATURE (°C) –60 IBAT (µA) 100 0.1 0.01 0.001 10020

40001 G02

14040 60 80–20 0 –40 120 VBAT = 3V VBAT = 60V VBAT = 15V TEMPERATURE (°C) –60 PIN VOL TAGE (V) 1.20 1.12 1.18 1.16 1.14 1.00 1.02 1.08 1.06 1.04 1.00 10020

40001 G03

14040 60 80–20 0 –40 120 VBFB_REG VIFB_REG VVM(TH) VOFB_REG TEMPERATURE (°C) –60 VIBMON (V) 1.015 1.010 0.995 1.000 0.990 1.005 0.985 10020

40001 G06

14040 60 80–20 0 –40 120 TEMPERATURE (°C) –60 PERCENT OF VBFB_REG (%) 100 10020

40001 G04

14040 60 80–20 0 –40 120 VLOBAT VRECHRG(RISE) VOUT(INST_ON) TEMPERATURE (°C) –60 ICL (µA) –45.0 –47.5 –52.5 –50.0 –55.0 10020

40001 G05

14040 60 80–20 0 –40 120 TEMPERATURE (°C) –60 –20 –40 IIN/IBAT (mA) 1.0 0.1 80 10020 40

40001 G01

VIN = VBAT = 15V VCSN = 15.5V CX Comparator Offset Voltage with VIBMON Falling Over Temperature TEMPERATURE (°C) –60 VOS (µV) 300 200 –100 –200 100 –300 10020

40001 G07

14040 60 80–20 0 –40 120 VOS(CSP , CSN) VOS(IN, CSN) VMAX(IN,CLN) = VMAX(CSP , CSN) = 15V Current Sense Offset Voltage Over Common Mode Voltage Range Current Sense Offset Voltage Over Temperature VMAX(IN, CLN)/VMAX(CSP , CSN) (V) VOS (µV) 300 200 –100 –200 100 –300

40001 G08

VOS(CSP , CSN) VOS(IN, CSN) TEMPERATURE (°C) –60 VCX,IBMON (mV) 10020

40001 G09

14040 60 80–20 0 –40 120

Typical perForMance characTerisTics PowerPath Forward Voltage Regulation Over Temperature Charge Termination Time with 0.1µF Timer Capacitor Over Temperature NTC Thresholds Over Temperature TEMPERATURE (°C) –60 TT (h) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 10020

40001 G10

14040 60 80–20 0 –40 120 TEMPERATURE (°C) –60 PERCENT OF VBIAS (%) 10020

40001 G11

14040 60 80–20 0 –40 120 VNTC(OPEN) VNTC(HOT) VNTC(COLD) TEMPERATURE (°C) –60 VIID,CSP/VBAT ,CSN (mV) 10020

40001 G12

14040 60 80–20 0 –40 120 VIID = VBAT = 60V VIID = VBAT = 3V VIID = VBAT = 15V PowerPath Turn-Off Gate Voltage Over Temperature BIAS Voltage at 0.5mA Load Over Temperature I TH Pull-Down Current Over Temperature PowerPath Fast Off, Fast On and Forward Regulation Over Temperature PowerPath Turn-On Gate Clamp Voltage Over Temperature TEMPERATURE (°C) –60 VIID,CSP/VBAT ,CSN (mV) 120 –30 –60 –90 10020

40001 G13

14040 60 80–20 0 –40 120 VIID = VBAT = 15V TEMPERATURE (°C) –60 VIGATE (ON)/VBGATE(ON) (V) 15.0 12.5 13.5 14.5 14.0 13.0 12.0 11.5 11.0 10020

40001 G14

14040 60 80–20 0 –40 120 VIID = VBAT = 15V TEMPERATURE (°C) –60 VCSP,IGATE/VCSN,BGATE (mV) 600 350 450 550 500 400 300 250 200 10020

40001 G15

14040 60 80–20 0 –40 120 VCSP = VCSN = 15V TEMPERATURE (°C) –60 VBIAS (V) 3.2 2.8 3.0 3.1 2.9 2.7 2.6 2.5 10020

40001 G16

14040 60 80–20 0 –40 120 VIN = 60V VIN = 15V VIN = 3V TEMPERATURE (°C) –60 IITH(PULL-DOWN) (mA) 1.5 0.8 1.0 1.1 1.2 1.3 1.4 0.9 0.7 0.6 0.5 10020

40001 G17

14040 60 80–20 0 –40 120 VITH = 0.4V ITH Pull-Down Current vs VITH VITH (V) IITH(PULL-DOWN) (mA) 2.5 1.5 2.0 1.0 0.5 0.80.4

40001 G18

VM (Pin 1/Pin 25): Voltage Monitor Input. High impedance input to an accurate comparator with a 1.193V threshold (typical). This pin controls the state of the RST output pin. Connect a resistor divider (RVM1, RVM2) between the monitored voltage and GND, with the center tap point con- nected to this pin. The falling threshold of the monitored voltage is calculated as follows: VVM _RST = RVM1 + RVM2 RVM2

1.193V where RVM2 is the bottom resistor between the VM pin and GND. Tie to the BIAS pin if voltage monitoring func- tion is not used. RST (Pin 2/Pin 26): High Voltage Open Drain Reset Output. When the voltage at the VM pin is below 1.193V, this status pin is pulled low. When driven low, this pin can disable a DC/DC converter when connected to the converter’s enable pin. This pin can also drive an LED to provide a visual status indicator of a monitored voltage. Short this pin to GND when not used. IIMON (Pin 3/Pin 27): Input Current Monitor. The voltage on this pin is 20 times (typical) the sense voltage (V IN,CLN) across the input current sense resistor(R IS), therefore providing a voltage proportional to the input current. Connect an appropriate capacitor to this pin to obtain a voltage representation of the time-average input current. Leave this pin open when input current monitoring func- tion is not needed. IFB (Pin 4/Pin 28): Input Voltage Feedback Pin. This pin is a high impedance input pin used to sense the input voltage level. In regulation, the input voltage loop sets the voltage on this feedback pin to 1.000V. When the input feedback voltage drops below 1.000V, the ITH pin is pulled down to reduce the load on the input source. Connect this pin to the center node of a resistor divider between the IN pin and GND to set the input voltage regulation level. This regulation level can then be obtained as follows: VIN _REG = ROFB1 ROFB2 + 1  • 1.000V If the input voltage regulation feature is not used, connect the IFB pin to the BIAS pin. ENC (Pin 5/Pin 1): Enable Charging Pin. High impedance digital input pin. Pull this pin above 1.5V to enable charg- ing and below 0.5V to disable charging. Leaving this pin open causes the internal 2µA pull-up current to pull the pin to 2.5V (typical). IBMON (Pin 6/Pin 2): Battery Charge Current Monitor. The voltage on this pin is 20 times (typical) the sense voltage CSP,CSN) across the battery current sense resistor (RCS), therefore providing a voltage proportional to the battery charge current. Connect an appropriate capacitor to this pin to obtain a voltage representation of the time-average battery charge current. Short this pin to GND to disable charge current limit feature. CX ( Pin 7/Pin 3): Charge Current Termination Pro- gramming. Connect the charge current termination pro- gramming resistor (R CX) to this pin. This pin is a high impedance input to a comparator and sources 5μA of current. When the voltage on this pin is greater than the charge current monitor voltage (V IBMON), the CHRG pin (QFN/SSOP)

pin FuncTions (QFN/SSOP) turns high impedance indicating that the CX threshold is reached. When this occurs, the charge current is imme- diately terminated if the TMR pin is shorted to the BIAS pin, otherwise charging continues until the charge termi- nation timer expires. The charge current termination value is determined using the following formula: IC/ X = 0.25µA • RCX( )− 0.5mV RCS Where RCS is the sense resistor connected to the CSP and the CSN pins. Note that if RCX = RCL ≤ 19.1kΩ, where RCL is the charge current programming resistor, then the charge current termination value is one tenth the full charge current, more familiarly known as C/10. Short this pin to GND to disable CX termination. CL (Pin 8/Pin 4): Charge Current Limit Programming. Con- nect the charge current programming resistor (RCL) to this pin. This pin sources 50µA of current. The regulation loop compares the voltage on this pin with the charge current monitor voltage (VIBMON), and drives the ITH pin accord- ingly to ensure that the programmed charge current limit is not exceeded. The charge current limit is determined using the following formula: ICLIM = 2.5µA • RCL RCS Where RCS is the sense resistor connected to the CSP and the CSN pins. Leave the pin open for the maximum charge current limit of 50mV/RCS. TMR (Pin 9/Pin 5): Charge Timer. Attach 1nF of external capacitance (CTMR) to GND for each 104 seconds of charge termination time and 26 seconds of bad battery indicator time. Short to GND to prevent bad battery indicator time and charge termination time from expiring – allowing a continuous trickle charge and top off float voltage regula- tion charge. Short to BIAS to disable bad battery detect and enable C/X charging termination. GND (Pins 10, 28, 29/Pins 6, 24): Device Ground Pins. Connect the ground pins to a suitable PCB copper ground plane for proper electrical operation. The QFN package exposed pad must be soldered to PCB ground for rated thermal performance. FLT, CHRG (Pin 11, Pin 12/Pin 7, Pin 8): Charge Status Indicator Pins. These pins are high voltage open drain pull down pins. The FLT pin pulls down when there is an under or over temperature condition during charging or when the voltage on the BFB pin stays below the low battery threshold during charging for a period longer than the bad battery indicator time. The CHRG pin pulls down during a charging cycle. Please refer to the application informa- tion section for details on specific modes indicated by the combination of the states of these two pins. Pull up each of these pins with an LED in series with a resistor to a voltage source to provide a visual status indicator. Short these pins to GND when not used. BIAS (Pin 13/Pin 9): 2.9V Regulator Output. Connect a capacitor of at least 470nF to bypass this 2.9V regulated voltage output. Use this pin to bias the resistor divider to set up the voltage at the NTC pin.

NTC (Pin 14/Pin 10): Thermistor Input. Connect a ther- mistor from NTC to GND, and a corresponding resistor from BIAS to NTC. The voltage level on this pin determines if the battery temperature is safe for charging. The charge current and charge timer are suspended if the thermistor indicates a temperature that is unsafe for charging. Once the temperature returns to the safe region, charging resumes. Leave the pin open or connected to a capacitor to disable the temperature qualified charging function. FBG (Pin 15/Pin 11): Feedback Ground Pin. This is the ground return pin for the resistor dividers connected to the BFB and OFB pins. As soon as the voltage at IN is valid (>3V typical), this pin has a 100Ω resistance to GND. When the voltage at IN is not valid, this pin is disconnected from GND to ensure that the resistor dividers connected to the BFB and OFB pins do not continue to drain the battery when the battery is the only available power source. BFB (Pin 16/Pin 12): Battery Feedback Voltage Pin. This pin is a high impedance input pin used to sense the battery voltage level. In regulation, the battery float voltage loop sets the voltage on this pin to 1.136V (typical). Connect this pin to the center node of a resistor divider between the BAT pin and the FBG pin to set the battery float voltage. The battery float voltage can then be obtained as follows: VFLOAT = RBFB2 + RBFB1 RBFB2

1.136V BAT (Pin 17/Pin 13): Battery Pack Connection. Connect the battery to this pin. This pin is the anode of the battery ideal diode driver (the cathode is the CSN pin). BGATE (Pin 18/Pin 14): External Battery PMOS Gate Drive Output. When not charging, the BGATE pin drives the external PMOS to behave as an ideal diode from the BAT pin (anode) to the CSN pin (cathode). This allows efficient delivery of any required additional power from the battery to the downstream system connected to the CSN pin. When charging a heavily discharged battery, the BGATE pin is regulated to set the output feedback voltage (OFB pin) to 86% of the battery float voltage (0.974V typical). This allows the instant-on feature, providing an immediate valid voltage level at the output when the LTC4000-1 is charging a heavily discharged battery. Once the voltage on the OFB pin is above the 0.974V typical value, then the BGATE pin is driven low to ensure an efficient charging path from the CSN pin to the BAT pin. CSN (Pin 19/Pin 15): Charge Current Sense Negative Input and Battery Ideal Diode Cathode. Connect a sense resistor between this pin and the CSP pin. The LTC4000-1 senses the voltage across this sense resistor and regulates it to a voltage equal to 1/20th (typical) of the voltage set at the CL pin. The maximum regulated sense voltage is 50mV. The CSN pin is also the cathode input of the battery ideal diode driver (the anode input is the BAT pin). Tie this pin to the CSP pin if no charge current limit is desired. Refer to the Applications Information section for complete details. CSP (Pin 20/Pin 16): Charge Current Sense Positive Input and Input Ideal Diode Cathode. Connect a sense resis- tor between this pin and the CSN pin for charge current sensing and regulation. This input should be tied to CSN to disable the charge current regulation function. This pin is also the cathode of the input ideal diode driver (the anode is the IID pin). pin FuncTions (QFN/SSOP)

pin FuncTions (QFN/SSOP) OFB (Pin 21/Pin 17): Output Feedback Voltage Pin. This pin is a high impedance input pin used to sense the output voltage level. In regulation, the output voltage loop sets the voltage on this feedback pin to 1.193V. Connect this pin to the center node of a resistor divider between the CSP pin and the FBG pin to set the output voltage when battery charging is terminated and all the output load current is provided from the input. The output voltage can then be obtained as follows: VOUT = ROFB2 + ROFB1 ROFB2

1.193V When charging a heavily discharged battery (such that VOFB < VOUT(INST_ON)), the battery PowerPath PMOS connected to BGATE is regulated to set the voltage on this feedback pin to 0.974V (approximately 86% of the battery float voltage). The instant-on output voltage is then as follows: VOUT(INST _ ON) = ROFB2 + ROFB1 ROFB2
0.974V IGATE (Pin 22/Pin 18): Input PMOS Gate Drive Output. The IGATE pin drives the external PMOS to behave as an ideal diode from the IID pin (anode) to the CSP pin (cathode). IID (Pin 23/Pin 19): Input Ideal Diode Anode. This pin is the anode of the input ideal diode driver (the cathode is the CSP pin). ITH (Pin 24/Pin 20): High Impedance Control Voltage Pin. When any of the regulation loops (input voltage, charge current, battery float voltage or the output voltage) indicate that its limit is reached, the ITH pin will sink current (up to 1mA) to regulate that particular loop at the limit. In many applications, this ITH pin is connected to the control/ compensation node of a DC/DC converter. Without any external pull-up, the operating voltage range on this pin is GND to 2.5V. With an external pull-up, the voltage on this pin can be pulled up to 6V. Note that the impedance connected to this pin affects the overall loop gain. For details, refer to the Applications Information section. CC (Pin 25/Pin 21): Converter Compensation Pin. Connect an R-C network from this pin to the ITH pin to provide a suitable loop compensation for the converter used. Refer to the Applications Information section for discussion and procedure on choosing an appropriate R-C network for a particular DC/DC converter. CLN (Pin 26/Pin 22): Input Current Sense Negative Input. Connect a sense resistor between this pin and the IN pin. The LTC4000-1 senses the voltage across this sense resistor and sets the voltage on the IIMON pin equal to 20 times this voltage. Tie this pin to the IN pin if the input current monitoring feature is not used. Refer to the Applications Information section for complete details. IN (Pin 27/Pin 23): Input Supply Voltage: 3V to 60V. Supplies power to the internal circuitry and the BIAS pin. Connect the power source to the downstream system and the battery charger to this pin. This pin is also the positive sense pin for the input current monitor. Connect a sense resistor between this pin and the CLN pin. Tie this pin to CLN if the input current monitoring feature is not used. A local 0.1µF bypass capacitor to ground is recommended on this pin.

Figure 1. LTC4000-1 Functional Block Diagram

The LTC4000-1 is designed to simplify the conversion of any externally compensated DC/DC converter into a high performance battery charger with PowerPath control. It only requires the DC/DC converter to have a control or external-compensation pin (usually named VC or ITH) whose voltage level varies in a positive monotonic way with its output. The output variable can be either output voltage or output current. For the following discussion, refer to the Block Diagram in Figure 1. The LTC4000-1 includes four different regulation loops: input voltage, charge current, battery float voltage and output voltage (A4-A7). Whichever loop requires the low- est voltage on the ITH pin for its regulation controls the external DC/DC converter. The input voltage regulation loop ensures that the input voltage level does not drop below the programmed level. The charge current regulation loop ensures that the pro- grammed battery charge current limit (using a resistor at CL) is not exceeded. The float voltage regulation loop ensures that the programmed battery stack voltage (us- ing a resistor divider from BAT to FBG via BFB) is not exceeded. The output voltage regulation loop ensures that the programmed system output voltage (using a resistor divider from CSP to FBG via OFB) is not exceeded. The LTC4000-1 also provides monitoring pins for the input current and charge current at the IIMON and IBMON pins respectively. The LTC4000-1 features an ideal diode controller at the input from the IID pin to the CSP pin and a PowerPath controller at the output from the BAT pin to the CSN pin. The output PowerPath controller behaves as an ideal diode controller when not charging. When charging, the output PowerPath controller has two modes of operation. If V OFB is greater than VOUT(INST_ON), BGATE is driven low. When VOFB is less than VOUT(INST_ON), a linear regulator implements the instant-on feature. This feature provides regulation of the BGATE pin so that a valid voltage level is immediately available at the output when the LTC4000-1 is charging an over-discharged, dead or short faulted battery. The state of the ENC pin determines whether charging is enabled. When ENC is grounded, charging is disabled and the battery float voltage loop is disabled. Charging is enabled when the ENC pin is left floating or pulled high (≥1.5V) The LTC4000-1 offers several user configurable battery charge termination schemes. The TMR pin can be config- ured for either C/X termination, charge timer termination or no termination. After a particular charge cycle terminates, the LTC4000-1 features an automatic recharge cycle if the battery voltage drops below 97.6% of the programmed float voltage. T rickle charge mode drops the charge current to one tenth of the normal charge current (programmed using a resistor from the CL pin to GND) when charging into an over discharged or dead battery. When trickle charging, a capacitor on the TMR pin can be used to program a time out period. When this bad battery timer expires and the battery voltage fails to charge above the low battery threshold (V LOBAT), the LTC4000-1 will terminate charging and indicate a bad battery condition through the status pins (FLT and CHRG). The LTC4000-1 also includes an NTC pin, which provides temperature qualified charging when connected to an NTC thermistor thermally coupled to the battery pack. To enable this feature, connect the thermistor between the NTC and the GND pins, and a corresponding resistor from the BIAS pin to the NTC pin. The LTC4000-1 also provides a charg- ing status indicator through the FLT and the CHRG pins. Aside from biasing the thermistor-resistor network, the BIAS pin can also be used for a convenient pull up voltage. This pin is the output of a low dropout voltage regulator that is capable of providing up to 0.5mA of current. The regulated voltage on the BIAS pin is available as soon as the IN pin is within its operating range (≥3V). Input Ideal Diode The input ideal diode feature provides low loss conduction and reverse blocking from the IID pin to the CSP pin. This reverse blocking prevents reverse current from the output (CSP pin) to the input (IID pin) which causes unneces- sary drain on the battery and in some cases may result in unexpected DC/DC converter behavior. The ideal diode behavior is achieved by controlling an external PMOS connected to the IID pin (drain) and the

behaves like a fixed value resistor (RDS(ON)). input voltage from dropping below the programmed level. current is set with a resistor on the CL pin. loads are light, battery charge current is maximized. constant voltage charging, charge current slowly declines. is started at the beginning of constant voltage charging. Charging terminates when the termination timer expires. tie the TMR pin to GND to disable termination. ensure that the output voltage at CSP remains in control. Figure 2. Input Voltage Regulation Loop

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does not drop below this programmed level.

initiates a new charge cycle. (RCS) does not exceed the programmed full charge current. output feedback voltage at the OFB pin is 1.193V. Figure 3. Charge Current Regulation Loop Figure 4. Battery Float Voltage Regulation Loop with FBG Figure 5. Output V

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40001 FO4

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the typical resistance from the FBG pin to GND is 100Ω. voltage drop from the BAT pin to the CSN pin is 8mV. behaves like a fixed value resistor (RDS(ON)).

pin to the BAT pin during charging. at the output (CSP pin), independent of the battery voltage. then the LTC4000-1 pauses any charge cycle in progress. 40% to 70% of VBIAS, charging resumes. chip functionality is enabled. Figure 6. Input Voltage Monitoring with RST Connected to

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different requirements are shown at Table 1. Table 1. PMOS is delivered through the body diode of the external PMOS. this momentary increase in power dissipation. putting a capacitor on the pin (CIIMON).

2.5µA The charge current through the sense resistor is available for monitoring through the IBMON pin. The voltage on the IBMON pin varies with the current through the sense resistor as follows: VIBMON = 20 •IRCS • RCS = 20 • VCSP – VCSN( ) The regulation voltage level at the IBMON pin is clamped at 1V with an accurate internal reference. At 1V on the IBMON pin, the charge current limit is regulated to the following value: ICLIM(MAX) (A) = 0.050V RCS(Ω ) When this maximum charge current limit is desired, leave the CL pin open or set it to a voltage >1.05V such that amplifier A5 can regulate the IBMON pin voltage accurately to the internal reference of 1V. When the output current waveform of the DC/DC converter or the system load current is noisy, it is recommended that

a capacitor is connected to the CSP pin (CCSP). This is to reduce the AC content of the current through the sense resistor (RCS). Where the highest accuracy is important, pick the value of C CSP such that the AC content is less than or equal to 50% of the average voltage across the sense resistor. Similar to the IIMON pin, the voltage on the IBMON pin is filtered further by putting a capacitor on the pin (CIBMON). This filter capacitor should not be arbitrarily large as it will slow down the overall compensated charge current regulation loop. For details on the loop compensa- tion, refer to the Compensation section. Battery Float Voltage Programming When the value of RBFB1 is much larger than 100Ω, the final float voltage is determined using the following formula: RBFB1 = VFLOAT 1.136V –1   RBFB2 When higher accuracy is important, a slightly more ac- curate final float voltage can be determined using the following formula: VFLOAT = RBFB1 + RBFB2 RBFB2

1.136V  – RBFB1 RBFB2
VFBG where V FBG is the voltage at the FBG pin during float voltage regulation, which accounts for all the current from all resistor dividers that are connected to this pin (RFBG = 100Ω typical). Low Battery T rickle Charge Programming and Bad Battery Detection When charging into an over-discharged or dead battery (VBFB < VLOBAT), the pull-up current at the CL pin is reduced to 10% of the normal pull-up current. Therefore, the trickle charge current is set using the following formula: RCL = ICLIM(TRKL) • RCS 0.25µA ⇒ ICLIM(TRKL) = 0.25µA • RCL RCS applicaTions inForMaTion Therefore, when 50µA•RCL is less than 1V, the following relation is true: ICLIM(TRKL) = ICLIM Once the battery voltage rises above the low battery voltage threshold, the charge current level rises from the trickle charge current level to the full charge current level. The LTC4000-1 also features bad battery detection. This detection is disabled if the TMR pin is grounded or tied to BIAS. However, when a capacitor is connected to the TMR pin, a bad battery detection timer is started as soon as trickle charging starts. If at the end of the bad battery detection time the battery voltage is still lower than the low battery threshold, charging is terminated and the part indicates a bad battery condition by pulling the FLT pin low and leaving the CHRG pin high impedance. The bad battery detection time can be programmed ac- cording to the following formula: CTMR (nF) = tBADBAT (h)• 138.5 Note that once a bad battery condition is detected, the condition is latched. In order to re-enable charging, re- move the battery and connect a new battery whose voltage causes BFB to rise above the recharge battery threshold (VRECHRG(RISE)). Alternatively toggle the ENC pin or remove and reapply power to IN. C/X Detection, Charge Termination and Automatic Recharge Once the constant voltage charging is reached, there are two ways in which charging can terminate. If the TMR pin is tied to BIAS, the battery charger terminates as soon as the charge current drops to the level programmed by the CX pin. The C/X current termination level is programmed according to the following formula: RCX = IC/ X • RCS 0.25µA + 0.5mV ⇒ IC/X = 0.25µA • RCX( )− 0.5mV RCS

where RCS is the charge current sense resistor connected between the CSP and the CSN pins. When the voltage at BFB is higher than the recharge threshold (97.6% of float), the C/X comparator is enabled. In order to ensure proper C/X termination coming out of a paused charging condition, connect a capacitor on the CX pin according to the following formula: CCX = 100CBGATE where CBGATE is the total capacitance connected to the BGATE pin. For example, a typical capacitance of 1nF requires a capaci- tor greater than 100nF connected to the CX pin to ensure proper C/X termination behavior. If a capacitor is connected to the TMR pin, as soon as the constant voltage charging is achieved, a charge termina- tion timer is started. When the charge termination timer expires, the charge cycle terminates. The total charge termination time can be programmed according to the following formula: CTMR (nF) = tTERMINATE (h)• 34.6 If the TMR pin is grounded, charging never terminates and the battery voltage is held at the float voltage. Note that regardless of which termination behavior is selected, the CHRG and FLT pins will both assume a high impedance state as soon as the charge current falls below the pro- grammed C/X level. After the charger terminates, the LTC4000-1 automatically restarts another charge cycle if the battery feedback voltage drops below 97.1% of the programmed final float voltage (VRECHRG(FALL)). When charging restarts, the CHRG pin pulls low and the FLT pin remains high impedance. Output Voltage Regulation Programming The output voltage regulation level is determined using the following formula: ROFB1 = VOUT 1.193 − 1  • R OFB2 As in the battery float voltage calculation, when higher accuracy is important, a slightly more accurate output is determined using the following formula: VOUT = ROFB1 + ROFB2 ROFB2

1.193V  – R OFB1 ROFB2
VFBG where VFBG is the voltage at the FBG pin during output voltage regulation, which accounts for all the current from all resistor dividers that are connected to this pin. Battery Instant-On and Ideal Diode External PMOS Consideration The instant-on voltage level is determined using the fol- lowing formula: VOUT(INST _ ON) = ROFB1 + ROFB2 ROFB2
0.974V Note that R OFB1 and R OFB2 are the same resistors that program the output voltage regulation level. Therefore, the output voltage regulation level is always 122.5% of the instant-on voltage level. During instant-on operation, it is critical to consider the charging PMOS power dissipation. When the battery volt- age is below the low battery threshold (V LOBAT), the power dissipation in the PMOS can be calculated as follows: PTRKL = 0.86 • VFLOAT – VBAT[ ]•ICLIM(TRKL) where ICLIM(TRKL) is the trickle charge current limit. On the other hand, when the battery voltage is above the low battery threshold but still below the instant-on thresh- old, the power dissipation can be calculated as follows: PINST _ ON = 0.86 • VFLOAT – VBAT[ ]• ICLIM where ICLIM is the full scale charge current limit. For example, when charging a 3-cell Lithium Ion battery with a programmed full charged current of 1A, the float voltage is 12.6V, the bad battery voltage level is 8.55V and the instant-on voltage level is 10.8V. During instant-on operation and in the trickle charge mode, the worst case

then the worst case maximum power dissipation is 2.25W. ing whenever the external PMOS temperature is too high. function is shown in Figure 7. point depending on the application. Figure 7. Charging PMOS Overtemperature Detection Circuit

1.136V VOUT = ROFB1 + ROFB2 ROFB2
1.193V VOUT(INST _ ON) = ROFB1 + ROFB2 ROFB2
0.974V In the typical application, VOUT is set higher than VFLOAT to ensure that the battery is charged fully to its intended float voltage. On the other hand, V OUT should not be programmed too high since VOUT(INST_ON), the minimum voltage on CSP, depends on the same resistors ROFB1 and ROFB2 that set VOUT. As noted before, this means that the output voltage regulation level is always 122.5% of the instant-on voltage. The higher the programmed value of VOUT(INST_ON), the larger the operating region when the charger PMOS is driven in the linear region where it is less efficient. If ROFB1 and ROFB2 are set to be equal to RBFB1 and RBFB2 respectively, then the output voltage is set at 105% of the float voltage and the instant-on voltage is set at 86% of the float voltage. Figure 8 shows the range of possible Li-Ion BATTERY PACK RCS RNTC1 TO SYSTEM RISING TEMPERATURE THRESHOLD SET AT 90°C VISHAY CURVE 2 NTC RESISTOR THERMALL Y COUPLED WITH CHARGING PMOS VOL TAGE HYSTERESIS CAN BE PROGRAMMED FOR TEMPERATURE HYSTERESIS 86mV ≈ 10°C CSN BGATE BAT CSP BIAS NTC L TC4000-1 162k 20k R4 = RNTC2 AT 25°C

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Figure 8. Possible Voltage Ranges for VOUT and VOUT(INST_ON) in Ideal Scenario

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charged in an ideal scenario. value at that corresponding temperature. Figure 9. NTC Thermistor Connection

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to prevent oscillation about the trip point. above to set either the cold or hot threshold but not both.

if the user finds that a negative value is needed for R D, the two temperature thresholds selected are too close to each other and a higher sensitivity thermistor is needed. For example, this method can be used to set the hot and cold thresholds independently to 60°C and –5°C. Using a Vishay Curve 2 thermistor whose nominal value at 25°C is 100k, the formula results in R3 = 130k and RD = 41.2k for the closest 1% resistors values. To increase thermal sensitivity such that the valid charging temperature band is much smaller than 40°C, it is pos- sible to put a PTC (positive thermal coefficient) resistor in series with R3 between the BIAS pin and the NTC pin. This PTC resistor also needs to be thermally coupled with the battery. Note that this method increases the number of thermal sensing connections to the battery pack from one wire to three wires. The exact value of the nominal PTC resistor required can be calculated using a similar method as described above, keeping in mind that the threshold at the NTC pin is always 75% and 35% of VBIAS. Leaving the NTC pin floating or connecting it to a capacitor disables all NTC functionality. Battery V oltage Temperature Compensation Some battery chemistries have charge voltage require- ments that vary with temperature. Lead-acid batteries in particular experience a significant change in charge volt- age requirements as temperature changes. For example, manufacturers of large lead-acid batteries recommend a float charge of 2.25V/cell at 25°C. This battery float voltage, however, has a temperature coefficient which is typically specified at –3.3mV/°C per cell. The LTC4000-1 employs a resistor feedback network to program the battery float voltage. manipulation of this network makes for an efficient implementation of vari- ous temperature compensation schemes of battery float voltage. A simple solution for tracking such a linear voltage de- pendence on temperature is to use the LM234 3-terminal temperature sensor. This creates an easily programmable linear temperature dependent characteristic. equal to 0.179 • R NTC at cold_threshold. Similarly, if the value of R3 is set to adjust the hot threshold, the value of the NTC resistor at the cold threshold is then equal to 5.571 • RNTC at cold_threshold. Note that changing the value of R3 to be larger than R25 will move both the hot and cold threshold lower and vice versa. For example, using a Vishay Curve 2 thermistor whose nominal value at 25°C is 100k, the user can set the cold temperature to be at 5°C by setting the value of R3 = 75k, which automatically then sets the hot threshold at approximately 50°C. It is possible to adjust the hot and cold threshold indepen- dently by introducing another resistor as a second degree of freedom (Figure 10). The resistor R D in effect reduces the sensitivity of the resistance between the NTC pin and ground. Therefore, intuitively this resistor will move the hot threshold to a hotter temperature and the cold threshold to a colder temperature.Figure 10. NTC Thermistor Connection with Desensitizing Resistor RD NTC RESISTOR THERMALL Y COUPLED WITH BATTERY PACK RNTC NTC BIAS BAT L TC4000-1 RD

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The value of R3 and RD can now be set according to the following formula: R3 = RNTC at cold_ threshold – RNTC at hot _ threshold 2.461 RD = 0.219 • RNTC at cold_ threshold – 1.219 • RNTC at hot _ threshold Note the important caveat that this method can only be used to desensitize the thermal effect on the thermistor and hence push the hot and cold temperature thresholds apart from each other. When using the formulas above,

is the desired battery float voltage at 25°C in V. Figure 13. Li-Ion Typical Charging Cycle

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Figure 12. Battery Voltage Temperature Compensation Circuit Figure 11. Lead-Acid 6-Cell Float Charge Voltage vs

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Table 2. Lithium Based Battery Charging Steps

is called 3-step charging (Bulk, Absorption and Float). in a typical 3-step charging of a lead-acid battery. Figure 14. Lead-Acid 3-Step Charging Cycle Figure 15. 3-Step Lead-Acid Circuit Configuration

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tery at a constant voltage at this absorption voltage level. Table 3. Lead-Acid Battery Charging Steps this 3-step lead-acid battery charging with the LTC4000-1.

reinitiated starting with the bulk charge. resistor (RCS) always at 50mV. Table 4. FLT and CHRG Status Indicator a low impedance pull-down state. the indicator pins indicate that VIBMON < (VCX – 10mV). at least 470nF of low ESR bypass capacitance for stability. conveniently connected to the BIAS pin. rising threshold voltage level can be calculated similarly. ables programming of a minimum input supply voltage. divider can be combined (see Figure 16).

VIN_REG to VVM_RST has to be greater than 0.838. the input regulation loop from functioning as expected. typical panel straight forward.

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Figure 16. Input Voltage Monitoring and Input Voltage Figure 17. Temperature Characteristic of a Solar

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VMP(25°C) = maximum power point voltage at 25°C in V. is 1mA at 0.4V with a maximum voltage range of 0V to 6V. sources as much current as possible from its ITH/VC pin. output voltage regulation level programmed at the OFB pin. (RC) between the CC pin and the ITH pin is shown here. sheet for the analytic description of the other three loops. compensation, as described here, is more practical. Figure 18. Maximum Power Point Voltage Temperature

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Figure 19. Error Amplifier Followed by Output Amplifier Driving

selected values of RC and CC for all operating conditions. the output capacitor or the RDS(ON) of the external PFETs. a 50Ω/1000µF series RC network to the regulator output. the settling waveform with no distortion. Figure 20. Empirical Loop Compensation Setup

40001 F20

channel A indicates a ground loop problem. damping and allow the value of CC to be further reduced. allow one to quickly find optimum values. the over damped starting condition for further iteration. input ripple voltage and output load transients. to maximum while observing the settling waveform. adequate stability at all temperatures. Figure 21. Typical Output T ransient Response at Various

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and is repeated here in Figure 22.

With RIFB2 set at 20k, the input voltage monitoring falling threshold is set at 15V and the input voltage regulation level is set at 17.6V according to the following formulas: RVM3 = 1− 1.193V 15V   17.6V    20kΩ = 324kΩ RVM4 = 1.193V 17.6V 15V    − 1  20kΩ = 8.06kΩ
The input current sense resistor is set at 5mΩ. There- fore, the voltage at the IIMON pin is related to the input current according to the following formula: VIIMON = (0.1Ω) • IRIS
RCL is set at 24.9kΩ such that the voltage at the CL pin is 1.25V. Similar to the IIMON pin, the regulation voltage on the IBMON pin is clamped at 1V with an accurate internal reference. Therefore, the charge current limit is set at 10A according to the following formula: ICLIM(MAX) = 0.050V RCS = 0.050V 5mΩ = 10A
The trickle charge current level is consequently set at 1.25A, according to the following formula: ICLIM(TRKL) = 0.25µA • 24.9kΩ 5mΩ = 1.25A
The battery float voltage is set at 10.8V according to the following formula: RBFB1 = 10.8 1.136 − 1

Figure 22. 10.8V at 10A Charger for Three LiFePO4 Cells with Solar Panel Input

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Figure 23. Charge Current Regulation Loop Compensation Setup

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The bad battery detection time is set at 43 minutes according to the following formula: CTMR (nF) = tBADBAT (h)• 138.5 = 43
138.5 = 100nF
The charge termination time is set at 2.9 hours accord- ing to the following formula: CTMR (nF) = tTERMINATE (h)• 34.6 = 2.9 • 34.6 = 100nF
The C/X current termination level is programmed at 1A according to the following formula: RCX = 1A • 5mΩ( ) + 0.5mV 0.25µA ≈ 22.1kΩ Note that in this particular solution, the timer termina- tion is selected since a capacitor connects to the TMR pin. Therefore, this C/X current termination level only applies to the CHRG indicator pin.
The output voltage regulation level is set at 12V accord- ing to the following formula: ROFB1 = 12 1.193 − 1  • 127kΩ ≈ 1.15MΩ
The instant -on voltage level is consequently set at 9.79V according to the following formula: VINST _ ON = 1150kΩ + 127kΩ 127kΩ
0.974V = 9.79V The worst-case power dissipation during instant-on operation can be calculated as follows:
During trickle charging: PTRKL = 0.86 • VFLOAT – VBAT[ ]•ICLIM _ TRKL = 9.3W
And beyond trickle charging: PINST _ ON = 0.86 • VFLOAT – VBAT[ ]•ICLIM = 19.3W Therefore, depending on the layout and heat sink avail- able to the charging PMOS, the suggested PMOS over temperature detection circuit included in Figure 7 may need to be included.
The range of valid temperature for charging is set at –1.5°C to 41.5°C by picking a 10k Vishay Curve 2 NTC thermistor that is thermally coupled to the battery, and connecting this in series with a regular 10k resistor to the BIAS pin.
For compensation, the procedure described in the empirical loop compensation section is followed. As recommended, first a 1µF CC and 10k RC is used, which sets all the loops to be stable. For an example of typical transient responses, the charge current regulation loop when VOFB is regulated to VOUT(INST_ON) is used here. Figure 23 shows the recommended setup to inject a DC-coupled charge current variation into this particular loop. The input to the CL pin is a square wave at 70Hz with the low level set at 120mV and the high level set at 130mV, corresponding to a 1.2A and 1.3A charge current (100mA charge current step). Therefore, in this particular example the trickle charge current regulation stability is examined. Note that the nominal trickle charge current in this example is programmed at 1.25A (RCL = 24.9kΩ). applicaTions inForMaTion

step observed at IBMON is shown in Figure 24. with CC = 22nF and RC = 20k is shown in Figure 26. Figure 24. Transient Response of Charge Current Regulation Loop

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with CC = 22nF and RC = 10k is shown in Figure 25. Figure 25. Transient Response of Charge Current Regulation Loop Figure 26. Transient Response of Charge Current Regulation Loop

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values are found to be CC = 22nF and RC = 20kΩ. response is checked at these different setup conditions. obtained, the values of RC and CC are noted.

the charge current regulation when VOFB > VOUT(INST_ON). sense resistors as mentioned in the applications section. well as from CBIAS to the BIAS and GND pins. sible and away from noisy sections of the board. Figure 27. Kelvin Sense Lines Configuration for LTC4000-1

40001 F27

with the ITH pin open circuit.

CC = A V10 • RO4-7 • CC is much larger than any other poles or zeroes in the system. Typically AV10 • RO4-7 = 5 • 1010 with the ITH pin open circuit. The exact value of gm10 and RO10 depends on the pull-up current and impedance connected to the ITH pin respectively. In most applications, compensation of the loops involves picking the right values of R C and CC. Aside from picking the values of R C and CC, the value of g m10 may also be adjusted. The value of g m10 can be adjusted higher by increasing the pull-up current into the ITH pin and its value can be approximated as: gm10 = IITH + 5µA 50mV The higher the value of gm10, the smaller the lower limit of the value of RC would be. This lower limit is to prevent the presence of the right half plane zero. Even though all the loops share this transfer function from the error amplifier input to the ITH pin, each of the loops has a slightly different dynamic due to differences in the feedback signal path. The Input Voltage Regulation Loop The feedback signal for the input voltage regulation loop is the voltage on the IFB pin, which is connected to the center node of the resistor divider between the input voltage (connected to the IN pin) and GND. This voltage is compared to an internal reference (1.000V typical) by the transconductance error amplifier A4. This amplifier then drives the output transconductance amplifier (A10) to appropriately adjust the voltage on the ITH pin driving the external DC/DC converter to regulate the output volt- age observed by the IFB pin. This loop is shown in detail in Figure 28. Assuming R IS << R IN << (R IFB1 + R IFB2), the simplified loop transmission is as follows: LIV (s) = gm4 RC – 1 gm10 CCs + 1 CCs
Gmi p(s)• RIN RIN CIN + CCLN( ) s + 1  • RIFB2 RIFB where Gmip(s) is the transfer function from V ITH to the input current of the external DC/DC converter, RIN is the equivalent output impedance of the input source, and RIFB = RIFB1 + RIFB2.

Figure 28. Simplified Linear Model of the Input Voltage

40001 F28

40001 F29

Figure 29. Solar Panel Input, 6-Cell Lead-Acid, 3-Step Battery Charger with 3.3A Bulk Charge Current, 14.1V at 25°C Absorption Voltage and 13.5V at

Figure 30. 21V at 5A Boost Converter 5-Cell Li-Ion Battery Charger for High Impedance Input Sources

40001 F30

Figure 31. 18V to 72VIN to 4.2V at 2.0A Isolated Flyback Single-Cell Li-Ion Battery Charger

40001 F31

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .386 – .393* (9.804 – 9.982) GN28 REV B 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 20 21 22 23 24 25 26 27 2819 18 17 13 14 1615 .016 – .050 (0.406 – 1.270) .015 ±.004 (0.38 ±0.10) × 45° 0° – 8° TYP.0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .033 (0.838) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 BSC.0165 ±.0015 .045 ±.005 * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B)

Figure 32. Solar Panel Input 6V to 36VIN to 14.4V at 4.5A Buck Boost Converter 4-Cell LiFePO4

40001 F32

Selected Specification

Linear Technology LTC4000-1 overview.

Summary

High Voltage High Current Controller for Battery Charging with Maximum Power Point Control

Description

High Voltage High Current Controller for Battery Charging with Maximum Power Point Control

Source title LTC4000-1 Datasheet(PDF) - Linear Technology

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