LTC4300A-1 LINER
Document overview
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Technical content
®4300A series hot swappable 2-wire bus buffers allow I/O card insertion into a live backplane without corruption of the data and clock busses. When the con- nection is made, the LTC4300A-1/LTC4300A-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. Rise-time accelerator circuitry* allows the use of weaker DC pull-up currents while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances. The LTC4300A-1 incorporates a CMOS threshold digital ENABLE input pin, which forces the part into a low current mode when driven to ground and sets normal operation when driven to VCC. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. The LTC4300A-2 replaces the ENABLE pin with a dedicated supply voltage pin, VCC2, for the card side, providing level shifting between 3.3V and 5V systems. Both the backplane and card may be powered with supply voltages ranging from 2.7V to 5.5V, with no contraints on which supply voltage is higher. The LTC4300A-2 also re- places the READY pin with a digital CMOS input pin, ACC, which enables and disables the rise-time accelerator currents. The LTC4300A is available in a small 8-pin MSOP package. I Hot Board Insertion I Servers I Capacitance Buffer/Bus Extender I Desktop Computer , LTC and LT are registered trademarks of Linear Technology Corporation. I Bidirectional Buffer for SDA and SCL Lines Increases Fanout I Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane I Isolates Input SDA and SCL Lines from Output I Compatible with I2C TM, I2C Fast Mode and SMBus Standards (Up to 400kHz Operation) I Small MSOP 8-Pin Package I Low ICC Chip Disable: <1µA (LTC4300A-1) I READY Open Drain Output (LTC4300A-1) I 1V Precharge on all SDA and SCL Lines I Supports Clock Stretching, Arbitration and Synchronization I 5V to 3.3V Level Translation (LTC4300A-2) I High Impedance SDA, SCL Pins for VCC = 0V Hot Swappable 2-Wire Bus Buffers I2C is a trademark of Philips Electronics N. V. *U.S. Patent No. 6,650,174 10k VCC 3.3V 10k ENABLE SCLIN SCLOUT SDAIN SDAOUT GND LTC4300A-1 READY 0.01µF 4300A-1/2 TA01 10k 10k APPLICATIO S U
FEATURES
U DESCRIPTIO U Input–Output Connection tPLH OUTPUT SIDE 50pF INPUT SIDE 150pF 4300A TA02
Operating Temperature Range ORDER PART NUMBER MS8 PART MARKING TJMAX = 125°C, θJA = 200°C/W Consult LTC marketing for parts specified with wider operating temperature ranges. LTABF LTABG LTACF LTACG LTC4300A-1CMS8 LTC4300A-1IMS8 LTC4300A-2CMS8 LTC4300A-2IMS8 ABSOLUTE AXI U RATI GS W W W U PACKAGE/ORDER I FOR ATIO U U W (Note 1)
ELECTRICAL CHARACTERISTICS
The G denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. ENABLE/VCC2* SCLOUT SCLIN GND VCC SDAOUT SDAIN READY/ACC* TOP VIEW MS8 PACKAGE 8-LEAD PLASTIC MSOP *LTC4300A-2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VCC Positive Supply Voltage G 2.7 5.5 V ICC Supply Current VCC = 5.5V, VSDAIN = VSCLIN = 0V, LTC4300A-1 G 5.1 mA ISD Supply Current in Shutdown Mode VENABLE = 0V, LTC4300A-1 0.1 µA VCC2 Card Side Supply Voltage LTC4300A-2 G 2.7 5.5 V IVCC1 VCC Supply Current VSDAIN = VSCLIN = 0V, VCC1 = VCC2 = 5.5V, 4.1 mA LTC4300A-2 IVCC2 VCC2 Supply Current VSDAOUT = VSCLOUT = 0V, VCC1 = VCC2 = 5.5V, 2.1 2.9 mA LTC4300A-2 Start-Up Circuitry VPRE Precharge Voltage SDA, SCL Floating G 0.8 1.0 1.2 V tIDLE Bus Idle Time G 150 µs VEN ENABLE Threshold Voltage LTC4300A-1 0.5 • VCC 0.9 • VCC V VDIS Disable Threshold Voltage LTC4300A-1, ENABLE Pin 0.1 • VCC 0.5 • VCC V IEN ENABLE Input Current ENABLE from 0V to VCC, LTC4300A-1 ±0.1 µA tPHL ENABLE Delay, On-Off LTC4300A-1 ns READY Delay, Off-On LTC4300A-1 ns tPLH ENABLE Delay, Off-On LTC4300A-1 µs READY Delay, On-Off LTC4300A-1 ns IOFF READY OFF State Leakage Current LTC4300A-1 ±0.1 µA VOL READY Output Low Voltage IPULLUP = 3mA, LTC4300A-1 G 0.4 V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pullup resistor and VCC voltage is shown in the Typical Performance Characteristics section. The G denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Rise-Time Accelerators IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA,SCL, VCC = 2.7V, mA Slew Rate = 1.25V/µs (Note 2), LTC4300A-2, ACC = 0.7 • VCC2, VCC2 = 2.7V VACCDIS Accelerator Disable Threshold LTC4300A-2 0.3 • VCC2 0.5 • VCC2 V VACCEN Accelerator Enable Threshold LTC4300A-2 0.5 • VCC2 0.7 • VCC2 V IVACC ACC Input Current LTC4300A-2 ±0.1 µA tPDOFF ACC Delay, On/Off LTC4300A-2 ns Input-Output Connection VOS Input-Output Offset Voltage 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), G 100 175 mV LTC4300A-2, VCC2 = 3.3V, VIN = 0.2V fSCL, SDA Operating Frequency Guaranteed by Design, Not Subject to Test 400 kHz CIN Digital Input Capacitance Guaranteed by Design, Not Subject to Test pF VOL Output Low Voltage, Input = 0V SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, G 0.4 V VCC2 = 2.7V, LTC4300A-2 ILEAK Input Leakage Current SDA, SCL Pins = VCC = 5.5V, µA LTC4300A-2, VCC2 = 5.5V Timing Characteristics fI2C I2C Operating Frequency (Note 4) 400 kHz tBUF Bus Free Time Between Stop (Note 4) 1.3 µs and Start Condition thD,STA Hold Time After (Repeated) (Note 4) 0.6 µs Start Condition tsu,STA Repeated Start Condition Setup Time (Note 4) 0.6 µs tsu,STO Stop Condition Setup Time (Note 4) 0.6 µs thD, DAT Data Hold Time (Note 4) 300 ns tsu, DAT Data Setup Time (Note 4) 100 ns tLOW Clock Low Period (Note 4) 1.3 µs tHIGH Clock High Period (Note 4) 0.6 µs tf Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tr Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • CB 300 ns Note 4: Guaranteed by design, not subject to test. Note 5: CB = total capacitance of one bus line in pF.
–50 –25 100 TEMPERATURE (°C) IPULLUPAC (mA) 4300-1/2 G03 VCC = 2.7V VCC = 5V VCC = 3V RPULLUP (Ω) 10,000 20,000 30,000 40,000 VOUT – VIN (mV) 4300-1/2 G04 300 250 200 150 100 VCC = 3.3V VCC = 5V TA = 25°C VIN = 0V IPULLUPAC vs Temperature Connection Circuitry VOUT – VIN TYPICAL PERFOR A CE CHARACTERISTICS U W –50 –25 100 TEMPERATURE (°C) tPHL (ns) 4300-1/2 G02 100 VCC = 2.7V VCC = 3.3V VCC = 5.5V CIN = COUT = 100pF RPULLUPIN = RPULLUPOUT = 10k Input – Output tPHL vs Temperature (LTC4300A-1) –40 TEMPERATURE (°C) ICC (mA) 4300-1/2 G01 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 VCC = 5.5V VCC = 2.7V ICC vs Temperature (LTC4300A-1)
ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Volt- age. For the LTC4300A-1, this is a digital CMOS threshold input pin. Grounding this pin puts the part in a low current (<1µA) mode. It also disables the rise-time accelerators, disables the bus precharge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. Drive ENABLE all the way to VCC for normal operation. Connect ENABLE to VCC if this feature is not being used. For the LTC4300A-2, this is the supply voltage for the devices on the card I2C busses. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. Place a bypass capacitor of at least 0.01µF close to this pin for best results. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the SCL bus on the card. SCLIN (Pin 3): Serial Clock Input. Connect this pin to the SCL bus on the backplane. GND (Pin 4): Ground. Connect this pin to a ground plane for best results. READY/ACC (Pin 5): Connection Flag/Rise-Time Accel- erator Control. For the LTC4300A-1, this is an open-drain NMOS output which pulls low when either ENABLE is low or the start-up sequence described in the Operation sec- tion has not been completed. READY goes high when ENABLE is high and start-up is complete. Connect a 10k resistor from this pin to VCC to provide the pull up. For the LTC4300A-2, this is a CMOS threshold digital input pin that enables and disables the rise-time accelerators on all four SDA and SCL pins. Drive ACC all the way to the VCC2 supply voltage to enable all four accelerators; drive ACC to ground to turn them off. SDAIN (Pin 6): Serial Data Input. Connect this pin to the SDA bus on the backplane. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the SDA bus on the card. VCC (Pin 8): Main Input Power Supply from Backplane. This is the supply voltage for the devices on the backplane I2C busses. Connect pull-up resistors from SDAIN and SCLIN (and also from SDAOUT and SCLOUT for the LTC4300A-1) to this pin. Place a bypass capacitor of at least 0.01µF close to this pin for best results. PI FU CTIO S U U U
0.5pF READY ENABLE UVLO SCLIN 4300A-1 BD CONNECT STOP BIT AND BUS IDLE GND CONNECT 20pF RD S QB 0.5µA 0.55VCC/ 0.45VCC VCC – 1V 2mA 95µs DELAY, RISING ONLY BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT SCLOUT SDAIN BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT SDAOUT VCC PRECHARGE 100k RCH2 100k RCH4 SLEW RATE DETECTOR 2mA SLEW RATE DETECTOR 2mA SLEW RATE DETECTOR 2mA SLEW RATE DETECTOR CONNECT ENABLE 2-Wire Bus Buffer and Hot Swap TM Controller BLOCK DIAGRA W Hot Swap is a trademark of Linear Technology Corporation. (LTC4300A-1)
W (LTC4300A-2) 100k RCH1 100k RCH3 0.5pF UVLO SCLIN 4300A-2 BD CONNECT CONNECT STOP BIT AND BUS IDLE GND 20pF RD S QB 0.5µA 0.55VCC/ 0.45VCC VCC2 – 1V 2mA BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT SCLOUT SDAIN VCC BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT SDAOUT VCC2 ACC PRECHARGE 100k RCH2 100k RCH4 CONNECT SLEW RATE DETECTOR 2mA SLEW RATE DETECTOR 2mA SLEW RATE DETECTOR ACC ACC 2mA SLEW RATE DETECTOR 95µs DELAY, RISING ONLY 2-Wire Bus Buffer and Hot Swap Controller
Figure 1. An external NMOS device pulls down the voltage it has enough voltage to do so.
capacitance in picofarads (pF). to overcome the precharge voltage. Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a CompactPCI System
- • • 10k 10k R10 10k I/O PERIPHERAL CARD 2 LTC4300A-1 CARD2_SCL CARD2_SDA STAGGERED CONNECTOR STAGGERED CONNECTOR 10k 10k 10k I/O PERIPHERAL CARD 1 LTC4300A-1 CARD_SCL CARD_SDA 10k VCC 10k BACKPLANE BACKPLANE CONNECTOR SDA BD_SEL SCL 0.01µF 10k 10k R11 10k 0.01µF 0.01µF POWER SUPPLY HOT SWAP POWER SUPPLY HOT SWAP POWER SUPPLY HOT SWAP CARD ENABLE/DISABLE CARD ENABLE/DISABLE
W U U U meeting rise- and fall-time specifications for one nanofarad of capacitance, thus allowing much more interconnect distance. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed VOL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-to-back LTC4300A-1s add together, directly contributing to the same problem. Systems with Disparate Supply Voltages (LTC4300A-1) In large 2-wire systems, the VCC voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. This situation is well modelled by a series resistor in the VCC line, as shown in Figure 8. For proper operation of the LTC4300A-1, make sure that VCC(BUS) ≥ VCC(LTC4300A) – 0.5V. 5V to 3.3V Level Translator and Power Supply Redundancy (LTC4300A-2) Systems requiring different supply voltages for the backplane side and the card side can use the LTC4300A-2, as shown in Figure 9. The pull-up resistors on the card side connect from SDAOUT to SCLOUT to VCC2, and those on the backplane side connect from SDAIN and SCLIN to VCC. The LTC4300A-2 functions for voltages ranging from 2.7V to 5.5V on both VCC and VCC2. There is no constraint on the voltage magnitudes of VCC and VCC2 with respect to each other. This application also provides power supply redundancy. If the VCC2 voltage falls below its UVLO threshold, the LTC4300A-2 disconnects the backplane from the card, so that the backplane can continue to function. If the VCC voltage falls below its UVLO threshold and the VCC2 voltage remains active, ground the ACC pin to ensure proper operation.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION U 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) MSOP (MS8) 0802 0.53 ± 0.015 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.077) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.13 ± 0.076 (.005 ± .003) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 4.90 ± 0.15 (1.93 ± .006) 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) NOTE 4 0.52 (.206) REF 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.04 (.0165 ± .0015) TYP 0.65 (.0256) BSC
LINEAR TECHNOLOGY CORPORATION 2001 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 G FAX: (408) 434-0507 G www.linear.com LT/TP 0203 2K • PRINTED IN USA RELATED PARTS PART NUMBER
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