LT8709

DATASHEET SEARCH SITE

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 46

Technical content

8709fFor more information www.linear .com/L T8709 Typical applicaTion FeaTures DescripTion Negative Input Synchronous Multi-Topology DC/DC Controller 250kHz, –16V to –30V Input to –12V/8.5A Output Buck Efficiency and Power Loss vs Load Current (–VIN = –24V)

applicaTions

L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The LT®8709 is a synchronous PWM controller for negative- to-negative or negative-to-positive DC/DC conversion, with rail-to-rail output current monitor and control. The LT8709 is ideal for many local power supply designs. It can be easily configured in buck, boost, buck-boost, and inverting topologies with negative input voltages. In addition, the LT8709’s rail-to-rail output current sense allows the part to be configured in current limited applica- tions such as battery or capacitor charging. The PG pin is used for power good indication. The LT8709’ s switching frequency range can be set between 100kHz and 750kHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to the –VIN pin, or it may be synchronized to an external clock. The LT8709 also features innovative EN/FBIN pin circuitry that allows for slowly varying input signals and an adjust- able undervoltage lockout function. The pin is also used as input voltage regulation to avoid collapsing a high imped- ance input supply. Additional features such as frequency foldback, thermal shutdown and soft-start are integrated. The LT8709 is available in a 20-lead TSSOP package. n Wide Negative Input Range: –4.5V to –80V n Rail-to-Rail Output Current Monitor and Control n Input Voltage Regulation for High Impedance Inputs n Power Good Indication Pin n MODE Pin for Forced CCM (Continuous Conduction Mode) or Pulse-Skipping/DCM (Discontinuous Conduction Mode) Operation n Switching Frequency Up to 750kHz n Easily Configurable as a Buck, Boost, Buck-Boost, or Inverting Converter with a Single Feedback Pin n Can be Synchronized to an External Clock n High Gain EN/FBIN Pin Accepts Slowly Varying Input Signals n 20-Lead TSSOP Package n High Power Negative Input, Negative Output Power Supplies n High Power Negative Input, Positive Output Power Supplies n Telecom Equipment Power Supplies n Cathodic Protection Power Supplies LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 4.5 3.5 4.0 2.5 1.5 3.0 2.0 1.0 0.5 52 7 8 9

8709 TA01b

IMON SS–VIN CSP BGCSNTG L T8709

8709 TA01a

–12V 8.5A –VIN –16V TO –30V –VIN 7.3µH 4m/uni03A9 120µF 2.2µF 22µF 10k 2.2µF 10µF 143k 100k 2m/uni03A9 62.5k 33k 5.9k 150µF+ 68nF 470nF 2.2nF 100pF 2.2µF 2.2µF 4.99k

8709f For more information www.linear .com/L T8709 pin conFiguraTion absoluTe MaxiMuM raTings (Note 1) FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW FBY V C SS PG IMON ISN ISP BIAS INTVEE TG –VIN SYNC RT MODE EN/FBIN CSP CSN GND INTV CC BG –VIN TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 21) IS –VIN, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8709EFE#PBF LT8709EFE#TRPBF LT8709FE 20-Lead Plastic TSSOP –40°C to 125°C LT8709IFE#PBF LT8709IFE#TRPBF LT8709FE 20-Lead Plastic TSSOP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ BI BG Vo TG Vo RT SS F EN/F SYN P MODE Vo INT IN C C I 0.4V to ISN + 2V IMO O perating Junction Temperature Range 40°C to 125°C °C to 125°C to 150°C

8709fFor more information www.linear .com/L T8709

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Input Voltage V GND – V–VIN OR VBIAS – V–VIN VGND – V–VIN, if VBIAS – V–VIN ≥ 4.5V l 4.25 4.5 V V Quiescent Current, IGND, Not Switching VBIAS – V–VIN = 8V, VISN – V–VIN = 8V VBIAS – V–VIN = 6.3V, VBIAS – VINTVEE = 6.3V 5.5 5.5 7.5 mA mA Quiescent Current in Shutdown, I GND VEN/FBIN = 0V 0 1 µA EN/FBIN Minimum Input Voltage High, Releases SS EN/FBIN Rising l 1.64 1.7 1.76 V EN/FBIN Minimum Input Voltage High, Chip-On but SS Held Low EN/FBIN Rising EN/FBIN Falling l l 1.22 1.18 1.3 1.26 1.38 1.34 V V EN/FBIN Minimum Input Voltage High Hysteresis 44 mV EN/FBIN Input Voltage Low Shutdown Mode l 0.3 V EN/FBIN Pin Bias Current VEN/FBIN = 3V VEN/FBIN = 1.7V VEN/FBIN = 1.6V VEN/FBIN = 0V 19.5 17.5 22.5 0.1 µA µA µA µA SS Charge Current V SS = 50mV, Current Flowing Out of SS Pin l 7 10.1 13.8 µA SS Low Detection Voltage Part Exiting Undervoltage Lockout l 18 50 82 mV SS Hi Detection Voltage SS Rising SS Falling 1.5 1.3 1.8 1.7 2.1 2.05 V V SS Hi Detection Hysteresis 100 mV Low Dropout Regulators, INTV CC and INTVEE INTVCC Voltage IINTVCC = 10mA l 6.2 6.3 6.4 V INTVCC Undervoltage Lockout INTV CC Rising INTVCC Falling l l 3.88 3.5 3.73 4.12 3.95 V V INTV CC Undervoltage Lockout Hysteresis 270 mV INTVCC Dropout Voltage, VGND – INTVCC VGND – V–VIN = 6V, VBIAS – V–VIN = 0V, IINTVCC = 10mA VGND – V–VIN = 0V, VBIAS – V–VIN = 6V, IINTVCC = 10mA 255 280 mV mV INTV CC Load Regulation VGND – V–VIN = 0V, IINTVCC = 0mA to 80mA VBIAS – V–VIN = 0V, IINTVCC = 0mA to 40mA –0.44 –0.34 INTV CC Line Regulation 10V ≤ VGND – V–VIN ≤ 80V, VBIAS – V–VIN = 0V, IINTVCC = 10mA 10V ≤ VBIAS – V–VIN ≤ 80V, VGND – V–VIN = 0V, IINTVCC = 10mA –0.003 –0.006 –0.03 –0.03 %/V %/V INTV CC Maximum External Load Current 5 mA INTVEE Voltage, VBIAS – VINTVEE IINTVEE = 10mA l 6.03 6.18 6.33 V INTVEE Undervoltage Lockout, VBIAS – VINTVEE VBIAS – VINTVEE Rising VBIAS – VINTVEE Falling l l 3.24 2.94 3.42 3.22 3.6 3.48 V V INTV EE Undervoltage Lockout Hysteresis, VBIAS – VINTVEE 200 mV INTVEE Dropout Voltage, VINTVEE – V–VIN VBIAS – V–VIN = 6V, IINTVEE = 10mA 0.75 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VGND – V–VIN = 12V, VEN/FBIN – V–VIN = 12V, VBIAS – V–VIN = 12V, unless otherwise noted. Pin voltages have the following relations: FBY is relative to the GND pin, TG and INTVEE to the BIAS pin, and all other pins to the –VIN pin, unless otherwise stated. Pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (Note 2)

8709f For more information www.linear .com/L T8709 PARAMETER CONDITIONS MIN TYP MAX UNITS Control Loops (Refer to Block Diagram to Locate Amplifiers) Current Limit Voltage, VCSP – VCSN IFBY = –67.9µA, Minimum Duty Cycle IFBY = –67.9µA, Maximum Duty Cycle l l mV mV I FBY = –108µA, MODE = 0V, Minimum Duty Cycle IFBY = –108µA, MODE = 0V, Maximum Duty Cycle l l –41 –65 –32 –51 –23 –38 mV mV FBY Voltage for Negative Output Voltage Regulation Q1 Conducting Current, Current Flowing Out of FBY Pin FBY Voltage for Positive Output Voltage Regulation M1 Conducting Current, Current Flowing into FBY Pin l –60 –15.8 25 mV Negative FBY Pin Bias Current Current Flowing Out FBY Pin l 81.4 83.5 85.7 µA Positive FBY Pin Bias Current Current Flowing Into FBY Pin l 80.1 83.9 87.5 µA FBY Voltage-to-Current Amp T ransconductance, ΔI FBY/ΔVFBY Current Flowing Out of FBY Pin, ΔIFBY = 10µA Current Flowing into FBY Pin, ΔIFBY = 10µA 1.8 1.05 mS mS FBY Error Amp T ransresistance ΔV VC/ΔIFBY Current Flowing Out of FBY Pin, ΔVVC = 200mV Current Flowing into FBY Pin, ΔVVC = 200mV 508 516 kΩ kΩ FBY Error Amp Current Gain ΔI VC/ΔIFBY ΔIVC = 2µA 1.5 A/A FBY Line Regulation 4.5V ≤ VGND – V–VIN ≤ 80V, VBIAS – V–VIN = 0V –0.02 0.003 0.02 %/V Output Current Sense Regulation Voltage, V ISP – VISN VISN = 80V, IFBY = –53µA VISN = 12V, IFBY = –53µA VISN = 0V, IFBY = –53µA VISN = 12V, IFBY = –53µA, INTVEE in UVLO and SS > 1.8V l l l l mV mV mV mV IMON Regulation Voltage, EA2 I FBY = –53µA IFBY = –53µA, INTVIEE in UVLO and SS > 1.8V l l 1.184 0.885 1.213 0.916 1.24 0.947 V V Output Current Sense Amp Transconductance, A7 ΔI IMON = 10μA 1000 µS Output Current Sense Amp Voltage Gain, A7

11.9 V/V

Output Current Sense Amp Input Dynamic Range, A7 Negative Input Range Positive Input Range 500 –51.8 mV mV IMON Amp T ransconductance, EA2 ΔI VC = 2μA, IFBY = –53µA 165 µS IMON Amp Voltage Gain, EA2 VISN = 12V, IFBY = –53µA 65 V/V EN/FBIN Input Regulation Voltage, EA3 I FBY = –53µA l 1.55 1.607 1.662 V EN/FBIN Amp T ransconductance, EA3 ΔI VC = 2µA, IFBY = –53µA 140 µS EN/FBIN Amp Voltage Gain, EA3 I FBY = –53µA 55 V/V MODE Forced CCM Threshold To Exit Forced CCM Mode, MODE Rising To Enter Forced CCM Mode, MODE Falling l l 1.19 1.125 1.224 1.175 1.258 1.23 V V MODE Forced CCM Threshold Hysteresis 49 mV DCM Comparator Threshold in Pulse-Skipping Mode, MODE = 2V V ISN = 80V, To Enter DCM Mode, VISP – VISN Falling VISN = 12V, To Enter DCM Mode, VISP – VISN Falling VISN = 0V, To Enter DCM Mode, VISP – VISN Falling l l l –4.5 –4.5 –7.5 2.8 2.8 2.8 mV mV mV DCM Comparator Threshold in Forced CCM, MODE = 0V V ISN = 80V, To Enter DCM Mode, VISP – VISN Falling VISN = 12V, To Enter DCM Mode, VISP – VISN Falling VISN = 0V, To Enter DCM Mode, VISP – VISN Falling l l l –380 –380 –380 –300 –300 –300 –220 –220 –220 mV mV mV elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VGND – V–VIN = 12V, VEN/FBIN – V–VIN = 12V, VBIAS – V–VIN = 12V, unless otherwise noted. Pin voltages have the following relations: FBY is relative to the GND pin, TG and INTVEE to the BIAS pin, and all other pins to the –VIN pin, unless otherwise stated. Pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (Note 2)

8709fFor more information www.linear .com/L T8709 PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator Switching Frequency, fOSC RT = 46.4k RT = 357k l l 640 750 100 860 115 kHz kHz Switching Frequency in Foldback Compared to Normal f OSC 1/5 ratio Switching Frequency Range Free-Running or Synchronizing l 100 750 kHz SYNC High Level for Sync l 1.5 V SYNC Low Level for Sync l 0.4 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 3V 20 80 % Recommended Min SYNC Ratio f SYNC/fOSC 3/4 Gate Drivers, BG and TG BG Rise Time CBG = 3300pF (Note 3) 24 ns BG Fall Time CBG = 3300pF (Note 3) 21 ns TG Rise Time CTG = 3300pF (Note 3) 15 ns TG Fall Time CTG = 3300pF (Note 3) 16 ns BG and TG Non-Overlap Time TG Rising to BG Rising, CBG = CTG = 3300pF (Note 3) BG Falling to TG Falling, CBG = CTG = 3300pF (Note 3) 140 220 150 ns ns BG Minimum On-Time C BG = CTG = 3300pF 150 420 ns BG Minimum Off-Time CBG = CTG = 3300pF 100 480 ns TG Minimum On-Time CBG = CTG = 3300pF 0 150 ns TG Minimum Off-Time CBG = CTG = 3300pF 290 770 ns Power Good Indicators, PG PG Power Good Threshold for Negative FBY Voltage Current Out of FBY Pin Rising Current Out of FBY Pin Falling l l 63.5 74.9 67.5 71.5 µA µA PG Power Good Threshold for Positive FBY Voltage Current into FBY Pin Rising Current into FBY Pin Falling l l 71.5 63.5 75.4 67.5 79.5 71.5 µA µA PG Power Good Hysteresis for Negative FBY Voltage 7.4 µA PG Power Good Hysteresis for Positive FBY Voltage 7.9 µA PG Anti-Glitch Delay Delay from PG Threshold T rip to PG Toggle 100 µs PG Output Voltage Low 100µA into PG Pin, |IFBY| < PG Threshold l 9 50 mV PG Leakage Current VPG = 7V, |IFBY| > PG Threshold 0.01 1 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8709E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LT8709I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. Note 5: Do not apply a positive or negative voltage or current source to the BG, TG, and INT VEE pins, otherwise permanent damage may occur, except INTVEE may be connected to –VIN if BIAS is connected to INTVCC. elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VGND – V–VIN = 12V, VEN/FBIN – V–VIN = 12V, VBIAS – V–VIN = 12V, unless otherwise noted. Pin voltages have the following relations: FBY is relative to the GND pin, TG and INTVEE to the BIAS pin, and all other pins to the –VIN pin, unless otherwise stated. Pin currents have the following relations: positive current is denoted as current flowing into the pin; negative current is denoted as current flowing out of the pin, unless otherwise stated. (Note 2)

8709f For more information www.linear .com/L T8709 Positive and Negative Feedback Voltage vs Temperature Positive and Negative FBY Currents vs Temperature Input Regulation Voltage vs Temperature (EN/FBIN) Input Regulation Voltage vs FBY (EN/FBIN) Current Sense Voltage vs Temperature (ISP-ISN and IMON) Current Sense Voltage vs FBY (ISP-ISN and IMON) Max Current Limit vs Duty Cycle (CSP - CSN) Max Current Limit vs Temperature (CSP - CSN) Max Current Limit vs SS (CSP - CSN) Typical perForMance characTerisTics DUTY CYCLE (%) MAX POSITIVE CSP-CSN (mV) MAX NEGATIVE CSP-CSN (mV) –20 –30 –25 –40 –50 –35 –45 –55 –60 5020 70 80 90

8709 G01

fOSC = 300kHz SS (V) 0.0 CSP-CSN (mV) 0.80.2 1 1.2 1.4

8709 G03

1.60.4 0.6 TEMPERATURE (°C) –50 MAX POSITIVE CSP-CSN (mV) MAX NEGATIVE CSP-CSN (mV) –26 –30 –28 –34 –32 –36 –38 50–25 75 100

8709 G02

TEMPERATURE (°C) –50 POSITIVE FBY VOL TAGE (mV) NEGATIVE FBY VOL TAGE (V) –10 –15 –20 –25 –30 –1.220 –1.230 –1.225 –1.240 –1.245 –1.250 –1.235 –1.255 –1.260 50–25 75 100

8709 G04

TEMPERATURE (°C) –50 POSITIVE FBY CURRENT INTO PIN (µA) NEGATIVE FBY CURRENT OUT OF PIN (µA)86.0 85.0 85.5 84.0 83.5 83.0 84.5 82.5 82.0 81.5 86.0 85.0 85.5 84.0 83.5 83.0 84.5 82.5 82.0 81.5 50–25 75 100

8709 G05

TEMPERATURE (°C) –50 EN/FBIN VOL TAGE (V) 1.63 1.61 1.62 1.60 1.59 1.58 1.57 –25 50 75 100

8709 G06

FBY CURRENT (µA) EN/FBIN (V) 2.0 1.8 1.9 1.7 1.6 1.5 1.4 20 50 60 70 80

8709 G07

TEMPERATURE (°C) –50 AVERAGE ISP-ISN (mV) IMON (V) 57.5 52.5 55.0 50.0 47.5 45.0 42.5 1.2175 1.2125 1.2150 1.2100 1.2075 1.2050 1.2025 –25 50 75 100

8709 G08

FBY CURRENT (µA) AVERAGE ISP-ISN (mV) IMON (V) 1.30 1.20 1.25 1.15 1.10 1.05 1.00 20 50 60 70 80

8709 G09

TA = 25°C, all voltages relative to –VIN unless otherwise noted.

8709fFor more information www.linear .com/L T8709 MODE Pin Threshold vs Temperature (Rising and Falling) EN/FBIN Thresholds vs Temperature (1.7V and 1.3V) EN/FBIN Pin Current (0V to 2V) vs Temperature EN/FBIN Pin Current (0V to 80V) vs Temperature Oscillator Frequency vs Temperature (100kHz and 750kHz) Oscillator Frequency During Soft-Start BG and TG T ransition Time vs Cap Load DCM Comparator Threshold vs Temperature PG Threshold vs Temperature (Rising and Falling) Typical perForMance characTerisTics CAP LOAD (nF) TRANSITION TIME (ns) 2 8 10

8709 G18

TA = 25°C, all voltages relative to –VIN unless otherwise noted. TEMPERATURE (°C) –50 ISP-ISN (mV) ISP-ISN (mV) –280 –300 –290 –310 –320 –330 –340 –25 50 75 100

8709 G10

MODE = 0V , FCM MODE = 2V , DCM TEMPERATURE (°C) –50 MODE (V) 1.24 1.22 1.23 1.21 1.20 1.18 1.17 1.19 1.16 1.15 1.14 –25 50 75 100

8709 G12

EN/FBIN VOL TAGE (V) EN/FBIN PIN CURRENT (µA) 0.25 1 1.25 1.5 1.75

8709 G14

20.5 0.75 –40°C 25°C 125°C EN/FBIN VOL TAGE (V) EN/FBIN PIN CURRENT (µA) 600 500 400 200 300 100 10 40 50 60 70

8709 G15

–40°C 25°C 125°C TEMPERATURE (°C) –50 fOSC (kHz) 900 800 700 500 400 200 100 600 300 –25 50 75 100 125

8709 G16

RT = 46.4k/uni03A9 RT = 357k/uni03A9 TEMPERATURE (°C) –50 EN/FBIN CHIP ENABLE (V) EN/FBIN ACTIVE MODE (V) 1.40 1.36 1.38 1.34 1.32 1.28 1.26 1.30 1.24 1.22 1.20 1.75 1.71 1.73 1.69 1.67 1.63 1.61 1.59 1.57 1.65 1.55 –25 50 75 100

8709 G13

FBY CURRENT (µA) –75 NORMALIZED OSCILLATOR FREQUENCY (FSW/FNOM) 1 –50 25 50 75

8709 G17

–25 0 INVERTING CONFIGURATIONS NONINVERTING CONFIGURATIONS TEMPERATURE (°C) –50 POSITIVE FBY CURRENT PIN (µA) NEGATIVE FBY CURRENT OUT OF PIN (µA)80 –25 50 75 100

8709 G11

8709f For more information www.linear .com/L T8709 INTVCC Current Limit vs GND or BIAS INTVCC Dropout from GND or BIAS INTV EE vs Temperature INTVEE UVLO vs Temperature (Rising and Falling) INTVEE Current Limit vs BIAS INTVEE Dropout (BIAS = 6V) Minimum Operating Input Voltage INTV CC vs Temperature INTVCC UVLO vs Temperature (Rising and Falling) Typical perForMance characTerisTics INTVEE LOAD CURRENT (mA) 10 0 INTVEE –V–VIN (V) 1.2 1.0 0.9 0.8 0.6 0.5 0.7 1.1 0.4

8709 G27

–40°C 25°C 125°C TEMPERATURE (°C) –50 GND OR VBIAS (V) 4.35 4.33 4.29 4.25 4.23 4.21 4.19 4.17 4.31 4.27 4.15 –25 75 100 125

8709 G19

TEMPERATURE (°C) –50 INTVCC (V) 6.40 6.28 6.24 6.36 6.32 6.20 –25 75 100 125

8709 G20

IINTVCC = 10mA TEMPERATURE (°C) –50 INTVCC (V) 4.2 3.9 3.8 3.7 3.6 4.1 4.0 3.5 –25 75 100 125

8709 G21

INPUT VOL TAGE (V) INTVCC CURRENT LIMIT (mA) 150 100 125 20 60 70 80

8709 G22

INTVCC > 3.5V INTVCC > 3.5V INTVCC < 3.5V INTVCC LOAD CURRENT (mA) 10 0 INPUT - INTVCC (V) 500 400 350 300 250 450 200 20 60 70 80

8709 G23

TEMPERATURE (°C) –25 –50 BIAS - INTVEE (V) 6.28 6.20 6.16 6.12 6.24 6.08 0 100 125

8709 G24

IINTVEE = 10mA TEMPERATURE (°C) –25 –50 BIAS - INTVEE (V) 3.6 3.4 3.3 3.2 3.1 3.5 3.0 0 100 125

8709 G25

BIAS (V) 20 10 INTVEE CURRENT LIMIT (mA) 30 70 80

8709 G26

BIAS - INTVEE =5V TA = 25°C, all voltages relative to –VIN unless otherwise noted.

8709fFor more information www.linear .com/L T8709 pin FuncTions FBY (Pin 1): Feedback Pin. Its voltage is referred to the GND pin. For a boost, buck-boost, or inverting converter, tie a resistor from the FBY pin to V OUT according to the following equations: RFBY = | VOUT | –1.234V 83.5µA Negative Output Voltage RFBY = VOUT + 15.8mV 83.9µA Positive Output Voltage See the Applications section for more information. VC (Pin 2): Error Amplifier Output Pin. Its voltage is re- ferred to the –VIN pin. Connect an external compensation network between this and the –VIN pin. SS (Pin 3): Soft-Start Pin. Its voltage is referred to the –VIN pin. Place a soft-start capacitor here that is greater than 5x the IMON capacitor. Upon start-up, the SS pin will be charged by a nominal 260k resistor to ~2.7V. During a current overload as seen by ISP-ISN, overtemperature, or UVLO condition, the SS pin will be quickly discharged to reset the part. Once these conditions have cleared, the part will attempt to restart. PG (Pin 4): Power Good Indication Pin. Its voltage is referred to the –VIN pin. The PG pin functions as an ac- tive high power good pin. Power is good when the FBY pin current is –74.9µA or 75.4µA (~90% of the regulation current), which corresponds to ~90% of the regulation voltage on V OUT. For power good indication, there is a 100µs anti-glitch delay. A pull-up resistor or some other form of pull-up network is required on this pin to use the feature. See the Block Diagram and Applications section for more information. IMON (Pin 5): Output Current Sense Monitor Pin. Its voltage is referred to the –V IN pin. Outputs a voltage that is proportional to the voltage between the ISP and ISN pins, as given below. VIMON = 11.9 • (VISP – ISN + 51.8mV) Since the voltage across the ISP and ISN pins is AC, a filtering capacitor is needed between the IMON and –VIN pins to average out the ISP and ISN voltage. Recommended capacitor values are from 10nF – 100nF. A 51.8mV offset is added to the amplifier such that an average voltage of 0V on ISP-ISN corresponds to a IMON voltage of 616mV. When the average voltage across the ISP and ISN pins is 50mV, the IMON pin will output ~1.213V. Do not resistively load down this pin. ISN, ISP (Pins 6, 7): Output Current Sense Negative and Positive Input Pins Respectively. Kelvin connect the ISN and ISP pins to a sense resistor to limit the output cur - rent. The commanded NFET current will limit the voltage difference across the sense resistor to 50mV. BIAS (Pin 8): Additional Input Supply and TG Gate Driver High Voltage Rail. BIAS is a second positive input sup- ply pin in addition to GND and must be locally bypassed to –VIN. The BIAS pin sets the top rail for the TG gate driver. BIAS must be connected to the converter’s V OUT for a negative inverting converter, or INTVCC for a negative boost converter, or GND for a negative buck or negative buck-boost converter. INTV EE (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must be locally bypassed to BIAS with a minimum capacitance of 2.2µF. This pin sets the bottom rail for the TG gate driver. The TG gate driver can begin switching when BIAS – INTVEE exceeds 3.42V (typical). Connect this pin to –VIN for a negative boost converter. TG (Pin 10): PFET Gate Drive Pin. Low and high levels are BIAS – INTVEE and BIAS respectively. BG (Pin 11): NFET Gate Drive Pin. Low and high levels are –VIN and INTVCC respectively. INTVCC (Pin 12): 6.3V Dual Input LDO Regulator Pin. Its voltage is referred to the –VIN pin. Must be locally bypassed to –VIN with a minimum capacitance of 2.2µF. Logic will choose to run INTV CC from the GND or BIAS pins. A maximum 5mA external load can connect to the INTV CC pin. The BG gate driver can begin switching when INTVCC exceeds the 4V (typical) INTVCC undervoltage lockout. GND (Pin 13): Positive Input Supply Pin. Must be locally bypassed to –VIN. Can run down to V–VIN as long as BIAS –V–VIN > 4.5V.

8709f For more information www.linear .com/L T8709 pin FuncTions CSN, CSP (Pins 14, 15): NFET Current Sense Negative and Positive Input Pins Respectively. Kelvin connect these pins to a sense resistor to control the NFET switch current. The maximum sense voltage at low duty cycle is 50mV (typical). EN/FBIN (Pin 16): Enable and Input Voltage Regulation Pin. Its voltage is referred to the –VIN pin. In conjunction with the INTVCC and INTVEE UVLO (undervoltage lockout) circuits, overtemperature protection and output overcur- rent protection; this pin is used to enable/disable the chip and restart the soft-start sequence. The EN/FBIN pin is also used to limit the NFET current to avoid collapsing the input supply. Drive the pin below 0.3V to disable the chip with very low quiescent current. Drive the pin above 1.7V (typical) to activate the chip and restart the soft-start sequence. The commanded NFET current will be controlled by the EN/FBIN amplifier when the voltage drops between 1.55V and 1.662V. See the Block Diagram and Applica - tions section for more information. Do not float this pin. MODE (Pin 17): DCM /CCM Mode Pin. Its voltage is referred to the –V IN pin. Drive the pin below 1.175V (typical) to operate in forced CCM. Drive the pin above 1.224V (typi- cal) to operate in DCM and/or pulse-skipping mode at light loads. If SS < 1.8V (typical) or INTVEE is in UVLO, the part will operate in DCM at light load. RT (Pin 18): Timing Resistor Pin. Adjusts the LT8709’s switching frequency. Place a resistor from this pin to –VIN to set the frequency to a fixed free running level. Do not float this pin. SYNC (Pin 19): External Clock Input Pin. Its voltage is referred to the –V IN pin. To synchronize the switching frequency to an outside clock, simply drive this pin with a clock to override the internal clock. The logic-high voltage level of the SYNC clock must exceed 1.5V, and the logic- low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. –VIN (Pin 20, Exposed Pad Pin 21): Negative Voltage Input Pin. Since –VIN also serves as the chip ground, it must be soldered onto a local –VIN plane on the PCB.

Figure 1. Block Diagram NOTE: ALL THE VOLTAGES INSIDE THE CHIP ARE REFERRED TO THE –VIN PIN.

Figure 2. State Diagram

• ALL SWITCHES DISABLED CHIP OFF
• SS PULLED LOW
• INTVCC CHARGES UP INITIALIZE
• SS SLOWLY CHARGES UP
• V C PULLED LOW ACTIVE MODE
• PFET TURNS OFF FOR REMAINDER OF CYCLE IF ISP-ISN VOLTAGE FALLS BELOW 2.8mV (TYP)
• FOR VERY LIGHT LOAD, PART MAY SKIP PULSES DCM AT LIGHT LOAD
• VC COMMANDS PEAK INDUCTOR CURRENT TO MAINTAIN REGULATION REGULATION
• OUTPUT CURRENT LIMITED TO 25mV AVERAGE ACROSS THE ISP-ISN PINS OUTPUT CURRENT FOLDBACK
• BG AND TG SWITCH AT CONSTANT FREQUENCY
• INDUCTOR CURRENT CAN REVERSE
• IF ISP-ISN VOLTAGE GOES BELOW –300mV (TYP), PFET TURNS OFF SO INDUCTOR CURRENT GOES MORE POSITIVE FORCED CCM OPERATION
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED EN/FBIN < 1.3V (TYP) OR GND AND BIAS < 4.5V (MAX) 1.3V < EN/FBIN < 1.7V (TYP) AND GND OR BIAS > 4.5V EN/FBIN > 1.7V AND GND OR BIAS > 4.5V AND INTV CC > 4V (TYP) INTVEE REGULATOR IN UVLO AND SS > 1.8V (TYP) MODE < 1.175V (TYP) AND SS > 1.8V (TYP) MODE > 1.224V (TYP) SS < 50mV RESET RESET DETECTED
• NO RESET CONDITIONS DETECTED RESET OVER RESET RESET
• NFET BEGINS SWITCHING
• PFET STARTS SWITCHING WHEN INTV EE REGULATOR IS NOT IN UVLO BEGIN SWITCHING RESET RESET RESET REGULATION = OUTPUT VOLTAGE (FBY) INPUT VOLTAGE (EN/FBIN) OUTPUT CURRENT (ISP-ISN AND IMON) RESET = UVLO ON GND OR BIAS ( < 4.5V (MAX)) UVLO ON INTV CC ( < 4V (TYP)) EN/FBIN < 1.7V (TYP) AT 1ST POWER-UP EN/FBIN < 1.26V (TYP) AFTER ACTIVE MODE SET OVERCURRENT (ISP – ISN > 63.6mV AVERAGE (TYP)) OVERTEMPERATURE (T J > 175°C (TYP)) NOTE: ALL VOLTAGES ARE REFERRED TO THE –VIN PIN VOLTAGE.

including the BIAS pin, are relative to the –VIN pin. efficiency and high output current applications possible. (typical), the SS pin is not pulled low by the EN/FBIN pin. the chip, resulting in extremely low quiescent current. See Figure 3 for the different EN/FBIN voltage thresholds. section for more information. pin to avoid start-up issues. Figure 3. EN/FBIN Modes of Operation

8709 F03

8709f For more information www.linear .com/L T8709 Frequency Foldback The frequency foldback circuitry reduces the switching frequency when the FBY pin current < 56.9µA (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current at start-up. When the FBY current exceeds this value, the switching frequency returns to normal. If the part is configured to be in forced continuous conduction mode (MODE pin is driven below 1.175V), then the frequency foldback circuitry is disabled as long as INTV EE is not in UVLO and the SS pin is higher than the SS Hi threshold. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. OPERATION – REGULATION Use the Block Diagram when stepping through the following description of the LT8709 operating in regulation. Also, assume the converter’s load current is high enough such that the part is operating in synchronous switching. The LT8709 has three modes of regulation: 1. Output Voltage (via FBY pin) 2. Input Voltage (via EN/FBIN pin) 3. Output Current (via ISP, ISN, and IMON pins) All three of these regulation loops control the peak com- manded current through the external NFET, MN. This operation is the same regardless of the regulation mode, so that will be described first. At the start of each oscillator cycle, the SR latch (SR1) is set, which first turns off the external PFET, MP, and then turns on the external NFET, MN. The NFET’s source current flows through an external current sense resistor (RSENSE1) generating a voltage proportional to the NFET switch current. This voltage is then amplified by A5 and added to a stabilizing ramp. The resulting sum is fed into the positive terminal of the PWM comparator A6. When the voltage on the positive input of A6 exceeds the voltage on the negative input (VC pin), the SR latch is reset, turning off the NFET and then turning on the PFET. The voltage on the VC pin is controlled by one of the regulation loops, or a combination of regulation loops. For simplicity, each mode of regulation will be described independently so that only one of the regulation loops is in command of the LT8709. Output Voltage Regulation In most cases, a single external resistor is used to set the target output voltage. See the Pin Functions section for selecting the feedback resistor for a desired output voltage. The VC pin voltage (negative input of A6) is set by EA1, which is an amplified difference between the FBX voltage, (the product of the FBY current and 7.25kΩ plus 0.6065V) and the reference voltage (1.213V). In this manner, the FBY error amplifier sets the correct peak current level to maintain output voltage regulation. Input Voltage Regulation There are two ways to set the input voltage regulation: a resistor divider to EN/FBIN between GND and –V IN or, a single resistor between GND and EN/FBIN pins. It is recom- mended to use a resistor divider for improved accuracy as described in the Setting the Input Voltage Regulation or Undervoltage Lockout section. The EN/FBIN pin volt - age connects to the positive input of amplifier EA3. The VC pin voltage is set by EA3, which is simply an amplified difference between the EN/FBIN pin voltage and a 1.607V reference voltage. In this manner, the EN/FBIN error ampli- fier sets the correct peak current level to maintain input voltage regulation. Output Current Regulation An external sense resistor connected between the ISP and ISN pins (RSENSE2) sets the maximum output current of the converter and is placed in series either with the source of the PFET, MP, or in series with the converter output, depending on the type of converter. A built-in 51.8mV offset is added to the voltage seen across RSENSE2. The sensed voltage along with the 51.8mV offset is then amplified and output to the IMON pin. An external capacitor must be placed from IMON to –VIN to filter the amplified chopped voltage that’s sensed across RSENSE2. The voltage at the IMON pin is fed to the negative input of the IMON error amplifier, EA2. The V C pin voltage is set by EA2, which is simply an amplified difference between the IMON pin voltage and the 1.213V reference voltage. In this manner, operaTion

to maintain output current regulation. current to about half of the desired limit.

1. Overcurrent sensed by IMON > 1.38V (typical)

Electrical Characteristics) to prevent cross conduction.

• MODE < 1.175V (typical) = Forced CCM or FCM
• MODE > 1.224V (typical) = DCM The forced continuous mode (FCM) allows the inductor current to reverse directions without any switches being forced off. At very light load currents, the inductor cur - rent will swing positive and negative as the appropriate average current is delivered to the output. There are some exceptions that negate the MODE pin and force the part to operate in DCM at light loads: 1. The INTVEE LDO is in UVLO (BIAS – INTVEE < 3.42V typical). 2. SS < 1.8V (typical). 3. The part is in a reset condition. When the LT8709 is in discontinuous mode (DCM), syn- chronous switch MP is held off whenever MP’s current falls near 0 current (less than 2.8mV (typical) across RSENSE2). This is to prevent current draw from the output and/or feeding current to the input supply. Under very light loads, the current comparator A6, may also remain tripped for several cycles (i.e. skipping pulses). Since MP is held off during the skipped pulses, the inductor current will not reverse. OPERATION – POWER GOOD (PG PIN) The PG pin is an open-drain pin that functions as an active high power good pin. The PG pin has 100µs (typical) delay in order to reject glitches or transient events. Power is good when FBY pin current is –74.9µA or 75.4µA (~90% of the regulation current), which corresponds to ~90% of the regulation voltage on V OUT. The PG compara- tors have 7.65µA of hysteresis to reject glitches. operaTion

Figure 4. Synchronous Switching

8709 F04

8709f For more information www.linear .com/L T8709 OPERATION – LDO REGULATORS (INTVCC AND INTVEE) The INTVCC LDO regulates to 6.3V (typical) and is used as the top rail for the BG gate driver. The INTVCC LDO can run from GND or BIAS and will minimize power losses by intelligently selecting the lower voltage as long as both are at a high enough voltage above –VIN. The INTVCC regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from dam- age if the pin is shorted to ground. The UVLO threshold on INTVCC is 4V (typical), and the LT8709 will be in reset until the LDO comes out of UVLO. The INTVEE regulator regulates to 6.18V (typical) below the BIAS pin voltage. The BIAS and INTV EE voltages are used for the top and bottom rails of the TG gate driver respectively. Just like the INTV CC regulator, the INTV EE regulator has a safety feature to limit the power dissipation in the internal pass device. The TG pin can begin switch- ing after the INTVEE regulator comes out of UVLO (3.42V typical across the BIAS and INTVEE pins) and the part is not in a reset condition. operaTion

Figure 5. Negative Buck Converter – The Component Values regulating FBY to –1.234V, referred to GND. information on the design equations presented in Table 1. Table 1. Negative Buck Design Equations Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations below. Performance Characteristics to find VCSPN at DCMAX.

• 2DCMAX –1( ) (2) LMAX ≤ RSENSE1 •(| VIN(MIN) | –| VOUT |)•DCMAX 3mV • f (3)
• Solve equations 1 to 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX. Step 7: COUT COUT ≥ 1–DCMIN 8 •L • f2•0.005 Step 8: CIN CIN ≥ IOUT •DCMAX •(1–DCMAX) f •0.005•| VIN(MIN)| Step 9: CIMON CIMON ≥ 100µA •DCMAX 0.005• f Step 10: RFBY1, RFBY2 RFBY2 = 4.99kΩ; RFBY1 = | VOUT | –1.234V 83.5µA+ 1.234V RFBY2 Step 11: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the effective ESR. IMON SS–VIN CSP BG CSNTG L T8709

8709 F05

8709 F06

Figure 6. Negative Inverting Converter – The Component Values –15.8mV with reference to the GND pin voltage. information on the design equations presented in Table 2. Table 2. Negative Inverting Converter Design Equations Performance Characteristics to find VCSPN at DCMAX.

• (1–DCMAX ) Step 5: RSENSE2 RSENSE2 = 0.05 1.6 •IOUT Step 6: L LTYP = RSENSE1 •| VIN(MIN) | •DCMAX 12.5mV • f (1) LMIN ≥ RSENSE1 •| VIN(MIN )| f • 40mV •DCMAX
• 2DCMAX –1 1–DCMAX   (2) LMAX ≤ RSENSE1 •| VIN(MIN)|• DCMAX 3mV • f (3)
• Solve equations 1 to 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX. Step 7: COUT COUT ≥ IOUT •DCMAX f •0.005• VOUT Step 8: CIN CIN ≥ IOUT •DCMAX f •0.005• VIN(MIN) Step 9: CIMON CIMON ≥ 100µA •DCMAX 0.005• f Step 10: RFBY RFBY = | VOUT |+15.8mV 83.9µA Step 11: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the effective ESR.

8709 F07

Figure 7. Negative Buck-Boost Converter – The Component –5V/7A Buck-Boost Topology Using Coupled Inductors. –1.234V through a single resistor between VOUT and FBY. the Appendix for the design equations. Table 3. Negative Buck-Boost Design Equations Performance Characteristics to find VCSPN at DCMAX.

• (1–DCMAX) Step 5: RSENSE2 RSENSE2 = 0.05 1.6 •IOUT Step 6: L LTYP = RSENSE1 •| VIN(MIN) | • DCMAX 12.5mV • f (1) LMIN ≥ RSENSE1 • |VIN(MIN)| f • 40mV •DCMAX
• 2DCMAX –1 1–DCMAX   (2) LMAX ≤ RSENSE1 • |VIN(MIN)| • DCMAX 3mV • f (3)
• Solve equations 1 to 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors. Step 7: C1 C1≥10µF TYPICAL;V RATING> |VOUT|( ) Step 8: COUT COUT ≥ 1– DCMIN 8 •L • f2•0.005 Step 9: CIN CIN ≥ IOUT •DCMAX f • 0.005• VIN Step 10: CIMON CIMON ≥ 100µA •DCMAX 0.005• f Step 11: RFBY RFBY = | VOUT| –1.234V 83.5µA Step 12: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the effective ESR.

Table 4. Negative Boost Design Equations Step 1: Inputs Pick VIN, VOUT, IOUT, and f to calculate equations below.

• (1–DCMAX) Step 5: R SENSE2 RSENSE2 = 0.05 1.6 •IOUT Step 6: L LTYP = RSENSE1 •| VIN(MIN)| • DCMAX 12.5mV • f (1) LMIN ≥ RSENSE1 •|VIN(MIN)|•(2DCMAX–1)/(1–DCMAX) f • 40mV • DCMAX (2) LMAX ≤ RSENSE1 • |VIN(MIN)| • DCMAX 3mV • f (3)
• Solve equations 1 to 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors. Step 7: C1 C1≥10µF TYPICAL;V RATING> |VOUT|( ) Step 8: COUT COUT ≥ 1– DCMIN 8 •L • f2•0.005 Step 9: CIN CIN ≥ DCMAX 8 •L • f2•0.005 Step 10: CIMON CIMON ≥ 100µA •DCMAX 0.005• f Step 11: RFBY RFBY = | VOUT| –1.234V 83.5µA Step 12: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The C OUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR.

Figure 8. Negative Boost Converter – The Component Values Output Boost Topology Using Coupled Inductors. voltage ripple due to inductor L2 in series with the output. the design equations presented in Table 4.

8709 F08

8709 F09

regulation voltage and current. voltage or to create an undervoltage lockout function. pin high to prevent reverse current flow. Figure 9. Configurable UVLO much higher than the EN/FBIN pin current. lockout if the LT8709 is NOT in forced continuous mode. be accompanied by a soft-start. must exceed 1.7V (typical) to begin a soft-start cycle. can be used to monitor and/or limit the output current.

1. If it is not desirable to monitor and limit the output

should follow the guidelines in the next couple sections.

limiting or monitoring isn’t required. current is limited to about half its set value. Figure 10. Output Current Monitor and Control

8709 F10

the inductor current will start going more positive. –VIN from going below the OVP point. such as SuperCaps, the charging current is set by RSENSE2. operating duty cycle in the plot mentioned).

• 1–DCMAX( ) • 1– iRIPPLE   where η = Conversion efficiency (assume ~90%) VCSPN = Max current limit voltage (see Max Current Limit vs Duty Cycle (CSP-CSN) plot in the Typical Performance Characteristics) IOUT = Converter load current DCMAX = Switching duty cycle at minimum magnitude VIN (see Power Switch Duty Cycle in Appendix) iRIPPLE = Peak-to-peak inductor ripple current percent- age at minimum magnitude VIN (recommended to use 25%) applicaTions inForMaTion

Figure 11. Input Overvoltage Protection

8709 F11

8709f For more information www.linear .com/L T8709 CURRENT SENSE FIL TERING Certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across R SENSE1 and/or RSENSE2. Higher operating voltages, higher values of R SENSE, and more capacitive MOSFETs will all contribute additional noise across R SENSE when MOSFETs transition. The CSP/CSN and/or the ISP/ISN sense signals can be filtered by add- ing one of the RC networks shown in Figure 12. The filter shown in Figure 12a filters out differential noise, whereas the filter in Figure 12b filters out differential and common mode noise at the expense of an additional capacitor and approximately twice the capacitance value. It is recom - mended to Kelvin the –VIN cap connection directly to the paddle of the LT8709 if using the filter in Figure 12b. The filter network should be placed as close as possible to the LT8709. Resistors greater than 10Ω should be avoided as this can increase the offset voltages at the CSP/CSN and ISP/ISN pins. The RC product should be kept less than 30ns, which is simply the total series R (5.1Ω+5.1Ω in this case) times the equivalent capacitance seen across the sense pins (2.2nF for Figure 12a and 2.35nF for Figure 12b). SWITCHING FREQUENCY The LT8709 runs with a constant frequency between 100kHz and 750kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switch- ing losses. To use the on-chip oscillator, the switching frequency can be set by placing an appropriate resistor from the RT pin to –V IN, the chip ground and tying the SYNC pin to –VIN, the logic low. The frequency can also be synchronized to an external clock source driven into the SYNC pin, as long as the logic levels appearing at the SYNC pin are relative to the chip ground (i.e., –VIN). The following sections provide more details. Oscillator Timing Resistor (RT) The operating frequency of the LT8709 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to –VIN. The oscillator frequency is calculated using the following formula: fOSC= 35,880 RT +1( ) where fOSC is in kHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in kHz) using: RT = 35,880 fOSC Clock Synchronization With proper logic levels, an external source can set the operating frequency for LT8709 by providing a digital clock signal into the SYNC pin (RT resistor still required). That way, the LT8709 will operate with this overriding SYNC clock frequency. The LT8709 will revert to its internal free- running oscillator clock when the SYNC pin is driven to logic low, i.e., below 0.4V for a few free-running clock periods. applicaTions inForMaTion Figure 12a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins Figure 12b. Differential and Common Mode RC Filter on CSP/ CSN and/or ISP/ISN Pins

8709 F012a

RSENSE1, RSENSE2 2.2nF 5.1/uni03A9 5.1/uni03A9 CSP OR ISP L T8709 CSN OR ISN

8709 F012b

RSENSE1, RSENSE2 –VIN 4.7nF 5.1/uni03A9 5.1/uni03A9 CSP OR ISP L T8709 CSN OR ISN 4.7nF

8709fFor more information www.linear .com/L T8709 Driving SYNC high, i.e., ≥1.5V for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT8709 will stop. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 100kHz to 750kHz. 2. The SYNC frequency can always be higher than the free- running oscillator frequency (as set by the RT resistor), fOSC, but should not be less than 75% of fOSC. After SYNC begins toggling, it is recommended that switch- ing activity is stopped before the SYNC pin stops toggling. Excess negative inductor current can result when SYNC stops toggling as the LT8709 transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving the EN/FBIN pin low. LEVEL SHIFTER CIRCUITS It is often the case that the user has a GND referenced signal and would like to be able to externally control the part. This could include using a signal to enable the part, read the logic state of power good (PG), or to sync the part to a clock. The following circuits below level shift the input signal with respect to –VIN to achieve these functions. LDO REGULATORS The LT8709 has two linear regulators to run the BG and TG gate drivers. The INTVCC LDO regulates to 6.3V (typical) above the –V IN pin, and the INTV EE regulator regulates 6.18V (typical) below the BIAS pin. INTVCC LDO Regulator The INTVCC LDO is used as the top rail for the BG gate driver of the primary switch, which is an N-type power MOSFET with its source connected to the chip ground (i.e., –VIN) in any applications of the LT8709. The INTVCC LDO is also used as the top rail for the TG gate driver for applications in which BIAS and INTVEE are tied to INTVCC and –VIN, respectively. An external capacitor of 2.2µF or greater must be placed from the INTVCC pin to –VIN. The UVLO threshold on INTVCC is 4V (typical), and the LT8709 will be in reset until the LDO comes out of UVLO. applicaTions inForMaTion

8709 F013a

EN/FBIN_EXT L T8709 –VIN –VIN 20k

8709 F013b

SYNCSYNC_EXT GND L T8709 –VIN –VIN 100k 0.1µF

8709 F013c

–VIN VDD –VIN 200k 20k 10k 100k PG Figure 13a. Level Shifter Circuit for EN/FBIN Figure 13b. Level Shifter Circuit for SYNC Figure 13c. Level Shifter Circuit for PG

noted that all voltages in the plot are relative to –VIN. 175°C (typical), the current limit of the LDO drops to 0. improve efficiency and prevent overheating of the LT8709. Figure 14. INTVCC Input Voltage Selection

1. The converter’s switching-node voltage (|V IN| for

INTVEE regulator comes out of UVLO. to limit the maximum power in the INTV EE pass device. 175°C (typical), the current limit of the LDO drops to zero. section apply to the INTVEE regulator as well.

8709 F14

the same concept can be used for any other converter.

• To optimize thermal per formance, solder the exposed pad of the LT8709 to the chip ground plane (i.e., –VIN) with multiple vias around the pad connecting to ad- ditional –VIN planes.
• High speed switching path (see specific topology below for more information) must be kept as short as possible.
• The FBY, V C, IMON, and RT components should be placed as close to the LT8709 as possible, while being far away as practically possible from switching nodes. The –VIN node/plane for these components should be separated from the switch current path.
• Place bypass capacitors for the GND and BIAS pins (CGND and CBIAS) as close as possible to the LT8709.
• Place bypass capacitors for the INTVCC and INTVEE pins (CVCC and CVEE) as close as possible to the LT8709.
• The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. applicaTions inForMaTion

Figure 15. Nonsynchronous Negative Buck-Boost

8709 F15

8709f For more information www.linear .com/L T8709 Negative Inverting Topology Specific Layout Guidelines

• Keep length of loop (high speed switching path) govern- ing CIN2, RSENSE1, MN, MP, RSENSE2, COUT1, and return through ground as short as possible to minimize parasitic inductive spikes at the switch node during switching. Negative Buck-Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov- erning CIN, RSENSE1, MN, C1, MP, RSENSE2, and return through ground as short as possible to minimize parasitic inductive spikes at the switch node during switching. applicaTions inForMaTion Negative Buck Topology Specific Layout Guidelines Keep length of loop (high speed switching path) govern- ing RSENSE1, MN, MP, CIN and return through –VIN as short as possible to minimize parasitic inductive spikes at the switch node during switching. Figure 16c. Negative Buck-Boost PCB Layout Figure 16a. Inverting Converter PCB Layout Figure 16b. Negative Buck Converter PCB Layout LT8709

8709 F16a

VOUT–VIN COUT1 CIN1 COUT2 RSENSE2RSENSE1 GND CIN2 GND GND MPMN LT8709 RSENSE1 –VIN RSENSE2 CIN CIN COUT –VOUT

8709 F16b

8709 F16c

–VOUT –VIN CIN RSENSE2RSENSE1 MN MP GND GND

Figure 17. Suggested Routing and Connections of CSP/CSN

• Keep length of loop (high speed switching path) govern- ing RSENSE1, MN, C1, MP, RSENSE2, and return through –VIN as short as possible to minimize parasitic inductive spikes at the switch node during switching. LT8709

8709 F16d

• Place the vias that connect to CSP/CSN and ISP/ISN lines directly at the inner current sense pads of the current sense resistors as shown in Figure 17. THERMAL CONSIDERATIONS Overview The components on the board that dissipate the most heat are the power switches, (i.e., MN and MP), the power inductor, and the LT8709 IC. It is imperative that a good thermal path be provided for these components to dissipate the heat generated within the packages. This can be accomplished by taking advantage of the thermal pads on the underside of the packages. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from each of these components and into a copper plane with as much area as possible. For the case of the power switches, the copper area of the drain connections shouldn’t be too big as to create a large EMI surface that can radiate noise around the board. Power MOSFET Loss and Thermal Calculations The LT8709 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. Important parameters for estimating the power dissipation in the MOSFETs are: 1. On-resistance (RDSON) 2. Gate-to-drain charge (QGD) 3. PFET body diode forward voltage (VBD) 4. VDS of the FETs during their Off-Time 5. Switch current (ISW) 6. Switching frequency (f) The power loss in each power switch has a DC and AC term. The DC term is when the power switch is fully on, and the AC term is when the power switch is transitioning from on-off or off-on. The following applies for both the NFET and PFET power switches. For a negative buck converter, the average cur- rent through the MOSFET (I SW) during its on-time is the same as the average output current; and the magnitude of the drain-to-source voltage, V DS, during its off-time is |VIN|. For a negative buck-boost or inverting or boost application, the average current through each MOSFET (ISW) during its on-time, is the sum of the average input current and the output current. The |VDS| voltage during the off-time is approximately |V IN| + |V OUT|. During the

8709 F17

8709f For more information www.linear .com/L T8709 non-overlap time of the gate drivers, the peak and valley inductor current is flowing through the body diode of the PFET. Given below are the equations for the power loss in MN and MP. PMOSFET =PI2R+PSWITCHING PMN=IN2 •RDSON+ VDS •IN • f • tRF +PRR – N PMP =IP2 •RDSON+VBD• IPK+ IVY 1.6   ISW = IOUT (1–DC); I PK =ISW+ iRIPPLE 2 ; I VY =ISW – iRIPPLE IN= DC • ISW2+ iRIPPLE2   IP = 1–DC( ) • ISW2+ iRIPPLE2   PRR – N≈ VDS •IRR • tRR • f PRR – P≈ VDS •IRR • tRR • f where: f = Switching Frequency IN = NFET RMS Current IP = PFET RMS Current tRF = Average of the rise and fall times of the NFET’s drain voltage ISW = Average switch current during its on-time IPK = Peak inductor current IVY = Valley inductor current iRIPPLE = Inductor ripple current DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) VBD = PFET body diode forward voltage at ISW PRR-N = NFET I2R loss term from the PFET body diode reverse recovery PRR-P = PFET body diode reverse recovery power loss IRR = Current needed to remove the PFET body diode charge tRR = Reverse recovery time of PFET body diode applicaTions inForMaTion Typical values for tRF are 10ns to 40ns depending on the MOSFET capacitance and drain voltage. In general, the lower the QGD of the MOSFET, the faster the rise and fall times of its drain voltage. For best calculations, measure the rise and fall times in the application. PFET body diode reverse recovery power loss is depen- dent on many factors and can be difficult to quantify in an application. In general, this power loss increases with higher VDS and/or higher switching frequency. Chip Power and Thermal Calculations Power dissipation in the LT8709 chip comes from three primary sources: the INTVCC LDO, INTVEE LDO, and input quiescent current. The average current through each LDO is determined by the gate charge of the power switches, MN and MP, and the switching frequency. Given below are the equations for calculating the chip power loss fol- lowed by examples. Negative Buck, Buck-Boost and Inverting Converters: The INTVCC LDO primarily supplies voltage for the BG gate driver. The BIAS and INTVEE voltages supply the top and bottom rails of the TG gate driver respectively. The chip Q current comes from the higher of GND and BIAS, referred to –VIN. Given below are the chip power equations for a negative buck, buck-boost or inverting converter: PVCC = 1.04 • QMN • f • VSELECT PVEE1 = QMP • f • VBIAS PVEE2 = 3.1mA • (1 – DC) • VBIAS PQ = 4mA • VMAX where: f = Switching frequency DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) QMN = Total gate charge of NFET power switch (MN) at 6.3VGS QMP = Total gate charge of PFET power switch (MP) at 6.18VSG VSELECT = INTVCC LDO selected input voltage, GND or BIAS (see LDO REGULATORS section) VMAX = Higher of GND and BIAS.

junction to the ambient air. suggestions in the Layout Guidelines section. Table 5. Power Calculations Example for a 250kHz, –16VIN to –30VIN to –12VOUT/8.5A Buck (–VIN = –24V, MN = BSC026N04LS

• 100% where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is a maximum of 480ns. Conversely, the external power NFET (MN in the Block Diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum al- lowable duty cycle given by: DCMIN = (MinOnTime) TP
• 100% where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is a maximum of 420ns. The application should be designed such that the operating duty cycle is between DC MIN and DCMAX. Duty cycle equations for several common topologies are given below where VMP_ON is the voltage drop across the external power PFET (MP) when it is on, and V MN_ON is the voltage drop across the external power NFET (MN) when it is on. For the negative buck topology (see Figure 5): For the negative inverting topology (see Figure 6): DC –INVERTER ≅ VOUT+ VMP_ON | VIN|+VOUT+ VMP_ON– VMN_ON For the negative buck-boost topology (see Figure 7): DC –BUCK–BOOST ≅ | VOUT|+VMP_ON For the negative boost topology (see Figure 8): | VOUT|+VMP_ON+ VMN_ON The LT8709 can be used in configurations where the duty cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode (MODE pin must be high) so that the effective duty cycle is reduced. INDUCTOR SELECTION For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturat- ing. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the negative buck-boost topology where each inductor carries a fraction of the total switch current. Molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5A to 15A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 6 for a list of inductor manufacturers.

Table 6. Inductor Manufacturers current to avoid false tripping of the current comparator.

8709fFor more information www.linear .com/L T8709 appenDix Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: 2• f • VCSPN RSENSE1 –IOUT   2• f • VCSPN RSENSE1 – | VOUT|•IOUT |VIN|• η –IOUT 2• f • VCSPN RSENSE1 – | VOUT|• IOUT |VIN|• η –IOUT 2• f • VCSPN RSENSE1 – | VOUT| • IOUT |VIN| • η –IOUT where… L-BUCK or L-INVERTER = L1 for the negative buck or invert- ing topologies (see Figures 5 and 6) L-BUCK-BOOST or L -BOOST = L 1 = L 2 for coupled dual inductor topologies (see Figures 7 and 8) L -BUCK-BOOST or L-BOOST = L1 || L2 for uncoupled dual inductor topologies (see Figures 7 and 8) DC = Switch duty cycle (see previous section) V CSPN = Current limit voltage at the operating switch duty cycle (see Max Current Limit vs Duty Cycle (CSP – CSN) plot in the Typical Performance Characteristics) R SENSE1 = Current sense resistor connected across the CSP-CSN pins (see Block Diagram) η = Power conversion efficiency (assume ~90%) f = Switching frequency I OUT = Maximum output current Negative values of inductance from above equations’ indicate that the output load current, I OUT, exceeds the switch current limit capability of the converter. Decrease RSENSE1 to increase the switch current limit. Avoiding Sub-Harmonic Oscillations The LT8709’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the in - ductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: 40m•DC• f •(1–DC) f • 40mV •DC where… LMIN = L 1 for single inductor topologies (see Figures 5 and 6). Note: for the negative buck, |V IN| – |V OUT| replaces |VIN|. LMIN = L 1 = L 2 for coupled dual inductor topologies (see Figures 7 and 8) LMIN = L1 || L2 for uncoupled dual inductor topologies (see Figures 7 and 8) Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A5 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX ≤ | VIN| • RSENSE1•DC 3mV • f FOR NEGATIVE BOOST, BUCK-BOOST AND INVERTING CONVER TERS FOR NEGATIVE BUCK CONVERTERS

or negative boost topologies with a few requirements. adjusted if RDAMP cannot be made below or close to 3Ω.

1. Gate threshold voltage (VGSTH)
2. Turn-off delay time (tD(OFF))
3. Package has exposed paddle as heat sink

Figure 18. RC Damp Network for Single Inductors

8709 F018

• BVDSS > |VIN| for negative buck converters
• BVDSS > |VIN| + |VOUT| for negative boost, buck-boost, or inverting converters If operating close to the BVDSS rating of the MOSFET, check the leakage specifications on the MOSFET because leakage can decrease the efficiency of the converter. The NFET and PFET gate-to-source drive is approximately 6.3V and 6.18V respectively, so logic level MOSFETs are required. The BG gate driver can begin switching when the INTV CC voltage exceeds ~4V, so ensure the selected NFET is in the triode region of operation with 4V of gate- to-source drive to prevent possible damage to the NFET. The TG gate driver can begin switching when the BIAS- INTVEE voltage exceeds ~3.42V, so it is optimal that the PFET be in the triode region of operation with 3.42V of gate-to-source drive. However, the PFET is less likely to be damaged if it’s not operating in the triode region since the drain-to-source voltage is clamped by its body diode during the NFET’s off-time. Having said that, try to choose a PFET with a low body diode reverse recovery time to minimize stored charge in the PFET. The stored charge in the PFET body diode is removed when the NFET switch turns on and can lead to a reduction in efficiency especially in applications where the VDS of the PFET (during off-time) is high. For these applications, it may be beneficial to put a Schottky diode across the PFET to reduce the amount of charge in the PFET body diode. In applications where the output voltage is high in magnitude, it is recommended to replace the PFET with a Schottky diode since the converter may be more efficient. Power MOSFET on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher total gate charge. Choose MOSFETs with an on-resistance to give a voltage drop to be less than 300mV at the peak current. At the same time, choose MOSFETs with a lower total gate charge to reduce LT8709 power dissipation and MOSFET switching losses. The turn-off delay time (t D(OFF)) of available NFETs is generally smaller than the LT8709’s non-overlap time. However, the turn-off time of the available PFETs should be checked before deciding on a PFET for a given applica- tion. The turn-off time must be less than the non-overlap time of the LT8709 or else the NFET and PFET could be on at the same time and damage to external components may occur. If the PFET turn-off delay time as specified in the data sheet is less than the LT8709 non-overlap time, then the PFET is good to use. If the turn-off delay time is longer than the non-overlap time, it doesn’t necessarily mean it can’t be used. It may be unclear how the PFET manufacturer measures the turn-off delay time, so it is best to measure the PFET turn-off delay time with respect to the PFET gate voltage. Finally, both the NFET and PFET power MOSFETs should be in a package with an exposed paddle for the drain connection to be able to dissipate heat. The on-resistance of MOSFETs is proportional to temperature, so it’s more efficient if the MOSFETs are running cool with the help of the exposed paddle. See Table 7 for a list of power MOSFET manufacturers.

Table 7. Power MOSFET (NFET and PFET) Manufacturers Table 8. Recommended PFETs

SUN-CON and POSCAP are also available. reduced capacitance at the desired operating voltage. the equivalent ESR of the input capacitor(s). for a list of ceramic capacitor manufacturers. Table 9. Ceramic Capacitor Manufacturers

8709fFor more information www.linear .com/L T8709 Figure 19c. T ransient Response is Well Damped Figure 19a. T ransient Response Shows Excessive Ringing Figure 19b. T ransient Response is Better appenDix –VIN. For most applications, choose a series capacitor in the range of 1nF to 10nF with 4.7nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 220pF with 100pF being a good starting value. The compensation resistor, R C, is usually in the range of 5k to 50k. A good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor RC. With the series and parallel capacitors at 2.2nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for R C can be found. Figures 19a to 19c illustrate this process for the circuit of Figure 22 with a load cur- rent stepped between 3A and 8A. Figure 19a shows the transient response with RC equal to 208Ω. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 19b, the value of RC is increased to 1.5k, which results in a more damped response. Figure 19c shows the results when RC is increased further to 5.9 k. The transient response is nicely damped and the compensation procedure is complete. COMPENSATION – THEORY Like all other current mode switching regulators, the LT8709 needs to be compensated for stable and efficient operation. Tw o feedback loops are used in the LT8709: a fast current loop which does not require compensation, and a slower voltage loop which does. Standard bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 20 shows the key equivalent elements of a negative buck converter where –V IN is treated as the signal ground. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and a current controlled current source Gmp acts as a current source where the peak input current, I OUT, is proportional to the VC voltage and current sense resistor, RSENSE1. Note that the maximum output currents of g mp and gma are finite. The external current sense resistor, R SENSE1, sets the value of: gmp ≈ 1 6 •RSENSE1 RC = 208/uni03A9 ILOAD 5A/DIV VOUT 500mV/DIV AC-COUPLED IL 5A/DIV 200µs/DIV

8709 F19a

RC = 1.5k/uni03A9 ILOAD 5A/DIV VOUT 500mV/DIV AC-COUPLED IL 5A/DIV 200µs/DIV

8709 F19b

RC = 5.9k/uni03A9 ILOAD 5A/DIV VOUT 500mV/DIV AC-COUPLED IL 5A/DIV 200µs/DIV

8709 F19c

Figure 20. Negative Buck Converter Equivalent Model

8709 F20

• gm,Q1•R2 / 2 Output Pole:P1= 1 2• π •RL •COUT Error Amp Pole:P2= 1 2• π •(RO+RC)•CC Error Amp Zero: Z1= 1 2• π •RC•CC ESR Zero: Z2= 1 2• π •RESR •COUT Phase Lead Zero: Z3= 1 2• π •RFBY1•CPL Phase LeadPole:P4= 1 2• π •RFBY2|| 1 gm(Q1)
• CPL Error Amp Filter Pole:P5= 1 2• π • RC •RO RC+RO
• CF ,CF < CC RHP Zero: Z4= VIN2 •RL 2• π • VOUT2 •L The current mode zero (Z3) which exists for the inverting and dual inductor topologies only, is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection.

Figure 21. Bode Plot for Example Negative Buck Converter Figure 22. Negative Buck Converter

8709 F22

8709 F21

8709f For more information www.linear .com/L T8709 Typical applicaTion 250kHz, –16V to –30V Input to –12V Output, Negative Buck Converter Delivers Up to 8.5A Output Current Efficiency and Power Loss vs Load Current (–VIN = –24V) T ransient Response with 3A to 8A to 3A Output Load Step (–V IN = –24V) IMON SS–VIN CSPTG CSN BG L T8709

8709 TA02a

–12V 8.5A –VIN –VIN –16V TO –30V 7.3µHMP RSENSE2 4m/uni03A9 RSENSE1 2m/uni03A9 MN CIN1 120µF 2.2µF COUT1 22µF 33k 4.99k10k 2.2µF CIN2 10µF L1: WÜRTH-HCI, 7.3µH, 7443551730 MP: FAIRCHILD, FDD4141 MN: INFINEON, BSC026N04LS R SENSE1: 2m/uni03A9, 2512 RSENSE2: 4m/uni03A9, 2512 CIN1: 0SCON, 35V , 120µF , 35SVPF120M CIN2: 50V , 10µF , X7S, 1210 COUT1: 25V , 22µF , X7R, 1812 COUT2: OSCON, 16V , 150µF , 16SEQP150M 143k 100k 62.5k 5.9k COUT2 150µF+ 68nF 470nF 2.2nF 100pF 2.2µF 2.2µF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 4.5 3.5 4.0 2.5 1.5 3.0 2.0 1.0 0.5 52 7 8 9

8709 TA02b

200µs/DIV 8709 TA02c

8709fFor more information www.linear .com/L T8709 Typical applicaTion Split Supply Input Generates 5V with Up to 10A Output Current Efficiency and Power Loss vs Load Current (VIN = ±12V) T ransient Response with 3A to 8A to 3A Output Load Step (V IN = ±12V) LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 52 7 8 10 9

8709 TA03b

100µs/DIV 8709 TA03c IMON SS CSPBG CSN TG L T8709

8709 TA03a

VIN(NEG) = –12V ±10% VIN(NEG) VIN(NEG) 3.5µH RSENSE2 3m/uni03A9 10µF ×2 VIN(POS) = 12V ±10% 2.2µF COUT1 100µF 10k CIN1 22µF CIN2 22µF 143k 100k 2m/uni03A9 MN 93.1k RSENSE1 60.4k 10/uni03A9 10/uni03A9 MP ×2 14.3k COUT2 330µF 47nF 220nF 2.2nF 100pF 2.2µF 2.2µF L1, L2: WÜRTH-CFWI, 3.5µH, 74485540350 MN: INFINEON, BSC059N04LSG MP: FAIRCHILD, FDD4141 R SENSE1: 2m/uni03A9, 2512 RSENSE2: 3m/uni03A9, 2512 CIN1: 22µF , 25V , 1812, X7R CIN2: 22µF , 25V , 1812, X7R C1: 10µF , 25V , 1210, X7R C OUT1: 100µF , 16V , 1210, X5R COUT2: OSCON, 16V , 330µF , 16SEQP330M –VIN 4.7nF 4.7nF 3.5µH DC= VOUT VIN(POS)+| VIN(NEG) |+VOUT FET BVDSS> VIN(POS)+| VIN(NEG) |+VOUT C1VRATING >VIN(POS)

8709f For more information www.linear .com/L T8709 Typical applicaTion 200kHz, –4.5V to –42V Input to 5V/4A Output Negative Inverting Converter Efficiency and Power Loss vs Load Current T ransient Response with 1.5A to 4A to 1.5A Output Load Step (–V IN = –5V) IMON SS–VIN CSP TG CSNBG L T8709

8709 TA04

–VIN –4.5V TO –42V –VIN 4.7µH MN RSENSE1 RSENSE2 8m/uni03A9MP 2.2µF COUT1 100µF 10k 2.2µF CIN 10µF 330µF 178k 100k 1.5m/uni03A9 4.99k 60.4k 16.9k COUT2 330µF 68nF 470nF 3.3nF 100pF 2.2µF L1: WÜRTH-HCI, 4.7µH, 7443551470 MP: VISHAY, SUD50P06 MN: FAIRCHILD, FDMS86500L R SENSE1: 1.5m/uni03A9, 2512 RSENSE2: 8m/uni03A9, 2512 CIN1: 10µF , 50V , 1206, X5R COUT1: 100µF , 6.3V , 1812, X5R COUT2: OSCON, 16V , 330µF , 16SEQP330M 2.2µF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100

8709 TA04b

–VIN = –12V –VIN = –12V –VIN = –5V –VIN = –5V ILOAD 2A/DIV VOUT 200mV/DIV AC-COUPLED IL 5A/DIV 200µs/DIV 8709 TA04c

8709fFor more information www.linear .com/L T8709 Typical applicaTion 400kHz, Negative Buck-Boost Converter Generates a –24V/2.5A Output from a –15V to –30V Input Efficiency and Power Loss vs Load Current T ransient Response with 1A to 2.5A to 1A Output Load Step (–V IN = –24V) IMON SS CSP TGCSNBG L T8709

8709 TA05

–24V 2.5A –VIN –15V TO –30V –VIN 15.4µH RDAMP CDAMP 10µF MN D1 220µF 2.2µF COUT1 10µF L1, L2: WÜRTH-HCI, 15.4µH, 7443551151 MN: INFINEON, BSC039N06NS D1: DIODES INC, SBR12U100P5 R SENSE1: 3m/uni03A9, 2512 RSENSE2: 13m/uni03A9, 2512 CIN: 50V , 10µF , X7R, 1210 C1: 50V , 10µF , X7R, 1210 R DAMP: 2.2/uni03A9, 0805 CDAMP: 50V , 10µF , X7R, 1210 COUT1: 50V , 10µF , X7R, 1210 10k 4.7µF CIN 10µF 88.7k 100k RSENSE1 3m/uni03A9 54.9k RSENSE2 13m 274k 15.4µH 60.4k COUT2 330µF 68nF 470nF 3.3nF 100pF 2.2µF 4.7µF 10µF ×32.2/uni03A9 –VIN LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100

8709 TA05b

2 1.5 2.50.5 –VIN = –15V –VIN = –15V –VIN = –24V –VIN = –24V ILOAD 2A/DIV VOUT 500mV/DIV AC-COUPLED IL1 + IL2 5A/DIV 500µs/DIV 8709 TA05c

8709f For more information www.linear .com/L T8709 Typical applicaTion High Power 300kHz, Negative Boost Converter Generates a –12V/4.5A Output from a –4.5V to –9V Input Efficiency and Power Loss vs Load Current (–VIN = –5V) T ransient Response with 2A to 4A to 2A Output Load Step (–V IN = –5V) IMON SS–VIN CSP TG CSNBG L T8709

8709 TA06a

–12V 4.5A –VIN –4.5V TO –9V –VIN 2.2µH MPMN CIN1 330µF 2.2µF COUT1 100µF 10k 2.2µF CIN2 100µF 118k 100k 2m/uni03A9 13.3k RSENSE1 2.2µH 130k 37.4k RSENSE2 7m/uni03A9 COUT2 330µF+ 68nF 470nF 2.2nF 100pF 2.2µF 22µF –VIN 0.47µF 499/uni03A9 L1, L2: WÜRTH-CFWI, 2.2µH, 74485540220 MN: INFINEON, BSC0901NSI MP: VISHAY, Si7143DP R SENSE1: 2m/uni03A9, 2512 RSENSE2: 7m/uni03A9, 2512 D1: ON-SEMI, MBRM110 C IN1: OSCON, 16V , 330µF , 16SEQP330M CIN2: 100µF , 16V , X5R, 1210 C1: 25V , 22µF , X7R, 1812 C OUT1: 100µF , 16V , X5R, 1210 COUT2: OSCON, 16V , 330µF , 16SEQP330M LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 1 1.5 2

8709 TA06b

3 3.5 42.5 4.50.5 ILOAD 2A/DIV VOUT 200mV/DIV AC-COUPLED IL1 + IL2 5A/DIV 200µs/DIV 8709 TA06c

8709fFor more information www.linear .com/L T8709 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. FE20 (CB) TSSOP REV K 0913 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 DETAIL A DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CB DETAIL A 0.60 (.024) REF 0.28 (.011) REF package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

8709f For more information www.linear .com/L T8709 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T8709  LINEAR TECHNOLOGY CORPORATION 2015 LT 0115 • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V IN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V IN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3759 Boost, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, 100kHz to 1MHz Programmable Operating Frequency, LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch 3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LT3958 Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 84V Switch 5V ≤ V IN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LT3959 Boost, SEPIC and Inverting Converter with 6A, 40V Switch 1.6V ≤ V IN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LT8710 Synchronous SEPIC/Inverting/Boost Controller with Output Current Control 4.5V ≤ V IN ≤ 80V, Rail to Rail Output Current Monitor and Control, C/10 or Power Good 250kHz, Wide Input Range, Buck-Boost Converter Generates a –5V Output with Up to 7A Output Current Efficiency and Power Loss vs Load Current T ransient Response with 2.5A to 6.5A to 2.5A Output Load Step (–V IN = –12V) LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 2 3

8709 TA07b

–VIN = –5V –VIN = –12V –VIN = –12V–VIN = –5V IMON SS–VIN CSP TGCSNBG L T8709

8709 TA07a

–5V –VIN –4.5V TO –25V –VIN 3.5µH MP MN 330µF 2.2µF C OUT1 100µF 10k 2.2µF CIN 10µF 143k 100k 1.5m/uni03A9 13.3k RSENSE1 RSENSE2 5m/uni03A9 3.5µH 45.3k 11k COUT2 330µF+ 68nF 470nF 3.3nF 100pF 10µF ×2 2.2µF 2.2µF L1, L2: WÜRTH-CFWI, 3.5µH, 74485540350 MP: FAIRCHILD FDD4141 MN: INFINEON, BSC026N04LS R SENSE1: 1.5m/uni03A9, 2512 RSENSE2: 5m/uni03A9, 2512 CIN: 50V , 10µF , X7R, 1210 C1: 50V , 10µF , X7R, 1210 C OUT1: 16V , 100µF , X5R, 1210 COUT2: OSCON, 16V , 330µF , 16SEQP330M ILOAD 5A/DIV VOUT 200mV/DIV AC-COUPLED IL1 + IL2 5A/DIV 200µs/DIV 8709 TA07c