LT8580_15 LINER
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Technical content
For more information www.linear .com/L T8580 Typical applicaTion
FeaTures
applicaTions
DescripTion
DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization The LT®8580 is a PWM DC/DC converter containing an internal 1A, 65V switch. The LT8580 can be configured as either a boost, SEPIC or inverting converter. The LT8580 has an adjustable oscillator, set by a resistor from the RT pin to ground. Additionally, the LT8580 can be synchronized to an external clock. The switching frequency of the part may be free running or synchronized, and can be set between 200kHz and 1.5MHz. The LT8580 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjust- able under voltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT8580 is available in tiny thermally enhanced 3mm × 3mm 8-lead DFN and 8-lead MSOP packages. 1.5MHz, 5V to 12V Boost Converter n 1A, 65V Power Switch n Adjustable Switching Frequency n Single Feedback Resistor Sets VOUT n Synchronizable to External Clock n High Gain SHDN Pin Accepts Slowly Varying Input Signals n Wide Input Voltage Range: 2.55V to 40V n Low VCESAT Switch: 400mV at 0.75A (Typical) n Integrated Soft-Start Function n Easily Configurable as a Boost, SEPIC, or Inverting Converter n User Configurable Undervoltage Lockout (UVLO) n Pin Compatible with LT3580 n Tiny Thermally Enhanced 8-Lead 3mm × 3mm DFN and 8-Lead MSOP Packages n VFD Bias Supplies n TFT-LCD Bias Supplies n GPS Receivers n DSL Modems n Local Power Supply Efficiency and Power Loss L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners . Protected by U.S. Patents , including 7579816. LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 100 100
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4.7µF VOUT 12V 200mA 15µH 130k V IN VIN SW
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6.04k 56.2k SHDN GND FBX VCSYNC SSRT 3.3nF 47pF 0.22µF 2.2µF
For more information www.linear .com/L T8580 absoluTe MaxiMuM raTings 4V to 65V 3V to 5V 3V to 2.5V V VC 3V to 2V (Note 1) TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN GND
1 FBX
V IN SW SYNC SS RT SHDN θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB FBX VC V IN SW SYNC SS RT SHDN TOP VIEW GND MS8E PACKAGE 8-LEAD PLASTIC MSOP θJA = 35°C/W TO 40°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB pin conFiguraTion orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8580EDD#PBF LT8580EDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT8580IDD#PBF LT8580IDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT8580HDD#PBF LT8580HDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C LT8580EMS8E#PBF LT8580EMS8E#TRPBF L TGKJ 8-Lead Plastic MSOP –40°C to 125°C LT8580IMS8E#PBF LT8580IMS8E#TRPBF L TGKJ 8-Lead Plastic MSOP –40°C to 125°C LT8580HMS8E#PBF LT8580HMS8E#TRPBF L TGKJ 8-Lead Plastic MSOP –40°C to 150°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3V to 5.5V Operating Junction Temperature Range LT858 0°C to 125°C
For more information www.linear .com/L T8580 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8580E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8580I is guaranteed over the full –40°C to 125°C operating junction temperature range. The LT8580H is guaranteed over the full –40°C to 150°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C. elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Voltage Range LT8580E, LT8580I LT8580H l l 2.55 2.9 V V Positive Feedback V oltage l 1.185 1.204 1.220 V Negative Feedback Voltage l –3 3 12 mV Positive FBX Pin Bias Current VFBX = Positive Feedback Voltage, Current Into Pin l 81 83.3 85 µA Negative FBX Pin Bias Current VFBX = Negative Feedback Voltage, Current Out of Pin l 81 83.3 86 µA Error Amplifier T ransconductance 200 µmhos Error Amplifier Voltage Gain 60 V/V Quiescent Current VSHDN = 2.5V, Not Switching 1.2 1.7 mA Quiescent Current in Shutdown VSHDN = 0V 0 1 µA Reference Line Regulation 2.5V ≤ VIN ≤ 40V 0.01 0.05 %/V Switching Frequency, fOSC RT = 56.2k RT = 422k l l 1.23 165 1.5 200 1.77 235 MHz kHz Switching Frequency in Foldback Compared to Normal fOSC 1/6 Ratio Switching Frequency Set Range SYNCing or Free Running l 200 1500 kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.4 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 35 65 % Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4 Minimum Off-Time 100 ns Minimum On-Time 350 ns Switch Current Limit Minimum Duty Cycle (Note 3) Maximum Duty Cycle (Notes 3, 4), fOSC = 1.5MHz Maximum Duty Cycle (Notes 3, 4), fOSC = 200kHz l l l 1.2 0.6 0.4 1.5 0.8 1.8 1.5 1.4 A A A Switch V CESAT ISW = 0.75A 400 mV Switch Leakage Current VSW = 5V 0.01 1 µA Soft-Start Charging Current VSS = 0.5V l 4 6 8 µA SHDN Minimum Input Voltage High Active Mode, SHDN Rising Active Mode, SHDN Falling l l 1.23 1.21 1.31 1.27 1.4 1.33 V V SHDN Input Voltage Low Shutdown Mode l 0.3 V SHDN Pin Bias Current VSHDN = 3V VSHDN = 1.3V VSHDN = 0V 0.1 µA µA µA SHDN Hysteresis 40 mV Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: Current limit measured at equivalent of listed switching frequency. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
For more information www.linear .com/L T8580 Typical perForMance characTerisTics Switch Current Limit vs Duty Cycle Switch Saturation Voltage Commanded Switch Current vs SS Switch Current Limit vs Temperature Positive and Negative Output Voltage Regulation Positive and Negative FBX Current at Output Voltage Regulation Oscillator Frequency T A = 25°C, unless otherwise specified DUTY CYCLE (%) SWITCH CURRENT LIMIT (A)0.50 0.75 0.25 1.00 1.25 1.50 1.75 30 50 70 90
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2.00 20 40 60 80 SWITCH CURRENT (A) SATURATION VOL TAGE (mV) 400 500 600 1.5
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0.5 0.25 0.75 1 1.25 100 700 SS VOL TAGE (V) SWITCH CURRENT (A)0.5 1.0 1.5 2.0 0.2 0.4 0.6 0.8
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1 1.2 TEMPERATURE (°C) –50 –25 SWITCH CURRENT LIMIT (A)0.5 1.0 1.5 2.0 0 50 25 125 150100 75
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TEMPERATURE (°C) –50 –25
1.170 POSITIVE FBX VOLTAGE (V)
NEGATIVE FBX VOLTAGE (mV) 1.200 1.220 0 50 75
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1.175 1.180 1.185 1.190 1.195 1.215 1.210 1.205 –20 –10 –15 25 100 150 125 TEMPERATURE (°C) –50 –25
80 POSITIVE FBX CURRENT INTO PIN (µA)
NEGATIVE FBX CURRENT OUT OF PIN (µA)86 0 50 75
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TEMPERATURE (°C) –50 –25 FREQUENCY (MHz) 0.8 1.0 1.2 1.4
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0.6 0.4 0 50 25 75 100 125 150 0.2 1.8 1.6 RT = 56.2k RT = 422k
For more information www.linear .com/L T8580 Typical perForMance characTerisTics SHDN Pin Current SHDN Pin Current Active/Lockout Threshold TA = 25°C, unless otherwise specified Oscillator Frequency During Soft-Start Internal UVLO FBX VOLTAGE (V) NORMALIZED OSCILLATOR FREQUENCY (F/FNOM) 0.2 0.4 INVERTING CONFIGURATIONS NONINVERTING CONFIGURATIONS 0.6 0.8
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1 1.2 TEMPERATURE (°C) –50 –25 2.1 VIN VOLTAGE (V) 2.2 2.7 2.4 2.3 0 50 25 75
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2.5 2.6 125 100 150 SHDN VOLTAGE (V) SHDN PIN CURRENT (µA)
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125°C 25°C –40°C SHDN VOLTAGE (V) SHDN PIN CURRENT (µA) 200 250 300 350 400 15 25
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125°C 25°C –40°C TEMPERATURE (°C) –50 –25
1.20 SHDN VOLTAGE (V)
1.22 1.26 1.28 1.30 1.40 1.34 0 50 75
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1.24 1.36 1.38 1.32 100 125 150 SHDN RISING SHDN FALLING
For more information www.linear .com/L T8580 pin FuncTions FBX (Pin 1): Positive and Negative Feedback Pin. For a noninverting or inverting converter, tie a resistor from the FBX pin to VOUT according to the following equations: RFBX = VOUT −1.204V( ) 83.3µA ; Noninverting Converter RFBX = VOUT + 3mV( ) 83.3µA ; Inverting Converter VC (Pin 2): Error Amplifier Output Pin. Tie external com- pensation network to this pin. VIN (Pin 3): Input Supply Pin. Must be locally bypassed. SW (Pin 4): Switch Pin. This is the collector of the internal NPN Power switch. Minimize the metal trace area connec- ted to this pin to minimize EMI. SHDN (Pin 5): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 1.21V to disable the chip. Drive above 1.40V to activate the chip and restart the soft-start sequence. Do not float this pin. RT (Pin 6): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 280k resistor to about 2.1V. SYNC (Pin 8): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less 0.4V. Drive this pin to less than 0.4V to revert to the internal free-running clock. See the Applications Information section for more information. GND (Exposed Pad Pin 9): Ground. Exposed pad must be soldered directly to local ground plane.
For more information www.linear .com/L T8580 block DiagraM 3 1.204V REFERENCE ADJUSTABLE OSCILLATOR FREQUENCY FOLDBACK SLOPE COMPENSATION COMPARATOR DISCHARGE DETECT SS VC 280k SR2 R S 14.5k 14.5k Q SR1 A4A1 SYNC RT SHDN FBX 1.3V VC SW 0.02/uni03A9 GND RT RFBX DRIVER ILIMIT VIN VOUT CSS CC CIN RC VIN SOFT- START SYNC BLOCK UVLO R S Q 8580 BD 50k
Figure 1. SEPIC Topology Allows for the Input to Span Figure 2. Dual Inductor Inverting Topology Results in
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- • RT RC CC The LT8580 uses a constant-frequency, current mode con- trol scheme to provide excellent line and load regulation. Refer to the Block Diagram for the following description of the part’s operation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switch, Q1. The switch current flows through the internal current sense resistor, generating a voltage proportional to the switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When this voltage exceeds the level at the negative input of A3, the SR latch is reset, turning off the power switch. The level at the negative input of A3 (VC pin) is set by the error amplifier A1 (or A2) and is simply an amplified version of the difference between the feedback voltage (FBX pin) and the reference voltage (1.204V or 3mV, depending on the configuration). In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. The LT8580 has an FBX pin architecture that can be used for either noninverting or inverting configurations. When configured as a noninverting converter, the FBX pin is pulled up to the internal bias voltage of 1.204V by the RFBX resistor connected from VOUT to FBX. Amplifier A2 becomes inactive and amplifier A1 performs the invert- ing amplification from FBX to VC. When the LT8580 is in an inverting configuration, the FBX pin is pulled down to 3mV by the R FBX resistor connected from V OUT to FBX. Amplifier A1 becomes inactive and amplifier A2 performs the noninverting amplification from FBX to VC. SEPIC Topology As shown in Figure 1, the LT8580 can be configured as a SEPIC (single-ended primary inductance converter). This topology allows for the input to be higher, equal, or lower than the desired output voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output. This is useful for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. Inverting Topology The LT8580 can also work in a dual inductor inverting topology, as shown in Figure 2. The part’s unique feedback pin allows for the inverting topology to be built by simply changing the connection of external components. This solution results in very low output voltage ripple due to the inductor L2 in series with the output. Abrupt changes in output capacitor current are eliminated because the output inductor delivers current to the output during both the off-time and the on-time of the LT8580 switch.
For more information www.linear .com/L T8580 Start-Up Operation Several functions are provided to enable a very clean start-up for the LT8580.
- First, the SHDN pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. An external resistor (or resistor divider) can be connected from the input power supply to the SHDN pin to provide a user-programmable undervoltage lockout function.
- Second, the soft-start circuitry provides for a gradual ramp-up of the switch current. When the part is brought out of shutdown, the external SS capacitor is first discharged (providing protection against SHDN pin glitches and slow ramping), then an integrated 280k resistor pulls the SS pin up to ~2.1V. By connecting an external capacitor to the SS pin, the voltage ramp rate on the pin can be set. Typical values for the soft-start capacitor range from 100nF to 1µF.
- Finally, the frequency foldback circuit reduces the switch- ing frequency when the FBX pin is in a nominal range of 300mV to 920mV. This feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. When the FBX voltage is pulled outside of this range, the switching frequency returns to normal. Current Limit and Thermal Shutdown Operation The LT8580 has a current limit circuit not shown in the Block Diagram. The switch current is constantly monitored and not allowed to exceed the maximum switch current at a given duty cycle (see the Electrical Characteristics table). If the switch current reaches this value, the SR latch (SR1) is reset regardless of the state of the comparator (A1/ A2). Also, not shown in the Block Diagram is the thermal shutdown circuit. If the temperature of the part exceeds approximately 165°C, the SR2 latch is set regardless of the state of the amplifier (A1/A2). When the part temperature falls below approximately 160°C, a full soft-start cycle will then be initiated. The current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the LT8580. operaTion
LT8580 allows for the use of small surface mount inductors. as current increases, and will saturate more easily. guidelines properly suit the final application. Table 1. Inductor Manufacturers inverting topologies (see the Electrical Characteristics). gram) cannot remain “on” for 100% of each clock cycle.
- 100% where TP is the clock period and Min Off Time (found in the Electrical Characteristics) is typically 100ns. The application should be designed so that the operating duty cycle does not exceed DC MAX. Duty cycle equations for several common topologies are given below, where VD is the diode forward voltage drop and VCESAT is typically 400mV at 0.75A. For the boost topology: DC ≅ VOUT − VIN + VD VOUT + VD − VCESAT For the SEPIC or dual inductor inverting topology (see Figure 1 and Figure 2): DC ≅ VD + |VOUT | VIN +|VOUT |+ VD − VCESAT The LT8580 can be used in configurations where the duty cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced.
For more information www.linear .com/L T8580 applicaTions inForMaTion provided to a load (I OUT). In order to provide adequate load current, L should be at least: LBOOST > DC •VIN 2(f) I LIM − |VOUT | •IOUT VIN •h for boost, topologies, or: LDUAL > DC •VIN 2(f) I LIM− VOUT •IOUT VIN • h −IOUT for the SEPIC and inverting topologies. where: LBOOST = L1 for boost topologies (see Figure 15) LDUAL = L1 = L2 for coupled dual inductor topologies (see Figure 16 and Figure 17) L DUAL = L1||L2 for uncoupled dual inductor topologies (see Figure 16 and Figure 17) DC = switch duty cycle (see previous section) I LIM = switch current limit, typically about 1.2A at 50% duty cycle (see the Typical Performance Characteristics section). h = power conversion efficiency (typically 85% for boost and 83% for dual inductor topologies at high currents). f = switching frequency I OUT = maximum load current Negative values of L indicate that the output load current IOUT exceeds the switch current limit capability of the LT8580. Avoiding Subharmonic Oscillations: The LT8580’s internal slope compensation circuit can prevent subharmonic oscil- lations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN > VIN 1− DC LMIN = L1 for boost topologies (see Figure 15) LMIN = L1 = L2 for coupled dual inductor topologies (see Figure 16 and Figure 17) L MIN = L1||L2 for uncoupled dual inductor topologies (see Figure 16 and Figure 17) Maximum Inductance: Excessive inductance can reduce current ripple to levels that are difficult for the current com- parator (A3 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = VIN − VCESAT IMIN-RIPPLE
- DC f where LMIN = L1 for boost topologies (see Figure 15) LMIN = L1 = L2 for coupled dual inductor topologies (see Figure 16 and Figure 17) L MIN = L1||L2 for uncoupled dual inductor topologies (see Figure 16 and Figure 17) I MIN(RIPPLE) = typically 80mA Current Rating: Finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. In steady state, the peak input inductor current (continuous conduction mode only) is given by: IL1-PEAK = |VOUT •IOUT | VIN •h + VIN •DC 2 •L1•f for the boost, uncoupled inductor SEPIC and uncoupled inductor inverting topologies.
Note: Inductor current can be higher during load transients. be used at the output to minimize the output ripple voltage. ESR with greater output ripple. to 2.2µF input capacitor is sufficient for most applications. tion on their entire selection of ceramic parts. Table 2. Ceramic Capacitor Manufacturers of 470pF to 2.2nF with 1nF being a good starting value. the compensation procedure is complete.
Figure 3. Transient Response Figure 4. 1.5MHz, 5V to 12V Boost Converter
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contribution of the various elements in the loop is critical. regulator, and is typically about 85%. Figure 5. Boost Converter Equivalent Model
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- IVIN From Figure 5, the DC gain, poles and zeros can be cal- culated as follows: Output Pole: P1= 2 2 •π •RL •COUT Error Amp Pole: P2 = 1 2 •π • RO +RC[ ] •CC Error Amp Zero: Z1= 1 2 •π •RC •CC DC Gain: (Breaking Loop at FBX Pin) ADC = AOL (0) = ∂VC ∂VFBX
- ∂IVIN ∂VC
- ∂VOUT ∂IVIN
- ∂VFBX ∂VOUT gma •R0( ) •gmp • h • VIN VOUT
- RL ⎟ • 0.5R2 R1+ 0.5R2 ESR Zero: Z2 = 1 2 •π •RESR •COUT RHP Zero: Z3 = VIN 2 •RL 4 •π •VOUT 2 •L High Frequency Pole: P3 > fS Phase Lead Zero: Z4 = 1 2 •π •R1•CPL Phase LeadPole: P4 = 1 2 •π • R1•R2 R1+ R2
- CPL Error Amp Filter Pole: P5 = 1 2 •π • RC •RO RC + RO
- CF , CF < CC The current mode zero (Z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection.
quency of the RHP zero to achieve adequate phase margin. 6) < 40V, the Diodes, Inc. SBR1V40LP is a good choice. Where VR > 40V, the Diodes Inc. DFLS1100 works well. Figure 6. Bode Plot for Example Boost Converter
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Table 3. Bode Plot Parameters
the switching operation of the LT8580 will stop. the free-running oscillator. be less than 25% below fOSC. any noise, therefore switching above 600kHz is desired. and filter capacitors go down in value and size. proportionally with frequency. possible, which results in large peak currents. external capacitor (typically 100nF to 1µF) to the SS pin. final value while limiting the start-up current. the soft-start occurs after every reactivation of the chip. resulting in extremely low quiescent current. or below the shutdown threshold. long as the SHDN voltage is limited to less than 40V. Figure 7. Chip States vs SHDN Voltage
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in SHDN pin current (see the Electrical Characteristics). Figure 8. Configurable UVLO start capacitor will begin charging. and into a copper plane with as much area as possible.
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For more information www.linear .com/L T8580 applicaTions inForMaTion Thermal Lockout If the die temperature reaches approximately 165°C, the part will go into thermal lockout, the power switch will be turned off and the soft-start capacitor will be discharged. The part will be enabled again when the die temperature has dropped by ~5°C (nominal). Thermal Calculations Power dissipation in the LT8580 chip comes from four primary sources: switch I 2R loss, NPN base drive (AC), NPN base drive (DC), and additional input current. The following formulas can be used to approximate the power losses. These formulas assume continuous mode opera- tion, so they should not be used for calculating efficiency in discontinuous mode or at light load currents. AverageInput Current: I IN = VOUT •IOUT VIN •h Switch I2R Loss: P SW = (DC)(IIN )2(RSW ) Base Drive Loss (AC): PBAC = 20ns(IIN )(VOUT )(f) Base Drive Loss (DC): PBDC = (VIN )(IIN )(DC) Input Power Loss: P INP = 6mA (VIN ) where: RSW = switch resistance (typically 530mΩ at 0.75A) DC = duty cycle (see the Power Switch Duty Cycle sec- tion for formulas) h = power conversion efficiency (typically 85% at high currents) Example: boost configuration, V IN = 5V, V OUT = 12V, IOUT = 0.2A, f = 1.25MHz, VD = 0.5V: IIN = 0.56A DC = 62.0% PSW = 105mW PBAC = 169mW PBDC = 44mW PINP = 30mW Total LT8580 power dissipation (PTOT) = 348mW Thermal resistance for the LT8580 is influenced by the pres- ence of internal, topside or backside planes. To calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: TJ = TA + θJA • PTOT where TJ = junction temperature, TA = ambient temperature, and θJA is the thermal resistance from the silicon junction to the ambient air. The published θ JA value is 43°C/W for the 3mm × 3mm DFN package and 35°C/W to 40°C/W for the MSOP ex- posed pad package. In practice, lower θJA values can be obtained if the board layout uses ground as a heat sink. For instance, thermal resistances of 34.7°C/W for the DFN package and 22.5°C/W for the MSOP package were obtained on a board designed with large ground planes. VIN Ramp Rate While initially powering a switching converter application, the VIN ramp rate should be limited. High VIN ramp rates can cause excessive inrush currents in the passive components of the converter. This can lead to current and/or voltage overstress and may damage the passive components or the chip. Ramp rates less than 500mV/µs, depending on component parameters, will generally prevent these issues. Also, be careful to avoid hot-plugging. Hot-plugging occurs when an active voltage supply is “instantly” connected or switched to the input of the converter. Hot-plugging results in very fast input ramp rates and is not recommended. Finally, for more information, refer to Linear application note AN88, which discusses voltage overstress that can occur when an inductive source impedance is hot-plugged to an input pin bypassed by ceramic capacitors.
ment for the boost and SEPIC configurations, respectively. tor, C1, should be placed close to the LT8580, as shown. into the system ground plane at the C3 ground terminal.
- 65V, 1A switch
- 40V VIN and SHDN absolute maximum rating
- FB renamed to FBX
- 5V FBX absolute maximum rating
Figure 9. High Speed “Chopped” Switching
- Shortening this path will also reduce the parasitic
prevent interplane coupling and overall noise.
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Figure 10. Suggested Component Placement for Boost Topology Figure 11. Suggested Component Placement for SEPIC Topology Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).
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Figure 13. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt Figure 14. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt
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Figure 15. Boost Converter: The Component Values and Voltages
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Figure 15. This topology allows for positive output voltages than 60V, see the Charge Pump Aided Regulators section. and switching frequency (VIN, VOUT and fOSC respectively). information on the design equations presented in Table 4. Table 4. Boost Design Equations
- Solve equations 1 to 4 for a range of L values
- The minimum of the L value range is the higher of LTYP and LMIN
- The maximum of the L value range is the lower of LMAX1 and LMAX2. Step 4: I RIPPLE IRIPPLE(MIN) = (VIN(MIN) – 0.4V)•DCMAX fOSC •L1 IRIPPLE(MAX) = (VIN(MAX) – 0.4V)•DCMIN fOSC •L1 Step 5: I OUT IOUT(MIN) = 1A− IRIPPLE(MIN) ⎟ •(1−DCMAX ) IOUT(MAX) = 1A− IRIPPLE(MAX) ⎟ •(1−DCMIN ) Step 6: VR > VOUT; IAVG > IOUT Step 7: C OUT COUT ≥ IOUT •DCMAX fOSC •0.005 •VOUT Step 8: C IN CIN ≥ CVIN +CPWR ≥ 1A•DCMAX 40 •fOSC •0.005 •VIN(MIN) + IRIPPLE(MAX) 8 •fOSC •0.005 •VIN(MAX)
- Refer to the Capacitor Selection Section for definition of CVIN and CPWR Step 9: R FBX RFBX = VOUT −1.204V 83.3µA Step 10: R T RT = 85.5 fOSC –1; f OSC in MHz and RT in kΩ Note 1: This table uses 1A for the peak switch current. Refer to the Electrical Characteristics Table and Typical Performance Characteristics plots for the peak switch current at an operating duty cycle. Note 2: The final values for C OUT and CIN may deviate from the previous equations in order to obtain desired load transient performance.
Figure 16. SEPIC Converter: The Component Values and Voltages
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and output due to capacitor C1. and switching frequency (VIN, VOUT and fOSC, respectively). information on the design equations presented in Table 5. Table 5. SEPIC Design Equations
- Solve equations 1, 2 and 3 for a range of L values
- The minimum of the L value range is the higher of LTYP and LMIN
- The maximum of the L value range is LMAX
- L = L1 = L2 for coupled inductors
- L = L1|| L2 for uncoupled inductors Step 4: I RIPPLE IRIPPLE(MIN) = (VIN(MIN) – 0.4V)•DCMAX fOSC •L IRIPPLE(MAX) = (VIN(MAX) – 0.4V)•DCMIN fOSC •L Step 5: I OUT IOUT(MIN) = 1A− IRIPPLE(MIN) ⎟ • 1−DCMAX( ) IOUT(MAX) = 1A− IRIPPLE(MAX) ⎟ • 1−DCMIN( ) Step 6: VR > VIN + VOUT; IAVG > IOUT Step 7: C1 ≥ 1µF; VRATING ≥ VIN Step 8: C OUT COUT ≥ IOUT(MIN) •DCMAX fOSC •0.005 •VOUT Step 9: C IN CIN ≥ CVIN +CPWR ≥ 1A•DCMAX 40 •fOSC •0.005 •VIN(MIN) + IRIPPLE(MAX) 8 •fOSC •0.005 •VIN(MAX)
- Refer to the Capacitor Selection Section for definition of CVIN and CPWR Step 10: R FBX RFBX = VOUT −1.204V 83.3µA Step 11: R T RT = 85.5 fOSC –1; f OSC in MHz and RT in kΩ Note 1: This table uses 1A for the peak switch current. Refer to the Electrical Characteristics Table and Typical Performance Characteristics plots for the peak switch current at an operating duty cycle. Note 2: The final values for C OUT, CIN and C1 may deviate from the previous equations in order to obtain desired load transient performance.
Figure 17. Dual Inductor Inverting Converter: The Component
8580 F17
- • DUAL INDUCTOR INVER TING CONVER TER COMPONENT SELECTION (COUPLED OR UNCOUPLED INDUCTORS) Due to its unique FBX pin, the LT8580 can work in a dual inductor inverting configuration as in Figure 17. Chang- ing the connections of L2 and the Schottky diode in the SEPIC topology results in generating negative output voltages. This solution results in very low output voltage ripple due to inductor L2 being in series with the output. Output disconnect is inherently built into this topology due to the capacitor C1. Table 6 is a step-by-step set of equations to calculate component values for the LT8580 when operating as a dual inductor inverting converter. Input parameters are input and output voltage, and switching frequency (V IN, VOUT and f OSC respectively). Refer to the Applications Information section for further information on the design equations presented in Table 6. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle f OSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current
Table 6. Dual Inductor Inverting Design Equations
- Solve equations 1, 2 and 3 for a range of L values
- The minimum of the L value range is the higher of LTYP and LMIN
- The maximum of the L value range is LMAX
- L = L1 = L2 for coupled inductors
- L = L1|| L2 for uncoupled inductors Step 4: I RIPPLE IRIPPLE(MIN) = (VIN(MIN) – 0.4V)•DCMAX fOSC •L IRIPPLE(MAX) = (VIN(MAX) – 0.4V)•DCMIN fOSC •L Step 5: I OUT IOUT(MIN) = 1A− IRIPPLE(MIN) ⎟ • 1−DCMAX( ) IOUT(MAX) = 1A− IRIPPLE(MAX) ⎟ • 1−DCMIN( ) Step 6: VR > VIN + |VOUT|; IAVG > IOUT Step 7: C1 ≥ 1µF; VRATING ≥ VIN(MAX) + |VOUT| Step 8: C OUT COUT ≥ IRIPPLE(MAX) 8 •fOSC (0.005 • VOUT ) Step 9: C IN CIN ≥ CVIN +CPWR ≥ 1A•DCMAX 40 •fOSC •0.005 •VIN(MIN) + IRIPPLE(MAX) 8 •fOSC •0.005 •VIN(MAX)
- Refer to the Capacitor Selection Section for definition of CVIN and CPWR Step 10: R FBX RFBX = VOUT + 3mV 83.3µA Step 11: R T RT = 85.5 fOSC –1; fOSC in MHz and RT in kΩ Note 1: This table uses 1A for the peak switch current. Refer to the Electrical Characteristics Table and Typical Performance Characteristics plots for the peak switch current at an operating duty cycle. Note 2: The final values for C OUT, CIN and C1 may deviate from the previous equations in order to obtain desired load transient performance.
For more information www.linear .com/L T8580 Typical applicaTions 1.5MHz, 5V to 12V Output Boost Converter 50mA to 150mA to 50mA Output Load Step Efficiency and Power Loss COUT 4.7µF VOUT 12V 200mA 15µH D1 130k VIN VIN SW
8580 TA02a
6.04k 56.2k SHDN GND FBX VCSYNC SSRT 3.3nF 47pF 0.22µF L1: WÜRTH 15µH WE-LQS 74404054150 D1: DIODES INC. SBR1U40LP C IN: 2.2µF , 35V , 0805, X7R COUT: 4.7µF , 16V , 0805, X7R CIN 2.2µF LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 100 100
8580 TA02b
100µs/DIV 8580 TA02c
For more information www.linear .com/L T8580 750kHz, –15V Output Inverting Converter Accepts 5V to 40V Input Typical applicaTions Efficiency and Power Loss (VIN = 12V) 60mA to 160mA to 60mA Output Load Step (VIN = 12V) COUT 4.7µF VOUT –15V 90mA (VIN = 5V) 210mA (VIN = 12V) 420mA (VIN = 40V) 22µH 22µH 1µF 182k VIN 5V TO 40V VIN SW
8580 TA03a
13.7k 113k SHDN GND FBX VCSYNC SSRT 10nF 47pF 0.22µF CIN 4.7µF
- • L1, L2: COILCRAFT 22µH MSD7342-223 D1: CENTRAL SEMI CMMSH1-60 C IN: 4.7µF , 50V , 1206, X5R COUT: 4.7µF , 25V , 1206, X7R C1: 1µF , 100V , 0805, X7S LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 100
8580 TA03b
200µs/DIV 8580 TA03c
For more information www.linear .com/L T8580 Typical applicaTions 1.2MHz Inverting Converter Generates –48V Output From 12V Input Switching Waveforms Efficiency and Power Loss Start-Up Waveforms COUT 2.2µF VOUT –48V 70mA 150µH 330µH 1µF 576k VIN 12V VIN SW
8580 TA04a
20.5k 69.8k SHDN GND FBX VCSYNC SSRT 4.7nF 47pF 0.33µF CIN 1µF 2.2µF L1: COOPER 150µH DR74-151 L2: COOPER 330µH DR74-331 D1: DIODES, INC. DFLS1100 C IN: 1µF , 50V , 0805, X7R COUT: 2.2µF , 100V , 1206, X7R C1: 1µF , 100V , 0805, X7S C2: 2.2µF , 100V , 1206, X7S 49.9/uni03A9 LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW)
8580 TA04b
200µs/DIV 8580 TA04c VOUT 10V/DIV VSW 20V/DIV IL1 + IL2 200mA/DIV 200µs/DIV 8580 TA04d
For more information www.linear .com/L T8580 Typical applicaTions Start-Up Waveforms VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz Danger High Voltage! Operation by High Voltage T rained Personnel Only Efficiency and Power Loss (VIN = 12V with Load on VOUT3) 1µF VOUT1 60V 60mA* V OUT3 180V 20mA* V OUT2 120V 30mA* 68µH 1µF D1 698k V IN 9V TO 16V VIN SW
8580 TA05a
22.1k 84.5k SHDN GND FBX VCSYNC SSRT 4.7nF 330pF 0.47µF CIN 1µF 1µF 1µF 1µF L1: WÜRTH 68µH WE-LQS 74404084680 D1-D5: DIODES, INC. DFLS1100 C IN: 1µF , 100V , 1206, X7R C1-C5: 1µF , 100V , 1206, X7S *MAX TOTAL OUTPUT POWER 3.5W 22/uni03A9 D422/uni03A9 OUTPUT POWER (W) EFFICIENCY (%) POWER LOSS (mW) 2.5
8580 TA05b
2 31 0.5 1.5 3.5 400 640 800 960 720 480 560 880 EFFICIENCY POWER LOSS VOUT3 50V/DIV VOUT2 50V/DIV V OUT1 50V/DIV IL1 200mA/DIV 2ms/DIV 8580 TA05c
For more information www.linear .com/L T8580 550kHz SEPIC Converter Generates 24V from 15V to 30V Input T ransient Response with 100mA to 225mA to 100mA Output Load Step (VIN = 24V) Typical applicaTions Efficiency and Power Loss (VIN = 24V) LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 200
8580 TA06b
100µs/DIV 8580 TA06c COUT 4.7µF VOUT 24V 195mA (V IN = 15V) 300mA (VIN = 24V) 47µH 47µH 1µF D1 274k V IN 15V TO 30V VIN SW
8580 TA06a
12.7k 154k SHDN GND FBX VCSYNC SSRT 3.3nF 22pF 0.1µF CIN 2.2µF L1, L2: COILCRAFT 47µH MSD7342-473 D1: DIODES INC. DFLS1100 C IN: 2.2µF , 35V , 0805, X7R COUT: 4.7µF , 35V , 1206, X7R C1: 1µF , 100V , 0805, X7S
For more information www.linear .com/L T8580 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 PIN 1 TOP MARK (NOTE 6)
0.200 REF
0.00 – 0.05 (DD8) DFN 0509 REV C 0.25 ±0.05 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.65 ±0.05 (2 SIDES)2.10 ±0.05 0.50 BSC 0.70 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ±0.05
0.50 BSC
8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C) package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
For more information www.linear .com/L T8580 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSOP (MS8E) 0213 REV K 0.53 ±0.152 (.021 ±.006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 1 2 3 4 4.90 ±0.152 (.193 ±.006) BOTTOM VIEW OF EXPOSED PAD OPTION 7 6 5 3.00 ±0.102 (.118 ±.004) (NOTE 3) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 0.52 (.0205) REF 1.68 (.066) 1.88 (.074) 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 1.68 ±0.102 (.066 ±.004) 1.88 ±0.102 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 0.65 (.0256) BSC 0.42 ±0.038 (.0165 ±.0015) TYP 0.1016 ±0.0508 (.004 ±.002) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE
0.05 REF
0.29 REF 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1662 Rev K)
For more information www.linear .com/L T8580 LINEAR TECHNOLOGY CORPORATION 2014 LT 0714 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T8580 relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT1310 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter V IN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT™ Package LT1613 550mA (ISW), 1.4MHz High Efficiency Step-Up DC/DC Converter V IN: 0.9V to 10V, VOUT(MAX) = 34V, IQ = 3mA, ISD < 1µA, ThinSOT Package LT1618 1.5A (ISW), 1.25MHz High Efficiency Step-Up DC/DC Converter V IN: 1.6V to 18V, VOUT(MAX) = 35V, IQ = 1.8mA, ISD < 1µA, LT1930 /LT1930A 1A (ISW), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 4.2mA/5.5mA, ISD < 1µA, ThinSOT Package LT1935 2A (ISW), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter V IN: 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT Package LT1944 /LT1944-1 Dual Output 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter VIN: 1.2V to 15V, VOUT(MAX) = 34V, IQ = 20µA, ISD < 1µA, LT1946 /LT1946A 1.5A (ISW), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC Converter VIN: 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1µA, LT3467 1.1A (ISW), 1.3MHz High Efficiency Step-Up DC/DC Converter V IN: 2.6V to 16V, VOUT(MAX) = 40V, IQ = 1.2mA, ISD < 1µA, ThinSOT, 2mm × 3mm DFN Packages LT3477 42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver VIN: 2.5V to 25V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1µA, QFN, TSSOP-20E Packages LT3479 3A Full-Featured DC/DC Converter with Soft-Start and Inrush Current Protection VIN: 2.5V to 24V, VOUT(MAX) = 40V, Analog/PWM, ISD < 1µA, DFN, TSSOP Packages LT3580 2A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC Converter VIN: 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = <1µA, 3mm × 3mm DFN-14, MSOP-16E LT3581 3.3A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC Converter VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = <1µA, 4mm × 3mm DFN-14, MSOP-16E LT3579 6A (ISW), 42V, 2.5MHz, High Efficiency, Step-Up DC/DC Converter VIN: 2.5V to 16V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = <1µA, 4mm × 5mm DFN-20, TSSOP-20 LT8582 Dual Channel, 3A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC Converter VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 2.1mA, ISD = <1µA, 4mm × 7mm DFN-24 Efficiency and Power Loss (VIN = 12V) 12V Battery Stabilizer Survives 40V T ransients COUT 4.7µF VOUT 12V 240mA 22µH 22µH 1µF D1 130k V IN 9V TO 16V UP TO 40V TRANSIENT VIN SW
8580 TA07a
16.2k 84.5k SHDN GND FBX VCSYNC SSRT 1nF 22pF 0.22µF CIN 4.7µF L1, L2: WÜRTH 22µH WE-DD 744877220 D1: DIODES INC. DFLS1100 C IN: 4.7µF , 50V , 1206, X7R COUT: 4.7µF , 25V , 1206, X7R C1: 1µF , 100V , 0805, X7S LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (mW) 160