LT8471IUFD#TRPBF

Linear Technology

Dual Multitopology DC/DC Converters with 2A Switches and Synchronization

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Technical content

8471fdFor more information www.linear .com/8471 Typical applicaTion FeaTures DescripTion Dual Multitopology DC/DC Converters with 2A Switches and Synchr onization The LT®8471 is a dual PWM DC/DC converter containing two internal 2A, 50V switches and an additional 500mA switch to facilitate step-down and inverting conversion. Each 2A channel can be independently configured as a buck, boost, SEPIC, flyback or inverting converter. Ca - pable of generating positive and negative outputs from a single input rail, the LT8471 is ideal for many local power supply designs. The LT8471 has an adjustable oscillator, set by a resistor placed from the RT pin to ground. Additionally, the LT8471 can be synchronized to an external clock. The free running or synchronized switching frequency range of the part can be set between 100kHz and 2MHz. Additional features such as frequency foldback, soft-start, and power good are integrated. The LT8471 is available in 20-lead TSSOP and 28-Lead (4mm × 5mm) QFN packages. 6V to 32V to ±5V, Dual DC/DC Converter Efficiency and Power Loss Load from VOUT1 to VOUT2

applicaTions

n Dual 2A and One 500mA, 50V Internal Power Switch Channels n 2A Primary Channels Can Be Buck, Boost, SEPIC, ZETA, Flyback or Inverting DC/DC Converter n 500mA Skyhook Channel Efficiently Generates Boosted Input Voltage n Wide Input Voltage Range of 2.6V to 50V n UVLO and OVLO Programmable on OV/UV Pin n Soft-Start Programmable for Each Channel n Fixed Frequency PWM (Set by RT Pin or Synchronized to External Clock) n Anti-Phase Switching Reduces Input Ripple n 20-Lead TSSOP and 28-Lead QFN Packages n Dual Rail Power for Signal Chain. n Buck/Buck, Buck/Boost, Boost/Boost, Boost/Invert, Invert/Invert, Buck/Invert L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. RTSYNC L T8471

8471 TA01a

1.5A VOUT2 –5V 0.65A 47µF 10µH 15µH 1µF 2.2µF 2.2µF 0.1µF 187k 2.2µF PG1 PG2 59k 316k 316k 59k 1µF 47µF 0.1µF 6V TO 32V 10µH 100k 100k 475k POWER LOSS LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

8471 F10b

VCC =

8471fd For more information www.linear .com/8471 absoluTe MaxiMuM raTings 0.4V to 50V 60V to 50V VIN1 to VE1 and VIN2 to VE2 Voltages Hi 0.4V to 60V VIN1 to VC1 and VIN2 to VC2 Voltages Hi 0.4V to 40V 0.4V to 50V 0.3V to 5V 0.3V to 5.5V (Note 1) pin conFiguraTion FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW V IN1 PG1 FB1 OV/UV RT SS1 SYNC GND V IN2 PG2 FB2 SS2 SHOUT GND GND GND θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1E1 VIN1 PG1 FB1 OV/UV RT SS1 SYNC VIN2 PG2 FB2 SS2 SHOUT NC NC NC NC NC GND GND GND GND GND GND 8 15 GND θJA = 44°C/W, θJC = 8°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB .5V to 2.5V 0.3V to 50V 0.3V to 5V 0.3V to 50V Operating Junction Temperature Range LT847 40°C to 125°C LT847 40°C to 125°C LT847 40°C to 150°C 65°C to 150°C Lead Temperature (Soldering, 10 sec) FE P 0°C

8471fdFor more information www.linear .com/8471 orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8471EFE#PBF LT8471EFE#TRPBF LT8471FE 20-Lead Plastic TSSOP –40°C to 125°C LT8471IFE#PBF LT8471IFE#TRPBF LT8471FE 20-Lead Plastic TSSOP –40°C to 125°C LT8471HFE#PBF LT8471HFE#TRPBF LT8471FE 20-Lead Plastic TSSOP –40°C to 150°C LT8471EUFD#PBF LT8471EUFD#TRPBF 8471 28-LEAD (4mm × 5mm) Plastic QFN –40°C to 125°C LT8471IUFD#PBF LT8471IUFD#TRPBF 8471 28-LEAD (4mm × 5mm) Plastic QFN –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS Input Voltage (VIN1, VIN2) l 2.6 50 V Quiescent Current (VIN1, Skyhook Disabled) V OV/UV = 1.3V, Not Switching 2.2 3.3 mA Quiescent Current (VIN1, Skyhook Enabled) V OV/UV = 1.3V, C3 = 5V, Not Switching 2.4 4 mA Quiescent Current (VIN2) VOV/UV = 1.3V, Not Switching 29 42 µA Quiescent Current in Shutdown (VIN1 + VIN2) V OV/UV = 0V 0.01 1 μA Positive Feedback Voltage (FB1, FB2) l 773 789 805 mV Negative Feedback Voltage (FB1, FB2) (LT8471E,I) (LT8471H) l l –806 –806 –788 –788 –770 –767 mV mV Feedback Pin Bias Current (FB1, FB2) V FB = Positive Feedback Voltage, Current Out of Pin VFB = Negative Feedback Voltage –100 200 100 nA nA Error Amp Transconductances Primary Channels, ∆I = 2μA 70 μmhos Error Amp Voltage Gains Primary Channels 95 V/ V Reference Line Regulation 2.6V ≤ VIN1 ≤ 50V 0.008 0.05 %/V Switching Frequency, fOSC RT = 46.4k RT = 732k l l 1.55 100 1.8 117 2.05 135 MHz kHz Switching Frequency in Foldback All Channels. Compared to Normal fOSC 1/8 Ratio Switching Frequency Range Synchronizing l 100 2000 kHz SYNC High Level for Sync l 1.3 V SYNC Low Level for Sync l 0.4 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 35 65 % Recommended Minimum SYNC Ratio fSYNC/fOSC ¾ Ratio Switching Phase Between Primary Channels R T = 46.4k RT = 732k 170 170 200 200 Deg Deg Skyhook Boost Voltage V SHOUT – VC2, Skyhook Enabled 3.0 4.25 5.4 V Minimum Switch Off-Time Primary Channels (Note 7) Skyhook Channel (Note 7) 170 100 ns ns Minimum Switch On-Time Primary Channels(Note 7) Skyhook Channel (Note 7) 220 ns ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 5V, unless otherwise noted (Note 2).

8471fd For more information www.linear .com/8471 PARAMETER CONDITIONS MIN TYP MAX UNITS Switch Current Limit (Primary Channels) Minimum Duty Cycle (Note 3) Maximum Duty Cycle (Notes 3, 4) l l 2.1 1.35 2.55 1.8 3.2 2.5 A A Switch Current Limit (Skyhook) (Note 3) l 400 500 600 mA Primary Switches VCESAT IC1 or IC2 = 1.5A 300 mV Skyhook Switch VCESAT IC3 = 250mA 250 mV C1, C2 Leakage Current VC1 = VC2 = 12V, VE1 = VE2 = 0V, VOV/UV = 0V, Current into Pin 0.01 1 μA C3 Leakage Current VC3 = 12V, VOV/UV = 0V 0.01 1 μA E1, E2 Leakage Current VOV/UV = 0V, Current Out of Pin VC1 = VC2 = 20V, VE1 = VE2 = 5V VC1 = VC2 = 5V, VE1 = VE2 = –10V 0.01 0.01 µA µA Schottky Reverse Leakage V REVERSE = 12V VREVERSE = 50V 0.01 0.02 µA µA Schottky Forward Voltage I DIODE = 100mA 650 mV Start-Up Characteristics Soft-Start Charge Current VSS1, VSS2 = 50mV, Current Flows Out of SS1, SS2 Pins l 5.5 8.5 11.5 µA OV/UV Current for OVLO Current into OV/UV Pin. VOV/UV Internally Clamped to 1.37V, Current Rising l 76 80 84 µA OV/UV Pin Bias Current VOV/UV =1V 0.01 0.5 µA OV/UV Minimum Input Voltage High Active Mode, OV/UV Rising Active Mode, OV/UV Falling l l 1.165 1.13 1.215 1.18 1.265 1.22 V V OV/UV Input Voltage Low Shutdown Mode l 0.3 V FB Pin Threshold for Power Good (Positive Output Voltage) FB Rising FB Falling l l 715 708 740 730 765 752 mV mV FB Pin Threshold for Power Good (Negative Output Voltage) FB Falling FB Rising l l –766 –755 –736 –727 –706 –699 mV mV PG1, PG2 Voltage Output Low V FB = 0.6V, IPG = 250μA 0.32 0.6 V PG1, PG2 Leakage VPG1, VPG2 = 12V, PG Driver Off 0.01 1 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8471E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8471I is guaranteed over the full –40°C to 125°C. The LT8471H is guaranteed over the full –40°C to 150°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C. elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, other wise specifications are at TA = 25°C. VIN1 = VIN2 = 5V, unless otherwise noted (Note 2). Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: Current Limit measured at equivalent switching frequency of 1MHz. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: Low side and high side configurations are discussed in the Switch Configurations and the Skyhook Regulator section. Note 7: Minimum switch on-time, off-time is guaranteed by design.

8471fdFor more information www.linear .com/8471 Typical perForMance characTerisTics Switch Current Limit at Minimum Duty Cycle Skyhook Current Limit vs Temperature Feedback Voltages Oscillator Frequency Switching Frequency During Soft-Start Internal UVLO for V IN1 and VIN2 Primary Switch Current Limit at 500kHz CH1, CH2 Switch V CESAT Skyhook Switch VCESAT TA = 25°C, unless otherwise specified. DUTY CYCLE (%) SWITCH CURRENT LIMIT (A) 2.0 2.5 3.0 1.5 1.0 40 8020 60 100 0.5 3.5

8471 G01

SWITCH CURRENT (A) SWITCH VCESAT (V)0.4 0.5 0.3 0.2 1 20.5 1.5 2.5 0.1 0.6

8471 G02

SWITCH CURRENT (A) SWITCH VCESAT (V) 0.1 0.2 0.3 0.4 0.5

8471 G03

1.0 2.0 3.0 0.5 1.5 2.5 –50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) SWTICH CURRENT LIMIT (A)

8471 G04

–50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) SWITCH CURRENT LIMIT (A)0.3 0.5 0.8 1.0

8471 G05

–50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) FB VOL TAGE (mV) –755 –765 –785 –805 –775 –795

8471 G06

+ FB – FB TEMPERATURE (°C) –55 FREQUENCY (MHz) 1.0 1.2 0.8 0.6 –15 5 45–35 25 65 10585 125 0.4 0.2

8471 G07

RT = 732k RT = 84.5k FB VOL TAGE (V) NORMALIZED OSCILLATOR FREQUENCY (fSW/fNOM) 0.25 0.50 0.75 1.00

8471 G08

2.0 2.1 2.3 2.5 2.2 2.4 –50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) SUPPL Y VOL TAGE (V)

8471 G09

8471fd For more information www.linear .com/8471 Typical perForMance characTerisTics SHOUT-C2 Regulation Voltage vs Temperature SHOUT-C2 Voltage vs SS1 Minimum Switch On-Time/ Switch Off-Time Skyhook Diode Forward Voltage PG Threshold vs Temperature (FB Falling) OV/UV Pin Current OV/UV Overvoltage Threshold OV/UV Undervoltage Threshold T A = 25°C, unless otherwise specified. OV/UV VOL TAGE (V) CURRENT INTO PIN (mA)

8471 G10

–40°C 27°C 125°C 75 –50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) OV/UV PIN CURRENT (µA)

8471 G11

–50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C)

1.10 OV/UV VOL TAGE (V)

1.15 1.20 1.25 1.30

8471 G12

–50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) SHOUT-C2 VOL TAGE (V)

8471 G13

MINIMUM VIN2-C2 VOL TAGE NEEDED TO OPERATE HIGH SIDE SWITCHES REGULATION VOL TAGE SS1 VOL TAGE (V) SHOUT- C2 VOL TAGE (V) 1 20.5 1.5 2.5

8471 G14

–55°C 25°C 125°C 150°C 100 200 250 400 150 300 350 0 5 10 15 20 25 30 35 40 VIN (V) SWITCH ON-TIME / SWITCH OFF-TIME (ns)

8471 G15

SKYHOOK DIODE CURRENT (mA) SKYHOOK DIODE VF (V) 0.2 0.4 0.6 0.8 1.0 100 200 300 400 500

8471 G16

–55°C 25°C 125°C 150°C –50 110–30 –10 10 30 50 70 90 130 150 TEMPERATURE (°C) THRESHOLD (%)

8471 G17

+ FB – FB

8471fdFor more information www.linear .com/8471 pin FuncTions C1, C2 (Pins 1, 20): Collector Pins. These are the collec- tors of the primary internal NPN power switches. If either pin is tied to a DC voltage, it must be locally bypassed; if either pin is a switching pin, minimize trace area connected to the pin to minimize EMI. When the Skyhook channel is used, the C2 pin must be tied to the input voltage of the Skyhook channel. C3 (Pin 13): Skyhook Collector Pin. This is the collector of the internal NPN power switch for the Skyhook channel. If the Skyhook channel is used, minimize the metal trace area connected to this pin to minimize EMI. If the Skyhook channel is not used, tie the C3 pin to GND. E1, E2 (Pins 2, 19): Emitter Pins. These are the emit - ters of the primary internal NPN power switches. Unless grounded, minimize trace area connected to these pins to minimize EMI. FB1, FB2 (Pins 5, 16): Feedback Pins for Primary Chan- nels. Connect a resistor divider between V OUT, FB and GND to set the output voltage. GND (Pins 10, 11,12, Exposed Pad 21): Ground. All of the ground pins must be soldered directly to the local ground plane. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. OV/UV (Pin 6): Overvoltage/Undervoltage Pin. Tie to 1.215V (typical) or more to enable the device; ground to shut down. Configurable as a UVLO and OVLO by connecting to an external resistor divider. See the Applications Information section for more information. PG1, PG2 (Pins 4, 17): Power Good Pins. Connect pull-up resistors to these pins. These open-drain output pins are pulled low when their respective output voltages are more than 7.5% below their target output voltages (as set by the external feedback resistors). When the output voltage is above 92.5% of the target voltage, the respective PG pin driver turns off, allowing the PG voltage to rise and indicate that the regulated output voltage is good. RT (Pin 7): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free-running level. Do not float this pin. SHOUT (Pin 14): Skyhook Output Voltage Pin. This is the cathode of the internal Schottky diode and the output of the Skyhook boost converter. SS1, SS2 (Pins 8, 15): Soft Start Pins. Place a soft-start capacitor on each pin. Upon start-up, the SS pins will be charged by (nominally) 250k resistors to about 2.15V. SYNC (Pin 9): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. V IN1 (Pin 3): Input Supply Pin 1. This is the power supply pin for primary channel 1 and the Skyhook channel. This pin also provides power to additional circuitry common to all channels. V IN1 must be greater than 2.6V for any channel to operate. VIN1 must be locally bypassed. VIN2 (Pin 18): Input Supply Pin 2. This is the power supply pin for primary channel 2 and must be greater than 2.6V when channel 2 is in use. VIN2 must be locally bypassed.

8471fd For more information www.linear .com/8471 block DiagraM 8471 BD 250k R Q S SR22 2.15V 2.15V UVLO OV/UVVIN2 UVLO SHOUT 250k R Q S SR21 SOFT- START SOFT- START VC1 0.5V DRIVER 50mV INTERNAL SUPPLY REG SYNC BLOCK VOLTAGE REFS 2.15V 0.73V –0.727V VC2 ADJUSTABLE OSCILLATOR FREQUENCY FOLDBACK RAMP GENERATOR OSC OSC –0.788V 0.789V COMPARATOR COMPARATOR 1.215V SKYHOOK DISABLE DRIVER DRIVER CSS1 R3A 50mV 0.789V 0.789V –0.788V VC1 VC2 CSS2 RT RPG2 VIN2 VOUT2 OV/UV LOGIC PEAK DETECT Q3 SWITCH CONTROL AND COMPENSATION SHOUT-C2 VOLTAGE COMPARE 40mV 80m/uni03A9 RSENSE2 RSENSE1 VOUT1 R2B R2A R1B R1A 0.5V 1.215V 1.37V R3B DSH VIN1 RT FB2 PG2 GND SYNC VIN1 SS2 SS1 OSC PGOOD DET. PGOOD DET. 0.73V –0.727V FREQUENCY FOLDBACK –0.788V FB1 PG1 OSC CURRENT LIMIT CONTROLLER R Q S SR12 A42 A32 RAMP GENERATOR VIN1 R Q S SR11 C1 A41 A31 CVCC VCC A43 RPG1

8471fdFor more information www.linear .com/8471 operaTion The LT8471 consists of two primary channels, each with a 2A power switch. One Skyhook channel is also avail- able with a 500mA power switch to support the primary channels when performing step-down conversions. The maximum voltage between VIN1 and E1 (or VIN2 and E2) is 40V when E1 (or E2) is grounded. This is the case for boost, SEPIC, flyback and dual-inductor inverting topologies. The maximum allowed voltage between VIN1 and E1 (or VIN2 and E2) is 60V when E1 (or E2) is allowed to toggle, such as in buck, ZETA and single-inductor inverting topologies. Primary Channels The two primary channels, 1 and 2, can be independently configured as boost, buck, SEPIC, ZETA, flyback or invert- ing DC/DC converters to adapt into various applications. Both channels use a constant-frequency, current mode control scheme to provide line and load regulation (refer to the Block Diagram). The channel 1 clock is in phase with the internal oscillator or the SYNC pin if it is toggling. In order to reduce transient switching spikes, the clock for channel 2 is approximately 180° out-of-phase with the channel 1 clock. At the start of each clock phase, an SR latch ( SR11/SR12 in the Block Diagram) is set, turning on the internal power switch (Q1/Q2 in the Block Diagram) for the respective channel. An amplifier (A41/A42 in the Block Diagram) and a comparator (A31/A32 in the Block Diagram) monitor the current flowing through the internal power switch, turning the switch off when the current reaches a level determined by the voltage at VC1/ VC2. An error amplifier measures the output voltage through an external resistor divider tied to the FB1/FB2 pin and servos the VC1/ VC2 voltage. If the error amplifier’s output (VC1/ VC2) increases, more current is delivered to the output; if it decreases, less current is delivered. An internal clamp on the VC1/ VC2 voltage provides current limit. Both of the primary channels contain a power good com- parator which trips when the corresponding FB pin voltage is at 92.5% of its regulated value. The PG1 and PG2 outputs are driven by open-drain N-channel MOSFET devices that are off when the respective output is in regulation, allow- ing external resistors to pull the PG1/PG2 pins high. The PG1 and PG2 pin states are only valid when the respective channel is enabled and VIN1 is above 2.6V. Skyhook Channel When either channel is configured as a buck, ZETA or single-inductor inverting converter, the respective V IN pin(s) must be boosted above the input voltage, VCC. The boosted supply provides base current to the appropriate Q1 and/or Q2 NPN power switch. The Skyhook channel provides this boosted voltage to the SHOUT pin which must also be connected to VIN2 and/or VIN1 as needed. The Skyhook is a constant-frequency, voltage mode boost converter including a Schottky diode integrated on chip. The Skyhook output, SHOUT, is regulated to a fixed voltage (4.25V typical) above the C2 pin which must be connected to a DC voltage (typically V CC). If the Skyhook is not needed it can be disabled by tying the C3 pin to GND. This also reduces the current draw from V IN1. Refer to the Applications Information section for more information about the proper use of the Skyhook channel. The Skyhook operates as follows: An error amplifier mea- sures the output voltage (SHOUT) through the SHOUT-C2 voltage comparator and servos an internal control volt- age. The control voltage determines the on-time of the power switch for each cycle, and thus, the amount of current being delivered to SHOUT. Loop compensation is integrated in the chip. Comparator A43 monitors the current in the power switch Q3 in order to detect over current conditions. If current in excess of 500mA (typ) is detected, switch Q3 is immediately turned off. Start-Up Operation Several functions are provided to enable a clean start-up for the LT8471.

First, the OV/UV pin voltage is monitored by an inter - nal voltage reference to give a precise turn-on voltage range. An external resistor (or resistor divider) can be connected from the input power supply to the OV/UV pin to provide a user-programmable undervoltage and overvoltage lockout function.
Second, the soft-start circuitry provides for a gradual ramp-up of the switch current for the primary channels

8471fd For more information www.linear .com/8471 Input Supply Requirements VIN1 is the main power supply of the LT8471. It powers channel 1, the Skyhook channel and most of the internal control and bias circuits for both channels. It must be powered up to enable any channel of the LT8471. V IN2 is the power supply for channel 2, and only needs to be powered up when channel 2 is used. When V IN2 is not powered up, channel 2 will shut down. Switch Configurations and the Skyhook Regulator The primary channel NPN power switches can be connected in low side or high side configurations. A low side connec- tion is when the power switch is on the lower voltage side of the inductor while the switch is on. The boost, SEPIC, flyback and dual-inductor inverting configurations use low side power switches. Conversely, a high side connection is when the power switch is on the higher voltage side of the inductor when it is on. The buck, ZETA and single-inductor inverting configurations use high side power switches. Channels 1 and 2 can be configured for high side or low side switching and do not need to be configured in the same way as the other. applicaTions inForMaTion operaTion In the low side configurations, the E pin is typically tied to ground and the respective C pin toggles. V IN for the respective channel must operate in a range of 2.6V to 40V. High side configurations require that the C pin be tied to a positive DC voltage supply and the respective E pin toggles. The channel’s VIN pin should be at least 2.2V (typical) higher than the respective C pin to provide adequate drive to the base of the NPN power switch. When configured with a high side switch, the channel’s V IN can operate up to 50V above ground, 60V above the respective E pin voltage, and 40V above the respective C pin voltage. The Skyhook boost regulator is available to provide ad - ditional VIN voltage when it is needed to support high side switch topologies. When enabled, the Skyhook output voltage (SHOUT) is regulated to 4.25V (typical) above the C2 pin voltage. Figure 1 shows an example where the application input voltage is 6V to 32V. The Skyhook boost converter regulates SHOUT, V IN1 and V IN2 to 10.25V to 36.25V insuring that the VIN1 and VIN2 pins are typically 4.25V above the C1 and C2 pins. More information about the Skyhook regulator is available in later sections. and a gradual ramp-up of duty cycle for the Skyhook channel. When the part is brought out of shutdown, the external SS capacitors are first discharged (providing protection against OV/UV pin glitches and slow ramp- ing). Next, internal 250k resistors pull the SS pins up to ~2.15V. By connecting an external capacitor to each of the SS pins, the voltage ramp rates on the pins can be set. Typical values for the soft-start capacitor range from 100nF to 1μF.

Finally, the primary channels’ switching frequency is folded back by 2, 4, or 8 times when the correspond - ing FB pin voltage is below certain thresholds (see the Typical Performance Characteristics section). This feature reduces the minimum duty cycle that the part can achieve, thus allowing better control of the switch current during start-up. The slope compensation func- tion is disabled during foldback to increase the available current that can be delivered to the output. Thermal Shutdown Operation Not shown in the Block Diagram is the thermal shutdown circuit. If the temperature of the part exceeds approximately 164°C, the SR21 and SR22 latches are set. A full soft-start cycle will then be initiated after the temperature drops below approximately 162.5°C. The thermal shutdown circuit protects the power switches as well as the external components connected to the LT8471.

8471fdFor more information www.linear .com/8471 Internal Undervoltage Lockouts The LT8471 monitors VIN1 and VIN2 supply voltages in case either drops below a minimum operating level (typically about 2.35V and 2.25V, respectively). When V IN1 is detected low, all power switches are de- activated, and while sufficient VIN1 voltage persists, the soft-start capacitors for both SS1 and SS2 are discharged. After VIN1 is detected high, the channel 1 power switch is re-enabled and SS1 begins charging. When V IN2 is detected low, the channel 2 power switch is deactivated, and while sufficient VIN1 voltage persists, the soft-start capacitor for SS2 is discharged. After both VIN1 and VIN2 are detected high, the channel 2 power switch is re-enabled and SS2 begins charging. Oscillator The internal free-running oscillator can set the operating frequency of the LT8471. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from RT to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 85.5 RT + 1 where fOSC is in MHz and R T is in kΩ. Conversely, R T (in kΩ) can be calculated from the desired frequency (in MHz) using: RT = 85.5 fOSC – 1 Clock Synchronization The operating frequency of the LT8471 can be synchro- nized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT8471 will operate at the SYNC clock frequency. The LT8471 will revert to the internal free- running oscillator clock after SYNC is driven low for a few free-running clock cycles. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latches SR11 and SR12 from becoming set (see the Block Diagram). As a result, the switching operation of the LT8471 stops, and all the power switches are turned off. The duty cycle of the SYNC signal must be between 35% and 65% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 100kHz to 2MHz unless it is set low to enable the free- running oscillator. 2. The SYNC frequency can always be higher than the free-running oscillator frequency, f OSC, but should not be less than 25% below fOSC. Operating Frequency Selection There are several considerations in selecting the operat- ing frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz, and in that case, a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The trade-off is efficiency, since the switching losses due to NPN base charge (see the Power and Thermal Calculation section), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Soft-Start The LT8471 contains soft-start circuitry to limit peak switch currents during start-up. High start-up current is inherent in switching regulators since the feedback loop is saturated due to V OUT being far from its final value. The regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. The start-up current can be limited by connecting external capacitors (typically 100nF to 1μF) to the SS1 and SS2 pins. The capacitors are slowly charged to ~2.15V by internal applicaTions inForMaTion

and below ~1.4V reduce the current limit of channel 1. after every reactivation of the chip. Performance Characteristics section. Figure 1. Chip States vs OV/UV Voltage Figure 2. Configurable OVLO and UVLO

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8471fdFor more information www.linear .com/8471 LT8471. Comparator CUVLO detects undervoltage condi- tions by comparing the OV/UV pin to typical thresholds of 1.215V (rising) and 1.18V (falling). The COVLO com- parator detects over voltage conditions by comparing the OV/UV pin current to typical thresholds of 80μA (rising) and 75μA (falling). Possible reasons to use the UVLO and/or OVLO functions are as follows: A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current-limit or latch up under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. The OVLO function is used to stop the switching regulator(s) in cases where the input supply voltage overshoots higher than desired. As an example, VIN1 overvoltage and undervoltage thresh- olds can be set independently by properly choosing R 3A and R 3B. Use the following formulas to determine the resistor values: R3A = V OVLO+ 80µA 1.18 •80µA R3B = 1.18 VUVLO – – 1.18 ⎠⎟ •R3A where: VOVLO+ is the desired rising OVLO threshold VUVLO– is the desired falling UVLO threshold After R3A and R3B have been selected, the UVLO and OVLO rising and falling thresholds can be determined using: V OVLO+ = 1.37 • R3A + R3B R3B ⎠⎟ + 80µA •R3A VOVLO – = 1.37 • R3A + R3B R3B ⎠⎟ + 75µA •R3A V UVLO+ = 1.215 • R3A + R3B R3B VUVLO – = 1.18 • R3A + R3B R3B where: VOVLO+ and V OVLO– are the rising and falling OVLO thresholds, respectively. V UVLO+ and V UVLO– are the rising and falling UVLO thresholds, respectively. There are a few limitations in selecting the OVLO and UVLO threshold voltages. The UVLO threshold must be at least 2.6V so that it’s higher than the minimum operating voltage the input supply. If the UVLO function is not needed, R3B can be omitted and R3A can be calculated using: R3A = V OVLO+ – 1.37V 80µA 2. The following relationship must be satisfied: V OVLO+ VUVLO – > 1.37 1.18 = 1.161 As the ratio of V OVLO to VUVLO gets closer to 1.161, the required resistances for R 3A and R 3B become smaller, thus increasing the operating current. applicaTions inForMaTion

8471fd For more information www.linear .com/8471 The following example shows how to select R3A and R3B to disable the LT8471 for V IN1 voltages below 5V and above 15V. First, check that the ratio of the OVLO to the UVLO thresh- old is greater than 1.161. Here, the ratio is 15V/5V = 3V, which satisfies the second rule just mentioned. Next, calculate: R3A = 15V 80µA – 1.37 •5V 1.18 •80µA = 114.9k Choose R3A to be a standard value resistance of 118k. Next, calculate: R3B = 1.18V 5V – 1.18V ⎝⎜ ⎞ ⎠⎟ •118k = 36.5k Choose R3B to be a standard value resistance of 36.5k. After selecting the standard value resistors for R 3A and R3B, calculate the final thresholds using the formulas previously provided. V OVLO+ = 1.37 • 118k + 36.5k 36.5k ⎝⎜ ⎞ ⎠⎟ + 80µA •118k = 15.24V VOVLO – = 1.37 • 118k + 36.5k 36.5k ⎝⎜ ⎞ ⎠⎟ + 75µA •118k = 14.65V V UVLO+ = 1.215 • 118k + 36.5k 36.5k ⎝⎜ ⎞ ⎠⎟ = 5.14V VUVLO – = 1.18 • 118k + 36.5k 36.5k ⎝⎜ ⎞ ⎠⎟ = 4.99V Setting the Output Voltage (Primary Channels) The output voltage is programmed with a resistor divider between the output and the FB pin. Choose 1% or better resistors according to: RA = RB • VOUT VFB – 1⎛ where V FB is the feedback voltage (0.789V typical for positive VOUT and –0.788V for negative VOUT). Reference designators are as shown in the Block Diagram. For example, for V OUT = 10V, choose R 1B = 10k, then choose: R1A = 10k • 10V 0.789V – 1⎛ ⎝⎜ ⎞ ⎠⎟ 115k Start-Up Sequencing Connecting one primary channel's PG pin to the other channel's SS pin is an easy way to sequence the start-up order of the outputs. For example, in most applications, connecting PG1 to SS2 will make the channel 1 output come up before the channel 2 output during the start-up. Because the skyhook channel does soft-start with the SS1 pin (see more details in the Soft-Start section), the following guidelines need to be applied if both power-up sequencing and the skyhook channel are used: Connect PG1 directly to SS2 to make channel 1's output come up first (see Figure 12). 2. Connect a 147k resistor between PG2 and SS1 to make channel 2's output come up first. An example using a 147k resistor connected between PG2 and SS1 is shown in Figure 9a. In this application, chan- nel 1 is configured as a boost converter, and channel 2 is configured as a buck converter. The buck converter has to start up first as its output is connected to the input of the boost converter. applicaTions inForMaTion

170ns (refer to the Electrical Characteristics section). verter. See the Typical Applications section for examples. Table 1. Inductor Manufacturers load current, and (2) avoiding subharmonic oscillation.

8471fd For more information www.linear .com/8471 Adequate Load Current: Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to a load (I OUT). In order to provide adequate load current, L should be at least: LBOOST > DC •VCC 2 •f • ILIM – VOUT •IOUT VCC •η LBUCK > DC •(VCC – VOUT ) 2 •f • ILIM − VOUT •IOUT VCC •η LSEPIC > DC •VCC 2 •f • ILIM – VOUT •IOUT VCC •η – IOUT L1 L _INV> DC •VCC 2 •f • ILIM – VOUT •IOUT VCC •η L2L _INV > DC •VCC 2 •f • ILIM − VOUT •IOUT VCC •η – IOUT LZETA > DC •VCC 2 •f • ILIM − VOUT •IOUT VCC •η – IOUT where: L = L1||L2 for dual uncoupled inductor topologies. L = L1 = L2 for dual-coupled inductor topologies. DC = Switch duty cycle in steady state. I LIM = Switch current limit, typically about 2.3A at 50% duty cycle (see the Typical Performance Characteristics section). η = Power conversion efficiency (typically 88% for boost, 75% for dual inductor, 85% for buck and 80% for 1L inverting topologies at high currents). V CC = Positive input voltage to the DC/DC converter. See the Typical Applications section for examples. f = Switching frequency. Negative values of L indicate that the output load current I OUT exceeds the switch current limit capability of the LT8471. Avoiding Subharmonic Oscillations: The LT8471’s internal slope compensation circuit will prevent subharmonic oscil- lations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LBOOST > VCC •(2 •DC – 1 ) (1– DC) •f LSEPIC > VCC •(2 •DC – 1 ) (1– DC) •f L2L _INV > VCC •(2 •DC – 1 ) (1– DC) •f LBUCK > VCC •(2 •DC – 1 ) f L1 L _INV> VCC •(2 •DC – 1 ) (1– DC) •f LZETA > VCC •(2 •DC – 1 ) (1– DC) •f where: L = L1 ||L2 for dual uncoupled inductor topologies. L = L1 = L2 for dual-coupled inductor topologies. DC = Switch duty cycle in steady state. V CC = Positive input voltage to the DC/DC converter. See the Typical Applications section for examples. f = Switching frequency. applicaTions inForMaTion

8471fdFor more information www.linear .com/8471 Maximum Inductance: Excessive inductance can reduce current ripple to levels that are difficult for the current comparator (A3 in the Block Diagram) to easily distinguish, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated using: LMAX = VCC − VCESAT IMIN(RIPPLE) •f •DC for inverting, boost, ZETA and SEPIC topologies, or: LMAX = (1− DC)•VCC − VCESAT IMIN(RIPPLE) •f •DC for the buck topology. where: LMAX = L1||L2 for dual uncoupled inductor topologies. LMAX = L1 = L2 for dual-coupled inductor topologies. I(MIN)RIPPLE is typically 120mA. DC = Switch duty cycle in steady state. V CC = Positive input voltage to the DC/DC converter. See the Typical Applications section for examples. f = Switching frequency. Maximum Current Rating: Finally, the inductor(s) must be rated to handle the peak operating current to prevent inductor saturation resulting in efficiency loss. In steady state, the peak input inductor current (continuous conduc- tion mode only) is given by: IL _PEAK = VOUT •IOUT VCC •η + (VCC − VCESAT ) •DC 2 •L •f (BOOST) IL _PEAK = VOUT •IOUT VCC •η + (VCC − VCESAT ) •DC 2 •L •f (1L _INV) IL _PEAK = IOUT + (VCC – VCESAT ) •DC •(1− DC) 2 •L •f (BUCK) IL1_PEAK = VOUT •IOUT VCC •η + (VCC − VCESAT ) •DC 2 •L1•f (SEPIC) IL2 _PEAK = IOUT + (VOUT + VD) •(1− DC) 2 •L2 •f (SEPIC) IL1_PEAK = VOUT •IOUT VCC •η + (VCC − VCESAT ) •DC 2 •L1•f (2L _INV) IL2 _PEAK = IOUT + ( VOUT + VD) •(1− DC) 2 •L2 •f (2L _INV) IL1_PEAK = VOUT •IOUT VCC •η + (VCC − VCESAT ) •DC 2 •L1•f (ZETA) IL2 _PEAK = IOUT + ( VOUT – VD) •(1− DC) 2 •L2 •f (ZETA) Note that the inductor current can be higher during load transients. It can also be higher during start-up if inad- equate soft-start capacitance is used. applicaTions inForMaTion

be used at the output to minimize the output ripple voltage. ESR with greater output ripple. is sufficient for most applications. on their entire selection of ceramic capacitors. Table 2. Ceramic Capacitor Manufacturers capacitor are available for adjusting the loop stability. adjust the voltage feedback loop. contribution of the various elements in the loop is critical. switching regulator, and is typically about 88%. Figure 3. Boost/Buck/Inverting Converter Equivalent Model

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IVIN η • VIN VOUT η • VIN • IVIN • DC VOUT

8471fdFor more information www.linear .com/8471 From Figure 3, the DC gain, poles and zeros can be cal- culated as follows: DC Gain: Boost Converters: ADC = (gma •RO) •gmp • η • VIN VOUT

RL
RB RA + RB Buck Converters: ADC = (gma •RO) •gmp •(η •RL ) • RB RA + RB Single Inductor Inverting Converters: ADC = (gma •RO) •gmp • η • VIN VIN + 2 • VOUT
RL
RB RA + RB Output Pole: Boost Converters: P1= 2 2 •π •RL •COUT Buck Converters: P1= 1 2 •π •RL •COUT Single Inductor Inverting Converters: P1= 2 • VOUT + VIN 2 •π •RL •COUT • VIN + VOUT( ) Error Amp Pole: P2= 1 2 •π •RO •CC Error Amp Zero: Z1= 1 2 •π •RC •CC ESR Zero: Z2 = 1 2 •π •RESR •COUT High Frequency Pole: P3> fS Phase Lead Zero: Z4 = 1 2 •π •RA •CPL Phase Lead Pole: P4 = 1 2 •π •CPL • RA •RB RA + RB Error Amp Filter Pole: P5 = 1 2 •π • RC •RO RC + RO
CF , CF < CC RHP Zero: Boost Converters: Z3= (1− DC)2 •RL 2 •π •L Buck Converters: Z3= ∞ Single Inductor Inverting Converters: Z3 = (1− DC)2 •RL 2 •π •DC •L applicaTions inForMaTion

Figure 4. Bode Plot for Example Buck Converter

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4 lists several Schottky diodes and their manufacturers. Table 4. Diode Vendors Table 3. Bode Plot Parameters

8471fdFor more information www.linear .com/8471 Skyhook Configuration Requirements The Skyhook provides the boosted V IN voltage required for channels operating in the high side configuration. High side channels have their respective C pin tied to a posi - tive DC voltage supply (usually VCC) while the respective E pin toggles. The channel’s V IN pin should be at least 2.2V (typical) higher than the respective C pin to provide adequate base drive for the NPN power switch. Internal circuits monitor the voltage difference between VIN1 and E1 (and V IN2 and E2). If the voltage difference is less than 2.2V (typical), the power switch will be turned off immediately for that clock cycle. Increasing voltage dif - ference between VIN and the respective C pin increases power loss and reduces efficiency. VIN must not be more than 40V higher than the respective C pin for high side configurations. If use of Skyhook channel is not desired, then the boosted VIN voltage can instead be provided by an external power supply or by the output of the opposite channel if the voltage is high enough. The Skyhook output (SHOUT) is regulated to ~4.25V above the C2 pin voltage and can be connected to the appropriate V IN pin(s) as shown in the Typical Applications section. When in use, the Skyhook can only be configured as a boost converter (i.e., as in Figure 1a). Also, since SHOUT is regulated to ~4.25V above C2, the C2 pin must be connected to a DC voltage (usually VCC) and must not be toggling. Because of this requirement, if channel 2 is used while the Skyhook is operating, channel 2 must be in the high side configuration such as buck or single-inductor inverting. If not being used, the Skyhook channel can be disabled by connecting the C3 pin to ground. When the Skyhook channel is disabled VIN1 current is reduced. Capacitor and Diode Selection (Skyhook) A low ESR capacitor should be used at the Skyhook output to minimize voltage ripple. Ceramic capacitors make a good choice for this (see the discussion in the Capacitor Selection (Primary Channels) section). The capacitor value can affect stability. Read the upcoming Compensation (Skyhook) section for more information. For the best noise performance, the Skyhook output capacitor should be connected from SHOUT to GND, and the capacitors should be placed close to the pins (V IN1 or VIN2) that SHOUT is shorted to. The Skyhook output capacitor can also be connected from SHOUT to the C2 pin (usually VCC), as shown in Figure 9a. By doing this, the output voltage of the Skyhook, or the boosted base drive voltage for the primary channels will have better tracking with the supply voltage of the channel. In addition, the voltage across the capacitor is lower, thus reducing the size and required voltage rating of the capacitor. The Skyhook has a Schottky diode built on-chip. Nev - ertheless, an external Schottky diode can be connected from C3 to SHOUT to improve performance when load currents are high. The diode choice can be made based on the discussion in the Diode Selection (Primary Chan- nels) section. The output current (IOUT) for the Skyhook channel can be estimated as: IOUT ≅ (VCC + 4.25V) •(IOUT1 •DC1 +IOUT2 •DC2) β •VCC •η where: V CC = Input voltage of the Skyhook. IOUT1 = Average output current of channel 1 if V IN1 is connected to SHOUT (0 otherwise). I OUT2 = Average output current of channel 1 if V IN2 is connected to SHOUT (0 otherwise). DC1 = Duty cycle of channel 1 in steady state. DC2 = Duty cycle of channel 2 in steady state. η = Power conversion efficiency of the Skyhook (typically 87%). β = Channel 1/channel 2 power switch beta (typically 35) applicaTions inForMaTion

8471fd For more information www.linear .com/8471 Inductor Selection (Skyhook) The general guidelines are the same as the ones for pri- mary channels, and can be found in the previous section. Minimum Inductance: There are three conditions that limit the minimum inductance for the Skyhook boost converter: 1. Provide adequate load current; 2. Avoid excessive power switch current overshoot; 3. Maintain good loop stability (see the subsequent Com- pensation (Skyhook) section). Choose an inductance that satisfies the minimum require- ments for all three criteria. At least 20% of additional margin is recommended for the inductance. Adequate Load Current: Starting by assuming the Skyhook operates in discontinuous mode (DCM), the minimum inductance (LDCM(MIN)) to provide adequate load current is: LDCM(MIN) > (IOUT1 •DC1+IOUT2 •DC2)•4.25V •2 35 •η •f •ILIM Next, verify if the Skyhook will actually operate in DCM with the following inequality: ILIM •LDCM(MIN) •f • 1 VCC + 1 4.25V ⎠⎟ < 1 If this inequality is true, then the Skyhook will operate in DCM, and IDCM(MIN) is the minimum inductance needed to provide adequate load current. Otherwise, the Skyhook will operate in continuous mode (CCM) when providing maximum load current, and the minimum inductance (LCCM(MIN)) needed is: LCCM(MIN) > DCSH •VCC 2 •f • ILIM – (VCC + 4.25V) •(IOUT1 •DC1+IOUT2 •DC2) 35 •VCC •η where: DCSH = Skyhook duty cycle in steady state: DCSH ≅ 4.25V + VDSH VC2 + 4.25V + VDSH VDSH = Skyhook diode forward voltage drop (see the Electrical Characteristics section). V CC= Input voltage of the Skyhook. ILIM = Skyhook switch fault current limit, typically 500mA. IOUT1 = Average output current of channel 1 if V IN1 is connected to SHOUT (0 otherwise). I OUT2 = Average output current of channel 2 if V IN2 is connected to SHOUT (0 otherwise). DC1 = Duty cycle of channel 1 in steady state. DC2 = Duty cycle of channel 2 in steady state. η = Power conversion efficiency of Skyhook (typically 87%). f = Switching frequency. Skyhook Power Switch Current Overshoot: In order to avoid excessive current overshoot in the Skyhook power switch, L OS(MIN) should be: LOS(MIN) > VCC •tD IOS where: V CC = Input voltage of the Skyhook. tD = Skyhook fault current limit comparator delay (typi- cally 50ns). I OS = The amount of overshoot current that can be toler- ated (typically 100mA). Current Rating: The maximum switch current limit for the Skyhook is 500mA. Choose an inductor that has a saturation current of 500mA or higher to avoid saturating the inductor. applicaTions inForMaTion

Table 5. LT8471 Power Dissipation a 15μH Skyhook inductor such as Würth 744025150. reduce the current overshoot. subsequent list to make additional adjustments if needed.

Reducing the SHOUT overshoot and undershoot during primary channel(s) load steps. Less output capacitance (C3 in the Block Diagram) can help with:
Improving loop stability.
Reducing peak inductor current during start-up. More Skyhook inductance can help with:
Reducing peak inductor current. Less Skyhook inductance can help with:
Improving loop stability when the SHOUT current load is consistently high ( i.e., the primary channel(s) powered by SHOUT is switching every cycle). Adding a resistor between SHOUT and C2, to introduce a few mA of constant load, can help with:
Improving the loop stability, SHOUT undershoot and overshoot when the SHOUT current load is consistently very light (i.e., the primary channel(s) powered by SHOUT is not switching every cycle). Thermal Considerations For the LT8471 to deliver its full output power, it is imperative that a good thermal path be provided to dis - sipate the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. applicaTions inForMaTion

the silicon junction to the ambient air. listed in the Layout Guidelines section. temperature drops by ~1.5°C (nominal). component parameters, will generally prevent these issues. in very fast input ramp rates and is not recommended. to an input pin bypassed by ceramic capacitors.

Boost: NPN power switch (C-E pins), external Schottky diode and output capacitor
Buck: NPN power switch (C-E pins), external Schottky diode and input capacitor
1L Inverting: NPN power switch (C-E pins), external Schottky diode, input capacitor and output capacitor The area inside the loop formed by these components should be kept as small as possible. This is implemented in the suggested layouts shown in Figure 5, Figure 6 and

Figure 7. Shortening the loop will also reduce the para -

Figure 5. Suggested Component Placement for a Buck and Single-Inductor Inverting Converter (TSSOP Package)

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Figure 6. Suggested Component Placement for a SEPIC and Boost Converter (TSSOP Package)

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Figure 7. Suggested Component Placement for a Boost and Dual-Inductor Inverting Converter (TSSOP Package)

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Figure 8. Suggested Component Placement for a Buck and Single-Inductor Inverting Converter (QFN Package)

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8471fdFor more information www.linear .com/8471 Typical applicaTions Figure 9a. Wide Input Range Buck Converter with 3.3V Output and Boost Converter with 18V Output at 400kHz Figure 9b. Start-Up Waveforms Figure 9c. Load Step on VOUT1 from 40mA to 135mA to 40mA IL2 500mA/DIV IL1 500mA/DIV VOUT1 5V/DIV VOUT2 2V/DIV

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8471 F09c

500µs/DIV RTSYNC L T8471

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3.3V 0.8A 22µF 1µFC4 2.2µF 2.2µF 0.1µF 215k PG2 PG1 27.4k 604k 100k 31.6k 22µF VCC 5.3V TO 28V C6 2.2µF 15µH 100k 147k 33µH 0.1µF 280k 432k 15µH C1: 25V , X7R, 1206 C2, C3, C6: 10V , X7R, 1206 C4: 50V , X7R, 1206 C5: 50V , X7R, 1206 D1: MICROSEMI UPS140 L1: SUMIDA CDRH105RNP-330NC L2: COILCRAFT MSS1038-153 L3: WÜRTH 744025150

8471fd For more information www.linear .com/8471 Typical applicaTions Figure 10a. T racking* ±12V Supplies from 6V to 36V Input at 800kHz Figure 10b. Efficiency and Power Loss (VCC = 18V, Load from VOUT1 to VOUT2) Figure 10c. 12V and –12V Outputs vs Load Current CC = 18V, Load from VOUT1 to VOUT2) Figure 10d. Load Step Between VOUT1 and VOUT2 from 150mA to 780mA to 150mA (VCC = 18V) 100 LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) LOAD CURRENT (A) VOUT1 (V) VOUT2 (V) –12.10 –12.14 –12.22 –12.30 –12.18 –12.26 12.00 12.04 12.12 12.20 12.08 12.16

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VOUT1 = 12V VOUT2 = –12V

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2.2ms/DIV IL2 1A/DIV IL1 1A/DIV VOUT2 500mV/DIV AC-COUPLED VOUT1 500mV/DIV AC-COUPLED RTSYNC L T8471

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1.1A (V CC = 36V) 1.02A (VCC = 27V) 0.92A (VCC = 18V) 0.7A (V CC = 10V) 0.4A (V CC = 6V) 1.1A (V CC = 36V) 1.02A (VCC = 27V) 0.92A (VCC = 18V) 0.7A (V CC = 10V) 0.4A (V CC = 6V) C1: 25V , X7R, 1206 C2, C3: 10V , X7R, 1206 C4, C5, C8: 50V , X7R, 1206 C6: 100V , X7R, 1206 C7: 6.3V , X7R, 0603 D1: DIODES INC SBR3U100LP-7 D2: MICROSEMI UPS140 L1: COOPER BUSSMANN DRQ74-150-R L2: COILCRAFT MSS1038-123 L3: WÜRTH 744025 150 V OUT2 –12V 22µF 1µF L1A, 15µH 12µH L1B 15µH 15µH 2.2µF 2.2µF 2.2µF 0.1µF 107k0.1µF 453k VCC 6V TO 36V PG1 PG2 232k 20k 287k 287k 20k 22µF 1µF D1 47nF *OUTPUTS DO NOT TRACK DURING START-UP

8471fdFor more information www.linear .com/8471 Typical applicaTions Figure 11a. Wide Input Range Converter with ±5V Output Voltages at 450kHz Figure 11c. Start-Up/Dropout Performance VCC Is Ramped from 0V Up to 6V and Then Back Down to 0V. Channel 1 Output Voltage Is Loaded by a 100Ω Resistor VCC Is Ramped from 0V Up to 6V and Then Back Down to 0V. Channel 1 Output Voltage Is Loaded by a 5Ω Resistor Figure 11d. Start-Up/Dropout Performance Figure 11b. Efficiency and Power Loss (Load from V OUT1 to VOUT2)

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1.6A (V CC = 6V) 1.5A (V CC = 18V) 1.5A (V CC = 32V) 0.65A (VCC = 6V) 0.95A (VCC = 18V) 1.05A (VCC = 32V)C1, C2: 10V , X7R, 1210 C3, C4, C5, C6, C7: 50V , X7R, 1206 D1, D2: DIODES INC SBR3U100LP-7 L1: WÜRTH 74437346 100 L2: WÜRTH 74437346 100 L3: WÜRTH 744025 150 V OUT2 –5V 47µF 10µH 15µH 1µF 2.2µF 2.2µF 2.2µF 0.1µF 187k 0.1µF PG1 PG2 59k 316k 316k 59k 1µF 47µF VCC 6V TO 32V 10µH 100k 100k 475k POWER LOSS LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

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VCC =

Figure 12. Boost Converter with 24V Output and Buck Converter with 5V Output at 550kHz

8471 F12

8471fdFor more information www.linear .com/8471 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE20 (CB) TSSOP REV J 1012 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev J) Exposed Pad Variation CB

8471fd For more information www.linear .com/8471 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B)

8471fdFor more information www.linear .com/8471 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 06/14 Clarified Applications Information Clarified Typical Applications 28, 29, 30, 31, 34 B 08/14 Clarified Operation Paragraph Clarified Applications Information 2nd Paragraph Clarified T ypical Application C 05/15 Added H-Grade Option 2, 3, 4 D 09/15 Added QFN Package Option Added Zeta Configuration in Skyhook Channel Description Clarified Voltages to 1.4V Clarified Figure to 9A on Start-Up Sequencing Description Clarified Figure to 11A on Start-Up Sequencing Description Clarified Figure to 9A on Capacitor and Diode Selection Description Added QFN θ JA Clarified Figure 5 (for TSSOP Package) added Reference to Figure 8 Clarified Figure 5 (for TSSOP Package) Clarified Figure 5 (for TSSOP Package) Added Figure 8 Relabeled Figures to 9A, 9B, 9C Relabeled Figures to 10A, 10B, 10C, 10D Relabeled Figures to 11A, 11B, 11C, 11D Relabeled Figures to 12 Added QFN Package Drawing Relocated TSSOP Package Drawing Was Page 34-Now Page 36 1, 2

8471fd For more information www.linear .com/8471 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/8471  LINEAR TECHNOLOGY CORPORATION 2014 LT 0915 REV D • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT8610/LT8611 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA and Input/ Output Current Limit/Monitor (LT8611 Only) VIN: 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD <1µA, MSOP-16E and 3mm × 5mm QFN-24 Packages LT8610A/ LT8610AB 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with I Q = 2.5µA VIN: 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD <1µA, MSOP-16E and 3mm × 5mm QFN-24 Package LT8582 40V, Dual 3A, 2.5MHz High Efficiency Boost Converter VIN: 2.5V to 22V, 40VMAX, VOUT(MAX) = ±40V, IQ = 2.8µA, ISD <1µA, 7mm × 4mm DFN-24 Package LT3581 40V, 3.3A, 2.5MHz High Efficiency Boost Converter VIN: 2.5V to 22V, 40VMAX, VOUT(MAX) = ±40V, IQ = 1mA, ISD <1µA, 4mm × 3mm DFN-14 and MSOP-16E Packages LT8582 40V, Dual 3A Boost, Inverter, SEPIC, 2.5MHz High Efficiency Boost Converter VIN: 2.5V to 22V, 40VMAX, VOUT(MAX) = ±40V, IQ = 2.1mA, ISD <1µA, 7mm × 4mm DFN-24 Package LT3579/LT3579-1 40V, 3.3A Boost, Inverter, SEPIC, 2.5MHz High Efficiency Boost Converter V IN: 2.5V to 22V, 40VMAX, VOUT(MAX) = ±40V, IQ = 1mA, ISD <1µA, 4mm × 5mm QFN-20 and TSSOP-20E Packages LT3471 40V Dual 1.3A Boost, Inverter, 1.2MHz High Efficiency Boost Converter V IN: 2.4V to 16V, 40VMAX, VOUT(MAX) = ±40V, IQ = 2.4mA, ISD <1µA, 3mm × 3mm DFN Package LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

8471 TA02b

8471 TA02a

VOUT1, –5V 0.55A (VCC = 4V) 0.95A (VCC = 12V) 1.05A (VCC = 24V) 0.55A (VCC = 4V) 0.95A (VCC = 12V) 1.05A (VCC = 24V) C1, C2: 10V , X7R, 1210 C3, C4, C5, C7: 35V , X7R, 1206 C6, C8: 50V , X7R, 1206 D1, D2: MICROSEMI UPS140 L1, L2: COOPER BUSSMANN DRQ74-100-R L3: WÜRTH 744025 150 V OUT2, 5V 47µF ×3C8 1µF L1A, 10µH L2A 10µH 15µH 2.2µF 2.2µF 2.2µF 0.1µF 169k 0.1µF 280k VCC 4V TO 25V PG1 PG2 100k 100k 182k 15k 80.6k 80.6k 15k 1µF C1 47µF 1µF L2B, 10µH L1B 10µH

D2 500kHz ZETA and 2L Inverting Converters Generates ±5V Outputs with Low Output Ripple Efficiency and Power Loss VCC = 12V, with Load Current from VOUT2 to VOUT1 Output Voltage Ripple in CCM, VCC = 10V IL2 500mA/DIV IL1 500mA/DIV VOUT1 20mV/DIV AC-COUPLED VOUT2 20mV/DIV AC-COUPLED

8471 TA02c

1µs/DIV

Selected Specification

Linear Technology LT8471IUFD#TRPBF overview.

Summary

Dual Multitopology DC/DC Converters with 2A Switches and Synchronization

Description

Dual Multitopology DC/DC Converters with 2A Switches and Synchronization

Source title LT8471IUFD#TRPBF Datasheet(PDF) - Linear Technology

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