LT8310

Linear Technology

100VIN Forward Converter Controller

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For more information www.linear .com/L T8310 Typical applicaTion FeaTures DescripTion 100VIN Forward Converter Controller The LT®8310 is a simple-to-use resonant reset forward converter controller that drives the gate of a low side N-channel MOSFET from an internally regulated 10V sup- ply. The LT8310 features duty mode control that generates a stable, regulated, isolated output using a single power transformer. With the addition of output voltage feedback, via opto-coupler (isolated) or directly wired (nonisolated), current mode regulation is activated, improving output accuracy and load response. The flexibility to choose transformer turns ratio makes high step-down or step-up ratios possible without operating at duty cycle extremes. The user can program the switching frequency from 100kHz to 500kHz to optimize efficiency, performance or external component size. A synchronous output is available for controlling secondary side synchronous rectification to improve efficiency. User programmable protection features include monitors on input voltage (UVLO and OVLO) and switch current (overcurrent limit). The LT8310 soft-start feature helps protect the transformer from flux saturation.

78 Watt Isolated Forward Converter, ±8% VOUT

Output Voltage Load Regulation

applicaTions

n Input Voltage Range: 6V to 100V n Duty Mode Control Regulates an Isolated Output without an Opto n High Efficiency Synchronous Control n Short-Circuit (Hiccup Mode) Overcurrent Protection n Programmable OVLO and UVLO with Hysteresis n Programmable Frequency (100kHz to 500kHz) n Synchronizable to an External Clock n Positive or Negative Polarity Output Voltage Feedback with a Single FBX Pin n Programmable Soft-Start n Low Shutdown Current < 1µA n Available in FE20 TSSOP with HV Pin Spacing n Industrial, Automotive and Military Systems n 48V Telecommunication Isolated Power Supplies n Isolated and Nonisolated DC/DC Converters L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. L T8310 UVLO OVLO DFIL T RT SS SYNC INTVCC RDVIN GATE SENSE GND VC NCNC FBX SOUT 4.7µF VIN 36V TO 72V VOUT 12V 0.6A TO 6.5A –VOUT –VIN VIN 86.6k 1.74k 1.43k 0.025/uni03A9 1%102k 49.9k 200kHz 2.2µF 100V 47µH 2:1 150pF NPO

8310 TA01a

1µF 100V 0.47µF NC 22µF ×8 100µF IOUT (A) VOUT (V) 13.5

8310 TA01b

12.0 11.0 1 2 4 10.5 10.0 14.0 13.0 12.5 11.5 5 6 7 VIN = 72V VIN = 48V VIN = 36V

For more information www.linear .com/L T8310 pin conFiguraTionabsoluTe MaxiMuM raTings D to 3V 0.3V to 0.3V te 3 Operating Junction Temperature Range (Notes 4, 5) LT83 40°C to 125°C LT83 0°C to 125°C LT83 40°C to 150°C LT83 55°C to 150°C 65°C to 150°C 0°C (Notes 1, 2) FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW UVLO OVLO DFILT RT SYNC SS V C FBX NC V IN RDVIN INTV CC GATE SENSE NC SOUT GND TJMAX = 125°C (E-, I-GRADES), TJMAX = 150°C (H-GRADE), θJC = 10°C/W, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO THE GROUND PLANE orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8310EFE#PBF LT8310EFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 125°C LT8310IFE#PBF LT8310IFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 125°C LT8310HFE#PBF LT8310HFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 150°C LT8310MPFE#PBF LT8310MPFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –55°C to 150°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

For more information www.linear .com/L T8310 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Operating Input Voltage l 6 100 V VIN Supply Current in Shutdown UVLO = 0V UVLO = 1.15V 0.3 µA µA V IN Operating Current Not Switching 3.8 4.6 mA UVLO UVLO Threshold Voltage UVLO Falling l 1.196 1.220 1.250 V UVLO Threshold Hysteresis UVLO Rising 40 mV UVLO Low Quiescent Current Threshold IVIN < 1µA l 0.36 0.62 0.85 V UVLO Pin Input Current UVLO = 1.15V UVLO = 1.30V 4.5 5.7 6.8 150 µA nA OVLO OVLO Threshold Voltage OVLO Rising l 1.225 1.250 1.275 V OVLO Threshold Hysteresis OVLO Falling –33 mV OVLO Pin Input Current OVLO = 1.17V OVLO = 1.32V 120 150 400 nA nA Linear Regulator INTV CC Regulation Voltage IINTVCC = 0mA to 20mA l 9.6 10.0 10.3 V Regulator Dropout Voltage (VIN – INTVCC) VIN = 9V, IINTVCC = 20mA 600 mV INTVCC Undervoltage Lockout Threshold INTVCC Falling 4.60 4.75 4.90 V INTVCC Undervoltage Hysteresis 0.45 V INTVCC Overvoltage Lockout Threshold INTVCC Rising 17.0 17.4 17.8 V INTVCC Overvoltage Hysteresis –0.65 V INTVCC Current Limit VIN = 12V l 25 33 39 mA INTVCC Current in Shutdown UVLO = 0V, INTVCC = 10V 125 µA INTVCC Line Regulation 10.8V ≤ VIN ≤ 100V 0.001 0.01 %/V INTVCC Load Regulation 0mA ≤ IINTVCC ≤ 20mA –3.0 –0.4 % Duty Cycle Control Minimum GATE On-Time 190 ns Maximum Duty Cycle VIN = 12V l 75 78 82 % RDVIN Pin Input Current l 19.7 20.0 20.3 µA Duty Control Transconductance (Note 6) (ΔIDFILT/ ΔVSET) VSET = 1V 22.5 25.0 27.5 µA/V Duty Mode Control Gain (Notes 6, 7), Gain = VIN/VSET at IDFILT = 0µA VSET = 0.5V to 6V l 11.76 12.00 12.24 V/V Duty Cycle Foldback, Foldback = Duty at VSS = 1.15V/Duty (Nom) Error Amplifier FBX Error Amp Reference Voltage FBX > 0V FBX < 0V l l 1.568 –0.820 1.600 –0.800 1.632 –0.780 V V FBX Over voltage Threshold FBX > 0V FBX < 0V 5.5 7.5 7.5

For more information www.linear .com/L T8310 PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Mode Threshold Voltage (Below = Duty Mode/Above = Current Mode) FBX > 0V FBX < 0V 0.2 –0.3 0.3 –0.2 0.4 –0.13 V V Feedback Mode Threshold Hysteresis FBX > 0V FBX < 0V mV mV FBX Pin Input Current FBX = 1.6V FBX = –0.8V –100 100 100 nA nA Transconductance (ΔI VC/ΔVFBX) 250 µA/V VC Source Current VFBX = 0V, VVC = 1.3V –14 µA VC Sink Current VFBX = 1.7V, VVC = 1.3V VFBX = –0.85V, VVC = 1.3V µA µA V C Pin Output Impedance 3.3 MΩ VC Pin Current Mode Gain 5 V/V Gate Driver GATE Rise Time CGATE = 3.3nF 30 ns GATE Fall Time CGATE = 3.3nF 27 ns GATE Low Voltage 0.05 V GATE High Voltage INTVCC – 0.05 V Current Sense SENSE Pin Maximum Current Threshold l 115 125 135 mV SENSE Pin Input Current –200 µA Oscillator Switching Frequency R T = 100k to GND, VSS ≥ 2.9V RT = 33.2k to GND, VSS ≥ 2.9V RT = 20k to GND, VSS ≥ 2.9V l l l 285 475 100 300 500 105 315 525 kHz kHz kHz Switching Frequency Line Regulation V IN = 6V to 100V 0.01 % RT Pin Voltage VSS = 3V 0.8 1.0 1.3 V Frequency Foldback Foldback = (fOSC at VSS = 1.15V)/fOSC(NOM) VSS = 1.15V 0.15 0.20 0.25 Hz/Hz SYNC Pin Input High Threshold Voltage l 2.00 V SYNC Pin Input Low Threshold Voltage l 1.00 V SYNC Pin Input Resistance SYNC = 2V 200 kΩ SYNC Frequency Operating Range RT = 33.2k l 260 400 kHz Minimum SYNC High Setup Time fSW = 400kHz l 250 ns Minimum SYNC Low Hold Time fSW = 400kHz l 250 ns SOUT Driver SOUT Rise Time CSOUT = 1nF 20 ns SOUT Fall Time CSOUT = 1nF 25 ns SOUT Low Voltage 0.05 V SOUT High Voltage INTVCC – 0.05 V elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless otherwise noted.

For more information www.linear .com/L T8310 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are relative to GND unless otherwise noted. All pin currents are defined positive into the pin unless otherwise noted. Note 3: Do not apply a positive or negative voltage or current source to the GATE or SOUT pins, otherwise permanent damage may occur. Note 4: The LT8310E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8310I is guaranteed over the full −40°C to 125°C operating junction temperature range. The LT8310H is guaranteed over the full –40°C to 150°C operating junction temperature range. The LT8310MP is guaranteed over the full –55°C to 150°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C. Note 5: The LT8310 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability. Note 6: V SET = VINTVCC – VRDVIN. Note 7: Line regulation in duty mode control applications is constrained by the accuracy of the RDVIN pin input current, the duty mode control gain, and the external set resistor, R SET. RSET should be specifiied to 1% or better. Note 8: See the Timing Diagrams section. PARAMETER CONDITIONS MIN TYP MAX UNITS SOUT-to-GATE Delay (tPRE) SOUT Falling to GATE Rising (Note 8) l 190 240 300 ns GATE-to-SOUT Delay (tPOST) GATE Falling to SOUT Rising (Note 8) l 0 12 25 ns Soft-Start SS Active Switching Level (GATE Switches) 0.95 1.00 1.05 V SS Frequency Foldback Complete fOSC within Specified Limits l 2.5 V SS Pin Current (Note 8) Soft-Up Slow Wake Hard-Down, V SS = 0.4V l l –60 –50 –40 µA µA mA SS Reset Threshold Voltage 0.27 V

For more information www.linear .com/L T8310 Typical perForMance characTerisTics UVLO Hysteresis Current vs UVLO Voltage UVLO Hysteresis Current vs Temperature OVLO Threshold Voltage vs Temperature Switching Frequency and (Period) vs Programming Resistance DUTY • V IN Line Regulation (Normalized) Duty • VIN Temperature Regulation Duty Set Current vs Temperature TA = 25°C, unless otherwise noted. Switching Frequency vs Temperature UVLO Threshold vs Temperature VIN (V) DUTY • VIN/(12 • VSET) (V/V) 1.00 1.01

8310 G01

0.99 0.98 20 40 60 100 1.02 VSET = 2V VSET = 1V VSET = 0.5V TEMPERATURE (°C) –75 –50 –25 0 25 50 75 100 125 150 DUTY • VIN (V) ERROR (%) 12.00 12.12

8310 G02

11.88 11.76 175 12.24 VSET = 1V VIN = 96V VIN = 48V VIN = 24V TEMPERATURE (°C) –75 –50 –25 0 25 50 75 100 125 150 IRDVIN (µA)20.0 20.1

8310 G03

19.9 19.8 175 20.2 0.5 –0.5 –1.0 1.0 VSET = 1V ERROR (%) RT (k/uni03A9) fSW (kHz) tSW (µs) 100 200 300 400 600 20 40 60 80

8310 G04

TEMPERATURE (°C) –75 –50 –25 0 25 50 75 100 125 150 fSW (kHz)300 303

8310 G05

RT = 33.2k ERROR (%) TEMPERATURE (°C) –75 VUVLO (V) 1.26 1.28 1.30 125

8310 G06

1.24 1.22 1.25 1.27 1.29 1.23 1.21 1.20 –25 25 75–50 1500 50 100 175 RISING FALLING VUVLO (V) IUVLO (µA)

8310 G07

0.2 0.4 1.6 UVLO FALLING TEMPERATURE (°C) 4.0 IUVLO (µA) 5.0 6.0 7.0 4.5 5.5 6.5 –25 25 75 125

8310 G08

175–50 –75 0 50 100 150 VUVLO = 1.15V TEMPERATURE (°C)

1.20 VOVLO (V)

1.22 1.24 1.26 1.21 1.23 1.25 –25 25 75 125

8310 G09

175–50 –75 0 50 100 150 RISING FALLING

For more information www.linear .com/L T8310 SENSE Overcurrent Threshold Voltage vs Temperature INTVCC Current Limit vs Input Voltage Typical perForMance characTerisTics VIN Quiescent Current vs Temperature GATE Driver T ransition Time vs Capacitance SOUT Driver T ransition Time vs Capacitance FBX Regulation Voltage vs Temperature INTV CC Voltage vs Temperature and Load Current INTVCC Dropout Voltage vs Load Current, Temperature INTVCC Current Limit vs Temperature TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –75 –50 –25 0 25 50 75 100 125 150 VSENSE (V) 125.0 127.5

8310 G10

122.5 120.0 175 130.0 ERROR (%) TA, AMBIENT TEMPERATURE (°C) –75 VINTVCC (V)10.0 10.2 10.4 125

8310 G11

9.8 9.6 9.4 –50 –25 0 25 50 75 100 150 175 SHUTDOWN AT TJ ≈ 165°C LOAD = 1mA LOAD = 10mA LOAD = 20mA INTVCC LOAD (mA) DROPOUT VOLTAGE (V) 0.4 0.8 1.2 1.6 2.4 4 8 12 16

8310 G12

2.0 TA = 125°C TA = –65°C TA = 25°C TA, AMBIENT TEMPERATURE (°C) –75 –IINTVCC (mA) 125

8310 G14

–50 –25 0 25 50 75 100 150 175 VIN = 12V TJ ≈ TA + 15°C TEMPERATURE (°C) –75 –50 –25 0 25 50 75 100 125 150 POSITIVE VFBX (V) 1.600 1.616

8310 G15

1.584 1.568 175 POSITIVE NEGATIVE 1.632 –0.800 –0.808 –0.792 –0.784 –0.816 NEGATIVE VFBX (V) TEMPERATURE (°C) –75 IVIN (mA)4.4 4.5 4.6 150 125

8310 G16

4.3 4.2 4.0 –25 25 75–50 1750 50 100 4.1 4.8 4.7 GATE, SOUT PINS NOT SWITCHING VIN (V) –IINTVCC (mA) 20 40 60 80

8310 G13

FROM OFF, TA = TC = 25°C THERMALLY SETTLED, TA = 25°C CGATE (nF) TIME (ns) 100

8310 G17

t RISE VIN = 48V fSW = 100kHz tFALL CSOUT (nF) TIME (ns) 100 6.0

8310 G18

1.5 3.0 4.5 7.5 t FALL VIN = 48V fSW = 100kHz tRISE

For more information www.linear .com/L T8310 TA = 25°C, unless otherwise noted.Typical perForMance characTerisTics Driver Nonoverlap Delays vs Temperature Set Current vs Soft-Start Voltage Switching Frequency (Normalized) vs Soft-Start Voltage GATE Duty Cycle (Normalized) vs Soft-Start Voltage Output Voltage T ransient Response (Typical Applications, Pages 1 and 31) TEMPERATURE (°C) –75 tDLY (ns)150 200 250 300 125

8310 G19

–25 25 75–50 1500 50 100 175 SOUT FALL TO GATE RISE GATE FALL TO SOUT RISE VSS (V) IRDVIN (µA) 0.5 1.0 1.5 2.0

8310 G20

2.5 3.0 VSS (V) 1.2 1.0 0.8 0.6 0.4 0.2 –0.2 1.5 2.5

8310 G21

0.5 1.0 2.0 3.0 fSW/fSW(NOM) (kHz/kHz) VSS (V) 1.2 1.0 0.8 0.6 0.4 0.2 –0.2 1.5 2.5

8310 G22

0.5 1.0 2.0 3.0 DUTY/DUTY (NORM) (%/%) 100kHz 300kHz 500kHz 1ms/DIV 8310 G23VIN = 48V IOUT = 4.5A TO 6.5A TO 4.5A VOUT 1V/DIV

For more information www.linear .com/L T8310 pin FuncTions UVLO ( Pin 1): System Undervoltage Lockout Input. Program the system falling UVLO threshold (minimum VIN voltage) with a resistive voltage divider from V IN to this pin. The pin voltage is compared internally to an ac- curate 1.22V threshold. Program the system rising UVLO hysteresis via this pin’s 5.7µA hysteretic current and the values of the external resistors. The device is shut down below the UVLO threshold and draws 1µA or less from VIN when VUVLO ≤ 0.36V (min). The UVLO pin can withstand 100V maximum. OVLO (Pin 3): System Overvoltage Lockout Input. Program the system rising OVLO threshold (maximum VIN voltage) with a resistive voltage divider from V IN to this pin. The pin voltage is compared internally to an accurate 1.25V threshold. Exceeding the OVLO threshold sets the fault latch and forces a system shutdown. DFIL T (Pin 5): Duty Cycle Loop Filter Pin. Set the duty cycle loop filter pole by connecting a capacitor to GND from this pin in both duty mode and current mode ap - plications. Consult the Applications Information section to choose the capacitor value to reduce load step ringing in duty mode control applications. Do not float this pin, a capacitor is required. RT (Pin 6): Switching Period Set Input. Set the oscillator switching period (frequency) via a resistor to GND from this pin, typically 20k to 100k for 2µs to 10µs (500kHz to 100kHz). In applications where an external clock drives the SYNC pin, program the switching period to the expected SYNC frequency value. Place the resistor close to the pin and minimize stray capacitance. Do not leave the RT pin open. SYNC (Pin 7): External Clock Input. Drive this pin with an external fixed-frequency clock signal to synchronize switching to it. The SYNC falling edge is automatically detected and converted to a pulse that starts the minimum off-time of the duty cycle. The SYNC pulse low and highs times must both be ≥250ns. Select an R T resistor that programs the internal switch frequency to the external SYNC frequency to keep the maximum duty cycle limit accurate. When VSS < 1V, the SYNC pin is ignored. SS (Pin 8): Soft-Start Input. Program start and hiccup timing by tying an external capacitor between SS and GND. During normal soft-start this pin sources 50µA. During faults and initial start, a 6mA (typ) current sink discharges this pin to 0.27V (typ). The GATE pin is shut off until V SS ≥ 1V. After an overcurrent shutdown, the pin sources only 5µA until VSS ≥ 1V, which provides an extended wake-up period that reduces power dissipation during repeated start-up retries (hiccup mode). Switching frequency and duty cycle are folded back until SS > 2.5V. Above 1V, the pin sources 50µA until charged to an internal 3V clamp. VC (Pin 9): T ransconductance Error Amp Output. Compen- sate the converter loop at this pin with an external series resistor and capacitor to GND in feedback applications. In opto-isolated feedback applications, compensation is generally done on the secondary side (see the Applica - tions Information section). In duty mode control applica- tions that have no output voltage feedback, leave this pin unconnected. FBX (Pin 10): Feedback Input and Mode Control. Standard input for nonisolated applications that require voltage feedback. Program output voltage with a resistive voltage divider to compare to the internal 1.6V reference for positive output applications, or to the –0.8V reference for negative output applications. When –0.2V < VFBX < 0.3V, duty mode controls the GATE pin, otherwise FBX is assumed to be in control. FBX exceeding its reference by 7.5% ends the switching cycle in progress without triggering a system reset. Tie FBX to GND if duty mode only is desired. SOUT (Pin 11): Synchronization Output. Pulse transformer driver for applications with synchronous secondary-side control, complementary to GATE. The SOUT falling edge leads GATE turn-on by 240ns (typ), and the rising edge trails GATE turn off by 12ns (typ). Actively pulled to INTVCC during shutdown. NC (Pin 12): No Internal Connection. Connect to GND.

For more information www.linear .com/L T8310 pin FuncTions SENSE (Pin 13): Switch Current Sense Input. Positive input of the low side current sense to the control loops and the overcurrent comparator. Kelvin-connect this pin to the sense resistor at the source of the N-channel MOSFET switch. Exceeding 125mV at this pin triggers an overcur- rent fault, and sends the system into fast shutdown, slow wake-up, and soft-start. GA TE (Pin 14): Switch Control Output. Low side switch drive (GND to INTVCC) for external N-channel MOSFET. The maximum duty cycle is limited to 78% (typ) because reso- nant reset forward converters require time for transformer flux to reset. Actively pulled to GND during shutdown. INT VCC (Pin 15): Regulated Supply Output. A 10V LDO supply generated from VIN and capable of supplying the GATE pin. Must be bypassed with a 4.7µF capacitor or higher. The regulator voltage can be externally driven up to 17V, as long as VIN ≥ VINTVCC, to reduce internal power dissipation from VIN or to accommodate more than 10V gate drive for high voltage N-channel MOSFETs. RDVIN (Pin 16): Duty Cycle Control Input. This pin sinks a precise 20µA in normal operation, but less during soft- start, when the duty cycle is folded back. Connect a resistor RSET between the INTVCC and RDVIN pins to program the desired (no opto) application output voltage: RSET = NP NS ⎟ • VOUT ⎝⎜ ⎞ 20µA Resistor value accuracy contributes directly to the output voltage accuracy, choose appropriate tolerance. In current mode applications, feedback sets VOUT, therefore program RSET to set a maximum duty cycle guardrail that constrains the volt-seconds of flux in the transformer during transients. This pin must be connected to INTVCC by a resistor. VIN (Pin 18): Supply Input and System Input Voltage Sense. Input supply for the part; operational from 6V to 100V. Accurate duty cycle requires accurate sensing of the VIN voltage, so keep the connection to the transformer primary short to minimize resistive voltage drops. Bypass to GND with 1µF. NC (Pin 20): No Internal Connection. Connect to V IN. GND (Exposed Pad Pin 21): Ground. This pin also senses the negative terminal of the current sense resistor. Solder the exposed pad directly to the ground plane.

8310 F01

Figure 1. LT8310 Block Diagram Configured as a Nonsynchronous Duty Mode Converter

For more information www.linear .com/L T8310 TiMing DiagraMs Start-Up/ Soft-Start / Fault / Shutdown / Restart Nonoverlapping GATE/SOUT VIN VUVLO RISING ~ 1.26V START UP FALLING 1.22V SHUT DOWN REGULATOR CAPACITOR DISSIPATINGVINTVCC VSS VGATE VSENSE 5.2V 1V 1V FAST DOWN 0.27V SOFT-START

8310 TD01

tPRE D • tSW (1 – D) • tSW tPOST tSW

8310 TD02

For more information www.linear .com/L T8310 operaTion INTRODUCTION The LT8310 is a constant-frequency forward converter controller with a low side N-channel MOSFET gate driver and low side switch current sensing that offers two oper- ating modes: duty mode control and peak current mode control. Duty mode control that requires no output voltage feedback is targeted for (but not limited to) isolated duty mode control applications, to which it brings a simple schematic, low parts count, and only one isolation element, a transformer. In current mode control applications, feed- back determines the output voltage, but the duty control loop enforces a programmable relative maximum duty cycle that clamps the volt-seconds of core flux to avoid transformer saturation during transients. At all times the LT8310 also enforces an absolute maximum duty cycle that provides time to reset the core each switching period. With a patent pending architecture, the LT8310’s duty control loop imposes volt-second accuracy over the span of input voltage that translates into both accurate output voltage without feedback and protection from transformer saturation. Duty Mode Control The duty mode control loop compels a PWM duty cycle that is inversely proportional to the system input voltage, D(V IN) ∝ 1/VIN, which is the correct function for a buck (or buck derived) converter to generate a constant output regardless of the line input. For a given scaling constant KD, D(VIN ) = KD V[ ] VIN [1] In a forward converter with transformer turns ration NP/NS, VOUT = D(VIN ) • VIN NP / NS = KD NP / NS [2] In the discussion that follows it will be helpful to refer to the Block Diagram in Figure 1. Duty mode control governs operation when the feedback pin (FBX) is tied to GND. It serves as an accurate volt-second clamp when current mode control governs operation because feedback is present. The system clock starts the PWM duty cycle by driving the GATE pin high to close the external MOSFET switch and initiating a timing ramp in the duty loop ramp generator. While GATE is high, current proportional to VIN discharges a capacitor (CDFIL T) between the DFIL T pin and GND; when GATE is pulled low, a fixed current charges it. The duty cycle ends when the ramp voltage plus some switch current feedback exceeds the DFIL T voltage, at which point GATE falls and shuts off the primary-side switch until the start of the next period. The condition of the main switch (on or off, as indicated by GATE pin voltage) controls the sourcing and sinking of current at the DFIL T pin. The voltage imposed between the INTVCC and RDVIN pins, V SET, establishes an inter- nal reference current (IREF). During the switch on-time, D • tSW, a current proportional to the system input voltage VIN (which is sensed at the VIN supply pin) is subtracted from the reference current and driven at DFIL T. During the switch off-time, (1-D) • tSW, only the reference current is driven. The external capacitor to GND at DFIL T (C DFIL T) integrates the current. In steady-state operation with suf- ficient load, the feedback loop forces the net cycle current to zero, which produces a duty cycle inversely proportional to VIN (Equation 3), and ultimately a constant output voltage (Equation 4). An external resistor (RSET) between INTVCC and RDVIN and a precise 20µA sink at RDVIN program VSET and thus, VOUT. D = 12 • VSET VIN [3] VOUT = 12 • VSET NP / NS [4]

For more information www.linear .com/L T8310 operaTion Several system operation and protection features are exclu- sive to current mode control. When the load is light, auto- matic pulse skipping allows the effective switching period to extend, which lowers the duty cycle without necessitating impractically narrow GATE pulses. If FBX pin overvoltage is detected during a cycle, the duty cycle ends, GATE falls, and the switch turns off, which allows the output voltage to coast down. When current mode control governs opera- tion, the duty loop circuitry acts as a relative maximum duty cycle clamp that protects the transformer from developing excessive volt-seconds of flux during transients and it limits the output voltage. This feature also allows the system to revert to duty mode control if FBX is grounded. The duty cycle clamp margin is user-programmable. Common Operation and Protection Features A programmable soft-start pin (SS) controls the power-up time and folds back the switching frequency and the duty cycle during start-up to protect the transformer and to limit inrush current. A minimum on-time of 190ns (typ) ensures that the MOSFET switch has enough time to turn on reliably, and a maximum duty cycle of 78% guarantees time for core reset each cycle. The SYNC pin allows an external pulse signal to override the LT8310’s oscillator and set the switching period. The SOUT pin supplies a non-overlapping signal complementary to the GATE that may be used for synchronous converter applications. The SOUT pin driver has about 40% of the GATE pin’s drive strength, and may be used to drive a pulse transformer (isolated) for forced continuous mode (FCM) operation. Other protection mechanisms end the normal switching cycle or force system shutdown to protect the applica - tion circuit. The minimum and maximum V IN operating thresholds are programmed at the UVLO and OVLO pins, respectively. Input voltages outside of the set limits shut down the system. Shutdown also occurs when the INTVCC regulator voltage goes above or below its operating range, and when the die temperature exceeds 165°C. The switch With no output voltage feedback, the secondary-side LC filter might freely ring (depending on load resistance and parasitics) in response to load current steps; the primary- side switch current that feeds into the duty mode control loop limits the ringing. During the switch on-time, induc- tor current translates to switch current that is scaled and added to the timing ramp. Constant current is absorbed into the DC level of the DFIL T voltage, which does not af- fect duty cycle, but changing current dynamically adjusts the duty cycle to dampen the ringing. The DFIL T capacitor is chosen with respect to the output LC time constant (√L1•CL) to track out the oscillation. The selection of this capacitor is discussed in the section, Compensating the Duty Mode Control Loop. Duty mode control operation requires a minimum load in steady-state to balance the sum of the transformer mag- netization current and output inductor ripple current, see the section, Minimum Load Requirements. Current Mode Control To serve applications that require tighter output voltage regulation and faster load response, the LT8310 offers standard constant-frequency peak current mode control when output voltage feedback (opto-isolated or noniso - lated) is connected. The system clock starts the PW M duty cycle by driving the GATE pin high to close the external MOSFET switch. The switch current flows through the external current sensing resistor R SENSE and generates a voltage proportional to the switch current. The current sense voltage is amplified and added to a stabilizing slope compensation ramp. When the resulting sum exceeds the control pin (V C) voltage, the duty cycle ends, and the main switch is opened. The VC pin level is set by the error ampli- fier, which amplifies the difference between the reference voltage (1.6V or –0.8V, depending on the configuration) and the feedback pin (FBX) voltage. In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation.

Figure 3. Forward Converter Architecture (Nonsynchronous)

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MOSFET during repeated retries. isolation for isolated applications. Figure 2. Typical Signals in a Forward Converter

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For more information www.linear .com/L T8310 operaTion D1 conducts, which imposes VIN/(NP/NS) – VOUT across inductor L1 ( ignoring voltage drop across the diode), for the switch on-time, D • tSW. When the GATE signal goes low, the switch turns off, and the primary winding volt- age collapses as the primary current charges the reset resistor CRST. The switch node voltage (V SW) resonates past VIN, which takes the primary winding voltage nega- tive. The secondary winding voltage also goes negative, for ward diode D1 turns off, and the inductor current flows through the catch diode, D2, which imposes –VOUT (again ignoring diode drop) across inductor L1 for the switch off-time, (1 – D) • tSW. The output voltage may be calculated by considering the volt-second balance in the inductor under steady-state conditions (Equation 5), and then solving for V OUT. Equation 6 makes it clear that forcing the duty cycle to be inversely proportional to the input voltage would create a constant output voltage as desired. VIN NP / NS − VOUT ⎟ •D • TSW +(−VOUT ) •(1−D)• TSW = 0 [5] VOUT = D • VIN NP / NS [6] To keep the transformer from saturating, its core flux must be reset periodically. The LT8310 relies on resonant reset each cycle uses a capacitor between the switch node, SW, and ground (see Figure 2). When the main switch turns off at the end of the duty cycle, V SW ramps up to and beyond V IN, which cuts off secondary-side current and forces primary-side current to charge the switching node. Node SW resonates for half a sine wave until the transformer voltage and current are both zero, which leaves VSW = VIN until the next switch activation. Note that (1) the maximum voltage on the primary switch exceeds the input voltage, and may be well above it, and (2) ideally, the flux reset completes within the switch off-time before the next cycle begins. The LT8310 controller imposes an absolute maximum duty cycle that provides a predictable minimum off-time (at a given switching frequency) in which to reset the core.

the LT8310 from excessive on-chip power dissipation. the Thermal Considerations section for further information. voltage, and the soft-start pin will be reset. is recommended when INTVCC is overdriven. contributes a small amount to the rising threshold as well. that sets the maximum restart VIN (Equation 11). Figure 4. Resistor Connections for System UVLO

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Choose a rising hysteresis voltage, VHYST(UVLO RISING),
Calculate the sum of R2 + R1 from Equation 8
Calculate R1 from Equation 10, which then determines
Recheck the thresholds using actual resistor values.

without output voltage feedback, using ideal components. 6 (here recast with the target output). and it is a measure of the relative duty cycle clamp margin. 75% (min), constrains the turns ratio per Equation 13. Figure 5. Forward Nonsynchronous Converter Core Schematic

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NP NS < 0.75 [14] Finally, the duty cycle scaling must be programmed. As discussed in the latter part of the section, Duty Mode Control, the voltage difference between the INTV CC and RDVIN pins, VSET, and an accurate internal gain of 12V/V sets the duty mode loop scaling constant, KD. The RDVIN pin sinks a precise 20µA that permits a single resistor, RSET, to program the voltage difference. KD = 12V V • VSET = 12V V •(20µA •RSET ) [15] Resistor RSET may be chosen to achieve the desired VOUT(TARG) based on Equation 16. RSET = VOUT(TARG) 12V / V • NP NS 20µA [16] The tolerance of the set resistor contributes directly to the accuracy of the target output voltage, which is especially important to the accuracy of converters operating without output voltage feedback, so always use a 1% or better resistor. Keep R SET close to the RDVIN and INTVCC pins of the chip to minimize trace length and avoid cross-coupling with other signals. During soft-start, the RDVIN sinking current is reduced to fold back the duty cycle while the clock frequency is also reduced. This protects the transformer by limiting the volt-seconds of flux generated when the clock period is made longer. Take care to consider the flux conditions during soft-start if external currents are employed for trimming or margining. Programming the Switching Frequency The RT frequency adjust pin allows the user to program the switching frequency from 100kHz to 500kHz to optimize efficiency and performance or external component size. Higher frequency operation yields smaller component size, but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. It also decreases magnetization current, which reduces the minimum load requirement under duty cycle mode control. Lower frequency operation gives bet- ter performance at the cost of larger external component size. Table 1 shows the RT values for several frequencies that match the design equation, Equation 17.

Table 1. Resistor Selection Guidance for Some Common

10k = tSW 1µs • 10k [17] Minimize stray-coupling to the adjacent DFIL T and SYNC pins by keeping the traces short. An external resistor from the RT pin to GND is required—do not leave this pin open. Programming the Current Sense The LT8310 features primary-side switch current sensing that protects the system from excessive load current, damps output ringing when duty mode control dominates, and sets the duty cycle when current mode control dominates. When VSENSE exceeds 125mV (nom), the maximum switch current threshold, the system shuts down and attempts a restart after a slow wake-up period (see Programming the Soft-Start Interval and Hiccup Period). In converter

For more information www.linear .com/L T8310 applicaTions inForMaTion applications operating without output voltage feedback, current sense information is fed back to the duty cycle loop to reduce output voltage ringing due to load current steps that excite the output LC tank. In supply applications, each cycle ends when the amplified SENSE voltage exceeds the VC pin control level. In all cases, during the cycle on-time, the switch sees the rippling inductor current (IL1), scaled by the transformer turns ratio (Equation 18) plus the transformer’s primary magnetizing current, Iµ,p. Applying VIN across the magnetizing inductance generates a peak magnetizing current of approximately 12 • VSET • tSW/Lµ,p. ISWITCH = IL1 NP / NS +Iµ,p [18] Resistor RSENSE connected between the SENSE and GND pins converts the switch current to a voltage. It should be selected to provide the maximum switch current required by the application, including inductor ripple current, without exceeding the SENSE pin’s overcurrent threshold. A good rule of thumb is to allow 10% margin on the minimum overcurrent threshold of 115mV. During steady-state operation, the average inductor current equals the load current. In applications under duty mode control, which require a minimum load, less inductor ripple means a lower minimum load current, so peak inductor current might be 10% or less above the maximum load current. Output voltage ring damping operates best with a strong average current signal, so RSENSE should be chosen as large as allowed by the SENSE pin threshold. Equation 19 provides a good value for RSENSE that accounts for the minimum SENSE threshold: RSENSE ≤ 115mV 1.1• ISWITCH(MAX) [19] In applications with output voltage feedback, current mode control is most agile with a steep slope to the ripple, so peak inductor current might be 20% or more above the average load current. Equation 20 provides a good value for RSENSE that accounts for the minimum SENSE threshold: RSENSE ≤ 115mV 1.4 • ISWITCH(MAX) [20] It is always prudent to verify the peak inductor current in the application to ensure the sense resistor selection provides margin to the SENSE overcurrent limit threshold. The placement of R SENSE should be close to the source of the N-channel MOSFET and GND of the LT8310. The SENSE input to LT8310 should be a Kelvin connection to the positive terminal of R SENSE. Verify the power in the resistor to ensure that it does not exceed its rated maximum. Programming the Soft-Start Interval and Hiccup Period The built-in soft-start circuit significantly reduces the inrush current spike and output voltage overshoot at start-up. Please refer to Figure 6 and the Timing Diagrams section for the following discussion of soft-start behavior. The soft-start interval is programmed by a capacitor connected from the SS pin to GND. In a normal start-up, after the INTV CC voltage exceeds its rising threshold of about 5.2V, the SS pin sources 50µA (typical), which ramps the capacitor voltage. Switching commences when the 1.00V switching threshold is exceeded (EN_GATE high). Assuming the SS pin starts fully discharged, the soft-start time, t SS, may be programmed by choosing C SS using Equation 21. A 100nF soft-start capacitor produces about 2ms of delay, which suits many applications. CSS = 50nF • tSS ms[ ] 1ms [21] The SS pin voltage is discharged when the fault latch is set under any of the following conditions: the UVLO pin voltage falls below its threshold (SYS_UV high), the OVLO pin voltage exceeds its threshold (SYS_OV high), the die temperature exceeds 165°C (SYS_OT high), the INTVCC voltage falls below or rises above its operating range (REG_UV or REG_OV high), or the SENSE pin voltage exceeds its maximum threshold because the switch current is too large (ISW_MAX high). When the fault condition ceases and V SS < 0.27V, the fault latch clears, which brings about restart as SS rises through the 1V threshold. Exceeding maximum switch current sets the hiccup latch, which extends the soft-start time by reducing the pull-up current to 5µA (typical). After the fault latch is reset, the

times the soft-start time (Equation 22). operation if the output feedback fails. define the output resonance time constant. and a faster response, decrease CDFIL T.

25µA V • L1•CL [25] In rare applications where a very fast duty loop response is more advantageous than output voltage ring reduction (e.g., sharp input voltage steps occur more regularly than sharp load current steps), the compensation capacitor may be chosen small for faster loop speed, independent of the LC tank’s natural period.

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Figure 6. Soft-Start Control Logic

connected from the VC pin to GND (Figure 7).

NP / NS( ) • VOUT VREF [26] A small capacitor is sometimes connected in parallel with the RC compensation network to attenuate the VC voltage ripple induced from the output voltage ripple through the internal error amplifier. The parallel capacitor usually ranges in value from 10pF to 100pF. A practical approach to design the compensation network is to start with the typical CC = 4.7nF and RZ = 20k, calcu- late an new RZ when all the component values in Equation 26 are available, then tune the compensation network to optimize the performance. Stability should be checked across all operating conditions, including load current, input voltage and temperature. Minimum Load Requirements In standard current mode converters, the controller senses rising output voltage and activates pulse-skipping mode that reduces the power delivered to the load as the output current demand decreases, until there is no load and the main switch is turned off. With no output voltage sensing to command pulse skipping and a VIN-based control loop that operates continuously, LT8310 nonsynchronous duty mode control applications require a minimum load in steady state operation to dissipate transformer magnetization and inductor ripple currents. Failure to provide the minimum load current results in an increased steady-state output voltage, which peaks at VIN/(NP/NS) when IOUT = 0A. In Equation 27, given an output voltage (VOUT), the mini- mum load current is expressed as a function of (1) the

Figure 7. Forward Nonsynchronous Direct-Wired Nonisolated Basic Schematic

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For more information www.linear .com/L T8310 applicaTions inForMaTion switching frequency (fSW), (2) the transformer’s primary magnetizing inductance (Lµ) as seen on the secondary- side through the turns ratio (N P/NS), and (3) the ripple current in the inductor (L1) during the off-time portion of the duty cycle (1 – DMIN). IOUT(MIN) = VOUT 2 • fSW

NP / NS( ) Lµ + 1− DMIN( ) [27] The minimum load current may be reduced in three ways, given a fixed output voltage. First, the switching frequency, fSW, may be increased while keeping the same transformer and output inductor. Operating at higher frequency tends to decrease efficiency as switching transients account for a higher percentage of the period. Some power transfer lost to lower efficiency generally outweighs power spent on burning dummy load current if the natural load is too light. Second, the transformer magnetizing inductance may be increased by using more turns to reduce the magnetiz- ing current. Within the same family of transformers, an 8:4 transformer will have more magnetizing inductance than a 2:1 transformer, but more turns also means more winding resistance losses. Third, the output inductor may be increased, which directly reduces the output ripple current, and thus the minimum load. If an application’s natural load is not sufficient, a dedicated load resistor that guarantees the minimum current for a given output voltage may be selected using Equation 28. Consider the power dissipation when choosing the rating and type of resistor ROUT. ROUT < 2 • fSW • Lµ NP / NS( ) 2  L1 (1− DMIN ) [28] Ohmic Loss Matters Before a more specific discussion of component selection, a general note about DC resistance in the power path is warranted. For duty mode control applications, no volt - age feedback exists to compensate for voltage drops in the system. Contributors include the on-resistance of all switches, the current sense resistor, and the DCR’s of the transformer and inductor. Take care to select components for their low ohmic losses to control both the absolute accuracy of the output voltage and the load regulation effect. Once ohmic losses are estimated or measured for a given application, the output voltage target may be adjusted upward, and a new value of set resistor chosen to compensate, see Programming the Duty Cycle Loop Output Voltage Target. T ransformer Selection Important parameters that guide the choice of transformer include the primary-to-secondary turns ratio, the presence or absence of auxiliary windings and their turns ratios, the power rating, the operating frequency, the magnetiz- ing inductance, the leakage inductance, the DC winding resistances of the primary and secondary and the isolation voltage rating. An application’s input voltage range and output voltage target drive the choice of turns ratio between the primary and secondary windings (see Equation 12). DC/DC power transformer winding ratios should be specified to ±1%, a variation that directly affects the accuracy of converters without output voltage feedback, but that only influences the duty cycle range in circuits with output voltage feedback. Some application circuits require auxiliary primary- or secondary-side rails to accommodate the supply limits of other external devices. Switching power dissipation in the LT8310 may be reduced by driving the INTVCC regulator externally from a third winding. Rather than stipulate a maximum current and core flux limit for DC/DC converter transformers, most vendors specify a power rating, an operating frequency range and a minimum magnetizing inductance. While flux capability ( saturation) is important, most manufacturers specify a power rating. For a lower minimum load current, choose less magnetiz- ing current/more magnetizing inductance.

For more information www.linear .com/L T8310 applicaTions inForMaTion Table 2 provides some recommended transformer vendors. Table 2.Recommended T ransformer Manufacturers MANUFACTURER WEB ADDRESS Champs Technologies www.champs-tech.com Coilcraft www.coilcraft.com Cooper-Coiltronics www.cooperet.com Pulse Electronics www.pulseelectronics.com Würth-Midcom www.we-online.com Resonant Reset Capacitor Selection The reset capacitor value must be sized to allow a half period of a sine wave to complete during the shortest off-time the switch normally experiences, namely when VIN is lowest and the duty cycle is greatest. The LT8310’s maximum duty cycle clamp of 78% typical/82% maximum (see the Electrical Characteristics section) sets a lower bound on the off-time of 18% of the period. Minimum input voltage, turns ratio, and output voltage target determine the largest duty cycle in steady state operation, D MAX. The resonant reset time, tRST, must fall between the two: 0.18 • tSW < tRST < (1 - DMAX) • tSW [29] The maximum switch node voltage, VSW(MAX), occurs at the peak of the resonance when the input voltage is greatest. In practical circuits, the switch node might slew beyond VIN before resonating, it might initially spike, and then have a high frequency ripple, or it might not complete resonance if the available reset time is too short—all of which change the peak voltage. Estimate the maximum switch voltage with Equation 30, and increase it by at least 20% when choosing the voltage rating of the reset capacitor. VSW(MAX) = VIN(MAX) +VOUT(TARG) • NP NS ⎟ • π 2 • tSW tRST [30] A COG/NPO type capacitor is the best choice for the reso- nant reset capacitor—first, for its negligible microphonic action that would otherwise cause electronic or audio interference, and second, for its excellent voltage linearity and flatness over temperature, which makes for consistent timing across operating conditions and less margining of other components and specifications. An initial design value for the resonant reset capacitor requires estimates of the transformer’s magnetizing in - ductance (Lµ) and MOSFET output capacitance (COSS), in addition to the reset time target (Equation 31). CRST = tRST π ⎝⎜ ⎞

1 Lµ − COSS [31] Board layout, transformer windings, and the forward diodes also contribute to the total switch node capacitances, and may be subtracted from the resonant capacitor value as required. Keep the resonant reset capacitor close to the MOSFET’s drain at one terminal and well grounded with a short trace at the other terminal. Prototyping to characterize the actual reset behavior is highly recommended. In step-up applications (where N P/NS < 1), splitting the capacitance between the primary-side switch node and the secondary-side forward node may help reduce switch node ringing. The secondary-side capacitor value reflects to the primary-side by a factor of (NS/NP)2. Primary Switch MOSFET Selection Important parameters for the primary N-channel MOSFET switch include the maximum drain-source voltage rating (VDS), the gate-source threshold voltage (V GS), the on- resistance (RDS(ON)), the gate charge (QG), the maximum drain current (ID), and the thermal resistances (θJC and θJA). The drain-source breakdown voltage (BVDSS or VDS(MAX)) is the key to MOSFET selection because the primary switch experiences a maximum voltage significantly above the input (see Figure 3), which was estimated in Equation 30. Many available power MOSFETs are avalanche-rated, and will easily withstand occasional overvoltage, but regular avalanching is inefficient, and can be destructive depend- ing on energy, frequency, and temperature. Derating the result of Equation 30 by at least 20% and prototyping the circuit are recommended design procedures. An internal current limit on the INTVCC output protects the LT8310 from excessive on-chip power dissipation. The minimum value of this current should be considered when choosing the main N-channel MOSFET and the operating frequency. Selection of a lower QG MOSFET allows higher

For more information www.linear .com/L T8310 applicaTions inForMaTion switching frequencies, which leads to smaller magnetics. The required switching current, I GATE, can be calculated using Equation 32, see the Thermal Considerations section for further details. IGATE = QG • fSW [32] The power dissipated in the primary MOSFET in a forward converter is described by Equation 33. The first term represents the conduction loss in the device, and the second term represents the switching loss. C RSS is the reverse-transfer capacitance, which is usually specified in the MOSFET characteristics. For maximum efficiency, RDS(ON) and CRSS should be minimized. PSW =I2 L(MAX) •RDS(ON) •DMAX +2 • V2 IN • CRSS • fSW • IL(MAX) [33] From the known power dissipated in the main MOSFET, its junction temperature can be obtained using Equation 34. TJ must not exceed the MOSFET maximum junction temperature rating. It is recommended to measure the MOSFET temperature in steady state to ensure that absolute maximum ratings are not exceeded. TJ = TA + PSW • θJA = TA + PSW • (θJC + θCA) [34] Input Capacitor Selection The input capacitor supplies the transient input current through to the transformer and main switch, so it must be sized according to transient current requirements. Forward converters experience discontinuous input currents on par with the load current divided by the transformer turns ratio. The switching frequency, output current, and tolerable input voltage ripple are key inputs to estimating the capacitor value required to limit input voltage ripple to a specified level. An X7R type ceramic capacitor is usually the best choice since it has the least variation with temperature and DC bias. Low ESR and ESL at the switching frequency are necessary to avoid excess spiking of the input voltage. To achieve RMS input ripple of V IN(RIPPLE), the input capacitor for a forward converter can be estimated using Equation 35. For example, 15µF is an appropriate selec- tion for 100 mV RMS ripple on a 350kHz converter with 2A maximum load current and a transformer turns ratio of NP/NS = 2. CIN = 0.5 • IL(MAX) fSW • VIN(RIPPLE) • NP / NS( ) [35] Table 3 provides some recommended ceramic capacitor vendors. Table 3.Recommended Ceramic Capacitor Manufacturers MANUFACTURER WEB ADDRESS Kemet www.kemet.com Murata www.murata.com Taiyo Yuden www.t-yuden.com TDK www.tdk.com Inductor Selection The inductor used with the LT8310 should have a saturation current rating appropriate to the maximum load current, and thus appropriate to the switch current rating and R SENSE resistor. For applications with no output voltage feedback, choose an inductor value that keeps ripple current low in support of the minimum load current target, I L(MIN). If the contribution of the output inductor equals that of the reflected transformer magnetizing inductance (Lµ), a first cut for the inductor value based on operating frequency, output voltage, and minimum duty cycle is: L1= VOUT • 1−DMIN( ) fSW • IL(MIN) [36] Once both the transformer and inductor are chosen, the minimum load current estimate in Equation 27 should be re-evaluated, and the component selections modified if necessary.

voltage, minimum duty cycle and transformer turns ratio.

RSENSE NP / NS( ) • 20mV [37] Table 4 provides some recommended inductor vendors.

Table 4. Recommended Inductor Manufacturers tion current after resonant reset completes (see Figure 3). threshold Schottky diodes with low series resistance. Table 5 provides some recommended diode vendors. Table 5. Recommended Diode Manufacturers. diodes, but the advantage of smaller forward voltage drops. cross-conduction, see their data sheets for details. reverse recovery time when selecting MOSFET switches.

it and meet the new load demand. Equation 39, to minimize its effect. with good temperature and bias stability. same performance, and should be avoided.

L1 [38] ESR2  L1 CL [39] In steady-state, output voltage ripple arises from induc- tor ripple current that charges and discharges the output capacitor, and from the voltage drop across its ESR. Equation 40 provides an estimate of the output ripple in relation to the nominal output voltage. VOUT(RIPPLE) ≈ L1• CL• f2 SW + ESR L1• fSW ⎟⎟ • VOUT(NOM) [40] Programming the Output V oltage in Direct-Wired Feedback Applications For nonisolated applications, direct-wired feedback from the load to the FBX pin configures the LT8310 as a tra - ditional peak current mode controlled forward converter. The FBX pin features dual references (1.6V and –0.8V) that support DC/DC conversion or DC/DC inversion auto- matically. Proper selection of the transformer turns ratio also makes large conversion/inversion ratios (step-down or step-up) possible without relying on extremely low or high duty cycles, which improves efficiency. In wired ap- plications, the output voltage (VOUT) is set by a resistor divider, as shown in Figure 8.

Figure 8. Wired Feedback for Nonisolated

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which usually governs the output voltage programming. Figure 9. Key Components of an Isolated Nonsynchronous Supply

8310 F09

For more information www.linear .com/L T8310 applicaTions inForMaTion Thermal Considerations The LT8310 is rated to a maximum input voltage of 100V. Careful attention must be paid to the internal power dis - sipation of the IC at higher input voltages to ensure that a junction temperature of 125°C (150°C for H-grade) is not exceeded. This junction limit is especially important when operating at high ambient temperatures. At a junction temperature of 165°C, the thermal limiter shuts down the system, which pulls the GATE pin to GND, pulls the SOUT pin to INTVCC, and discharges the soft-start (SS) pin to GND. Switching can resume after the device temperature falls by 10°C. This function is intended to protect the device during momentary thermal overload. In many applications, the majority of the power dissipation in the IC comes from the supply current needed to drive the gate capacitance of the external power MOSFET(s). For the main switch driven by the GATE pin, and a switch (if present) on the SOUT pin, the gate-drive current can be calculated for each as in Equation 7. A low Q G power MOSFET should always be used when op- erating at high input voltages and the switching frequency should also be chosen carefully to ensure that the IC does not exceed a safe junction temperature. The internal junc- tion temperature of the IC can be estimated by: TJ = TA + VIN • (IQ + IDRIVE (TOT)) • θJA [44] where TA is the ambient temperature, IQ is the quiescent current of the part (maximum 4mA), and θJA is the pack- age’s junction-to-ambient thermal impedance (38°C/W). For example, an application having T A(MAX) = 85°C, VIN(MAX) = 80V, fSW = 200kHz, and having a MOSFET with QG = 30nC, the maximum IC junction temperature will be approximately: TJ = 85°C + 80V • (4mA + 30nC • 200kHz) The exposed pad on the bottom of the package must be soldered to a ground plane. This ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the IC. The LT8310’s internal power dissipation can be reduced by supplying the GATE and SOUT pins (and some internal circuits) from an external source, such as a regulated auxiliary transformer winding. The INTV CC pin may be overdriven as long as 10.5V < V INTVCC(MAX) < V IN(MIN), which avoids back-driving the VIN pin. The practical up- per limit of IN TVCC overdrive is 17.4V (typ) where the regulator’s overvoltage threshold shuts down switching. PCB Layout / Thermal Guidelines For proper operation, PCB layout must be given special attention. Critical programming signals must be able to coexist with high dv/dt signals. Compact layout can be achieved but not at the cost of poor thermal management. The following guidelines should be followed to approach optimal performance. Ensure that a local bypass capacitor is used (and placed as close as possible) between V IN and GND for the controller IC(s). 2. The critical programming resistor for timing, RT, must use short traces to both the RT pin and the GND pin (exposed pad). Keep traces to the RT pin and the DFIL T pin separated. 3. The critical programming resistor for duty cycle, RSET, must use short traces to both the RDVIN pin and the INTVCC pin. 4. The current sense resistor for the forward converter must use short Kelvin connections to the SENSE pin and GND pin (exposed pad).

For more information www.linear .com/L T8310 applicaTions inForMaTion 5. High dv/dt lines should be kept away from both critical programming resistors (RT, RSET), the current sense inputs, the VC pin, the UVLO and OVLO pins, and the FBX feedback traces. 6. Gate driver (GATE) and synchronization (SOUT) traces should be kept as short as possible. 7. When working with high power components, multiple parallel components are the best method for spread- ing out power dissipation and minimizing temperature rise. In particular, multiple copper layers connected by vias should be used to sink heat away from each power MOSFET and power diode. 8. Keep high switching current paths away from signal grounding. Also minimize trace lengths for those high current switching paths to minimize parasitic inductance. 9. For synchronous applications, ensure that the pulse transformer (from LT8310’s SOUT pin to the SYNC pin of the secondary-side controller) is properly damped and not effected by high dv/dt traces. This will prevent false triggering of the synchronous FETs, avoiding cross-conduction and repeated soft-start retry (hiccup mode) behavior.

For more information www.linear .com/L T8310 Typical applicaTions

78 Watt Isolated Nonsynchronous Forward Converter

4.7µF VIN 36V TO 72V VOUT 12V 0.6A TO 6.5A –VOUT –VIN VIN 86.6k 1.74k 1.43k RSENSE 0.025/uni03A9 102k 49.9k 200kHz 2.2µF 100V 47µHT1 2:1 150pF 250V NPO

8310 TA02a

22µF 35V 33µF 35V TANT 10nF 1µF 100V 0.47µF NC D1: VISHAY VB30120S D2: VISHAY VBT3080S L1: WÜRTH WE74435584700 M1: INFINEON IPD600N25N3 T1: WÜRTH WE750313917 Output Voltage Line Regulation Efficiency vs Load Current VIN (V) VOUT (V) 11.5 12.0 12.5 60 80

8310 TA02b

11.0 10.5 10.0 40 50 70 13.0 13.5 14.0 IOUT = 0.6A IOUT = 1.5A IOUT = 3.5A IOUT = 6.5A IOUT (A) 3 5

8310 TA02c

EFFICIENCY (%) VIN = 36V VIN = 48V VIN = 60V VIN = 72V

For more information www.linear .com/L T8310

78 Watt Isolated Synchronous Forward Converter

Output Voltage Line Regulation Efficiency vs Load Current L T8310 L TC3900 UVLO CG CS+ VCC CS– SYNC FG OVLO TIMER GND GATE SENSE GND SOUT FBX VC NC 2.2µF 100V V IN 36V TO 72V VOUT 12V 0A TO 6.5A OUT–VIN VIN 86.6k 1.74k 1.43k 1µF 100V 22µH 2:1 1:1 220pF 150pF 250V NPO R SENSE 0.025/uni03A9 5.6k 22µF 25V 47µF 25V TANT 330/uni03A9

8310 TA03a

L1: WÜRTH WE74435572200 M1: INFINEON IPD600N25N3 M2: INFINEON BSC077N12NS3 M3: INFINEON BSC076N06NS3 Q1: CENTRAL SEMI MMBT5551 T1: WÜRTH WE750313917 T2: PULSE PE-68386NL DFIL T RT SS SYNC INTVCC RDVIN NC 4.7µF 16V 102k 49.9k 200kHz 10nF 0.47µF 5.6k 0.1µF 50V 10k 270k 10/uni03A9 100pF 4.7µF 10V IOUT (A) VOUT (V) 13.5

8310 TA03b

12.0 11.0 1 2 4 10.5 10.0 14.0 13.0 12.5 11.5 5 6 7 VIN = 36V VIN = 48V VIN = 72V IOUT (A) 3 5

8310 TA03c

EFFICIENCY (%) VIN = 36V VIN = 48V VIN = 60V VIN = 72V

For more information www.linear .com/L T8310 Typical applicaTions

78 Watt Isolated Nonsynchronous Forward Converter with Opto Feedback

4.7µF 16V 2.2nF 0.01µF 10k 100k 0.1µF 50V R SENSE 0.025/uni03A9 3300µH VIN 36V TO 72V VOUT 12V 0A TO 6.5A OUT –VIN VIN 86.6k 1.74k 1.43k 130k VINTVCC VINTVCC 6.8nF49.9k 200kHz 2.2µF 100V 22µHT1 2:1 150pF 250V NPO 6.65k 909k 20.0k MOC 207 D1: VISHAY VB30120S D2: VISHAY VBT3080S D3, D4: BAV3004 D5: BAS516 L1: WÜRTH WE744355722 L2: COILCRAFT LPS5030-335MRB M1: INFINEON IPD600N25N3 Q1: CENTRAL SEMI MMBT5551 T1: WÜRTH WE750313917 11.3k

8310 TA04a

6.34k 330/uni03A9 10/uni03A9 330/uni03A9 4.7µF 16V220pF

• C4 22µF 25V 33µF 25V TANT 1µF 100V 0.47µF NC L T4430 VIN GND OPTO FB OC COMP 10V Output Voltage Line Regulation Efficiency vs Load Current IOUT (A) VOUT (V) 11.5 12.0 12.5 3 7

8310 TA04b

11.0 10.5 10.0 1 2 4 5 6 13.0 13.5 14.0 VIN = 36V TO 72V IOUT (A) 3 5 EFFICIENCY (%) VIN = 36V VIN = 48V VIN = 60V VIN = 72V

For more information www.linear .com/L T8310 Typical applicaTions Wide VIN, 60 Watt Isolated 8V Rail for Low Voltage Regulators Output Voltage Line Regulation Efficiency vs Load Current L T8310 L TC3900 UVLO CG CS+ VCC CS– SYNC FG OVLO TIMER GND GATE SENSE GND SOUT FBX VC NC 2.2µF 100V V IN 9V TO 42V VOUT 0A TO 7.5A –VOUT–VIN VIN 39.2k 5.62k 1.24k 1µF 100V 3300µH 3:4 1:1 220pF 2200pF 100V NPO R SENSE 0.008/uni03A9 30.1k 22µF 25V 22µF 25V TANT 33µH 330/uni03A9

8310 TA05a

D1, D2: BAV3004 D3: CENTRAL SEMI CMMR1U-02 L1: WÜRTH WE74435583300 L2: COILCRAFT LPS5030-335MRB M1: INFINEON BSC057N08S3-GL NOTE 1: IN GENERAL, TWO STACKED 5V TO 6V ZENERS WILL HAVE LESS THERMAL VARIATION THAN A SINGLE 10V TO 12V ZENER NOTE 2: FOR EXAMPLE, USE THREE (3) PARALLELED 10k, 1W RESISTORS M2: INFINEON BSC067N06LS3-G M3: INFINEON BSC060N10S3-G Q1: CENTRAL SEMI MMBT5551 T1: WÜRTH WE750341138 T2: PULSE PE-68386NL DFIL T 10nF 10/uni03A9 RT SS SYNC INTVCC RDVIN NC 4.7µF 16V 25.5k 49.9k 200kHz 2.2nF 0.47µF 30.1k 0.1µF 50V 470/uni03A9 10/uni03A9 3.3k 3W NOTE 2 NOTE 1 5.6V 5.6V 220pF 4.7µF 16V 33nF 100V 270k + IOUT (V) VOUT (V) 8.0 9.0

8310 TA05b

7.0 6.0 2 4 61 3 5 7 10.0 7.5 8.5 6.5 9.5 VIN = 9V VIN = 18V VIN = 30V VIN = 42V IOUT (A) EFFICIENCY (%) 2 4 6 8

8310 TA05c

VIN = 9V VIN = 18V VIN = 30V VIN = 42V

For more information www.linear .com/L T8310 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE20(16) (CB) TSSOP REV 0 0512 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 5 6 7 8 9 10 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 18 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC Variation: FE20(16) 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1924 Rev Ø) Exposed Pad Variation CB

For more information www.linear .com/L T8310  LINEAR TECHNOLOGY CORPORATION 2014 LT 0814 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T8310 relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT3752/LT3752-1 Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller Input Voltage Range: LT3752: 6.5V to 100V, LT3752-1: Limited Only by External Components LT3753 Active Clamp Synchronous Synchronous Forward Controller Input Voltage Range: 8.5V to 100V LT8311 Preactive Secondary-Side Synchronous Forward Controller Optimized for Use with Primary-Side LT3752/-1, LT3753 and LT8310 Controllers LT C 3765/LTC3766 Synchronous No-Opto Forward Controller Chip Set with Active Clamp Reset Direct Flux Limit™, Supports Self-Starting Secondary Forward Control LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers High Efficiency with On-Chip MOSFET Drivers, Adjustable Synchronous Rectification Timing LTC3721-1/LTC3721-2 Nonsynchronous Push-Pull and Full-Bridge Controllers Minimizes External Components, On-Chip MOSFET Drivers LTC3722/LTC2722-2 Synchronous Full-Bridge Controllers Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable Synchronous Rectification Timing LT3748 100V Isolated Flyback Controller 5V ≤ V IN ≤ 100V, No-Opto Flyback , MSOP-16 with High Voltage Spacing LT3798 Off-Line Isolated No-Opto Flyback Controller with Active PFC V IN and VOUT Limited Only by External Components LTC3900 Synchronous Rectifier N-Channel MOSFET Driver for Forward Converters Programmable Timeout and Reverse-Inductor Protection, T ransformer Synchronization, SSOP-16 LT4430 Secondary-Side Optocoupler Driver with Reference Voltage Overshoot Control Prevents Output Overshoot During Start-up and Short-Cir cuit Recovery 94% Efficient, 150W Isolated Synchronous Forward Converter L T8310 UVLO OVLO DFIL T RT SS SYNC INTVCC RDVIN GATE SENSE GND SOUTNC VC FBX 4.7µF 16V 3.9nF 220pF VIN 36V TO 72V –VIN VIN 86.6k 1.74k 1.43k RSENSE 0.012/uni03A9 121k VINTVCC VINTVCC 40.2k 249kHz 4.7µF 100V 8:4 390pF 250V 90.9k 178/uni03A9 8µH 178/uni03A9

• 1.25:1
• 1µF 100V 0.47µF 20k 62k 10k 499k3.3k 100k 11.3k 100k 20k 22nF 499/uni03A9 560/uni03A9 PS2801-1 100pF 1µF 22nF 4.7µF D1: CENTRAL SEMI CMMR1U-02 L1: CHAMPS HRPQI2050-08 M1: INFINEON BSC320N20NS3G M2: INFINEON BSC042NE7NS3 M3: FAIRCHILD SEMI FDMS86101DC T1: PULSE PA0423 T2: PULSE PA3493NL 2.2µF

8310 TA06a

–VOUT 68pF 47µF ×2 470µF V OUT 12V 0A TO 12.5A 3.9nF FG CSP CG CSN FB FSW CSW VIN SYNC COMP OPTO PGOOD INTVCC PMODE SS GNDTIMER L T8311

Selected Specification

Linear Technology LT8310 overview.

Summary

100VIN Forward Converter Controller

Description

100VIN Forward Converter Controller

Source title LT8310_15 Datasheet(PDF) - Linear Technology

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