LT5546

LT5546 LINER

Document overview

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Technical content

n 17MHz I/Q Lowpass Output Noise Filters n Wide Range 1.8V to 5.25V Supply Voltage n Frequency Range: 40MHz to 500MHz n THD < 0.14% (–57dBc) at 800mVP-P Differential Output Level n IF Overload Detector n Log Linear Gain Control Range: –7dB to 56dB n Baseband I/Q Amplitude Imbalance: 0.2dB n Baseband I/Q Phase Imbalance: 0.6° n 7.8dB Noise Figure at Max Gain n Input IP3 at Low Gain: – 1dBm n Low Supply Current: 24mA n Low Delay Shift Over Gain Control Range: 2ps/dB n Outputs Biased Up While in Standby n 16-Lead QFN 4mm × 4mm Package with Exposed Pad 40MHz to 500MHz VGA and I/Q Demodulator with 17MHz Baseband Bandwidth , LTC and LT are registered trademarks of Linear Technology Corporation. Total Harmonic Distortion vs IF Input Level at 1.8V Supply n GPS IF Receivers n Satellite IF Receivers n VHF/UHF Receivers n Wireless Local Loop 2xLO+ 2xLO– IF+ IF– EN STBY VCC IOUT+ IOUT– QOUT+ QOUT– GND 1.8VC2 1µF 1nF 1.8pF STANDBY 2xLO 560MHz INPUT 280MHz IF INPUT 10pF

5546 TA01

3.3pF 3.3pF GAIN CONTROL ENABLE IF DETVCTRL The LT 5546 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA) and 17MHz I/Q baseband bandwidth designed for low volt- age operation. It supports standards that use a linear modu- lation format. The chip consists of a VGA, quadrature down- converting mixers and 17MHz lowpass noise filters (LPF). The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF down- conversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linear- in-dB relationship to the control input voltage. Hard-clip- ping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The –3dB corner frequency of the noise filters is approximately 17MHz and has a first order roll- off. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip. IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –25 –30 –35 –40 –45 –50 –55 –60 –50 –40 –30 –20

5546 TA01b

–10 fIF, 1 = 280MHz fIF, 2 = 280.1MHz f2xLO = 570MHz 800mVP-P DIFFERENTIAL OUT FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U

Operating Ambient Temperature Voltage on Any Pin ORDER PART NUMBER TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD IS GND (PIN 17) (MUST BE SOLDERED TO PCB) LT5546EUF ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W (Note 1) ELECTRICAL CHARACTERISTICSVCC = 3V, f2xLO = 570MHz, P2xLO = –5dBm (Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Consult LTC Marketing for parts specified with wider operating temperature ranges. 16 15 14 13 5 6 7 8 TOP VIEW UF PACKAGE 16-LEAD (4mm × 4mm) PLASTIC QFN 1GND IF+ IF– GND STBY 2xLO+ 2xLO– EN IOUT+ IOUT– QOUT+ QOUT– VCC VCTRL IF DET VCC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IF Input fIF Frequency Range 40 to 500 MHz Nominal Input Level R SOURCE = 200Ω Differential –76 to –19 dBm Input Impedance IF +, IF– to GND, EN = VCC 100Ω //1.2pF IF+, IF– to GND, EN = GND 1pF NF Noise Figure at Max Gain V CTRL = 1.7V 7.8 dB GL Min Gain (Note 4) V CTRL = 0.2V 1.6 6 dB GH Max Gain (Note 4) V CTRL = 1.7V 49 56 dB IIP3 Input IP3, Min Gain P IF = –22.5dBm (Note 7) –1 dBm Input IP3, Max Gain P IF = –75dBm (Note 7) –49 dBm IIP2 Input IP2, Min Gain V CTRL = 0.2V (Note 9) 36 dBm Input IP2, Max Gain V CTRL = 1.7V (Note 9) –25 dBm Demodulator I/Q Output Nominal Voltage Swing (Note 6) 0.8 V P-P Clipping Level (Note 6) 1.47 V P-P DC Common Mode Voltage V CC – 1.19 V I/Q Amplitude Imbalance (Note 8) 0.14 0.6 dB I/Q Phase Imbalance (Note 8) 0.6 3 Deg DC Offset (Notes 6, 8) 21 mV Output Driving Capability Single Ended, C LOAD ≤ 10pF 2 1.5 k Ω ro Small-Signal Output Impedance (Note 6) 180 Ω STBY to Turn-On Delay 0.3 µs I/Q Output 1dB Compression –10 dBm I/Q Output IM3 P IF, 1 = –25.5dBm, 280MHz – 49 dBc PIF, 2 = –25.5dBm, 280.1MHz (Note 7) UF PART MARKING 5546

VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm (Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the –40°C to 85°C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the configuration of Figure 6. The IF input transformer loss is substracted from the measured values. Note 4: Power gain is defined here as the I (or Q) output power into a 4kΩ differential load, divided by the IF input power in dB. To calculate the voltage gain between the differential I output (or Q output) and the IF input, including ideal matching network, 10 • log(4kΩ /50) = 19dB has to be added to this power gain. Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2 transformer with 240Ω shunt resistor, 2xLO input power can be reduced to –10dBm, without degrading the phase imbalance. See Figure 11 and Figure 6. Note 6: Differential between IOUT+ and IOUT– (or differential between QOUT+ and QOUT–). Note 7: The gain control voltage VCTRL is set in such a way that the differential output voltage between IOUT+ and IOUT– (or differential between QOUT+ and QOUT–) is 800mVP-P, with the given input power PIF. IF frequencies are 280MHz and 280.1MHz, with f2xLO = 570MHz. Note 8: The typical parameter is defined as the mean of the absolute values of the data distribution. Note 9: IF frequency is 125MHz, with f2xLO = 502MHz. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Variable Gain Amplifier (VGA) Gain Slope Linearity Error V CTRL = 0V to 1.4V ±0.5 dB Temperature Gain Shift T = –40 °C to 85°C, VCTRL = 0V to 1.4V ±0.4 dB Gain Control Response Time Settled within 10% of Final Value 90 ns Gain Control Voltage Range 0 to 1.7 V Gain Control Slope 41 dB/V Gain Control Input Impedance To Internal 0.2V Reference 25 k Ω Delay Shift Over Gain Control Measured Over 10dB Step 2 ps/dB Baseband Lowpass Filter (LPF) –3dB Cutoff Frequency 13 17 MHz Amplitude Roll-Off at 50MHz –9 dB Group Delay Ripple 1n s 2xLO Input f2xLO Frequency Range 80 to 1000 MHz P2xLO Input Power 1:2 Transformer with 240 Ω Shunt Resistor (Note 5) –20 –5 dBm Input Power LC Balun (Note 5) –10 dBm Input Impedance Differential Between 2xLO + and 2xLO– 800Ω //0.4pF DC Common Mode Voltage V CC – 0.4 V IF Detector IF Detector Range Referred to IF Input –30 to 8 dBm Output Voltage Range For P IF = –30dBm to 8dBm 0.27 to 1.2 V Detector Response Time With External 1.8pF Load, 80 ns Settling within 10% of Final Value Power Supply VCC Supply Voltage 1.8 5.25 V ICC Supply Current EN = High, STBY = Low or High 24 34 mA IOFF Shutdown Current EN, STBY < 350mV 0.2 30 µA ISTBY Standby Current EN = Low; STBY = High 3.6 6 mA Mode Enable Enable Pin Voltage EN = High 1 V Disable Enable Pin Voltage EN = Low 0.5 V Standby Standby Pin Voltage STBY = High 1 V No Standby Standby Pin Voltage STBY = Low 0.5 V

Supply Current vs Supply Voltage Gain and Noise Figure vs Control Voltage at 3V Supply Gain and Noise Figure vs Control Voltage at 1.8V Supply Gain Flatness vs Control Voltage at 3V Supply Gain and Noise Figure vs Control Voltage and VCC Gain and Noise Figure vs IF Frequency at 3V Supply TYPICAL PERFOR A CE CHARACTERISTICSUW VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) SUPPLY VOLTAGE (V) 1.75 SUPPLY CURRENT (mA) 2.25 2.75 3.25 3.75

5546 G01

4.25 4.75 5.25 –40°C 25°C 85°C VCTRL (V) GAIN AND NOISE FIGURE (dB) 1.5

5546 G02

0.6 GAIN NF –10 0.3 0.9 1.2 1.8 GAIN AT 25°C NF AT 25°C GAIN AT –40°C NF AT –40°C GAIN AT 85°C NF AT 85°C fIF = 284MHz f2xLO = 570MHz VCTRL (V) GAIN AND NOISE FIGURE (dB) 1.5

5546 G03

0.6 GAIN NF –10 0.3 0.9 1.2 1.8 GAIN AT –40°C NF AT 25°C GAIN AT 25°C NF AT –40°C GAIN AT 85°C NF AT 85°C fIF = 284MHz f2xLO = 570MHz VCTRL (V) –0.5GAIN DEVIATI0N FROM LINEAR FIT (dB) –0.3 –0.1 0.1 0.3 0.6 0.9

5546 G04

1.2 0.3 0.5 –0.4 –0.2 0.2 0.4 1.5 –40°C 85°C 25°C VCTRL (V) GAIN AND NOISE FIGURE (dB) 1.5

5546 G05

0.6 GAIN NF –10 0.3 0.9 1.2 1.8 GAIN AT 1.8V NF AT 1.8V GAIN AT 3V NF AT 3V GAIN AT 5.25V NF AT 5.25V fIF = 284MHz f2xLO = 570MHz IF FREQUENCY (MHz) –10 GAIN AND NOISE FIGURE (dB) 100 1000

5546 G06

GAIN, VCTRL = 1.6V GAIN, VCTRL = 0.9V GAIN, VCTRL = 0.2V NF, VCTRL = 1.6V NF, VCTRL = 0.9V NF, VCTRL = 0.2V

vs IF Input Power at 3V Supply and 800mVP-P Differential Out Total Harmonic Distortion vs IF Input Power and IF Frequency Total Harmonic Distortion vs IF Input Power at 1.8V Supply and 800mVP-P Differential Out Total Harmonic Distortion vs IF Input Power and Supply Voltage LPF Frequency Response vs Baseband Frequency and Temperature LPF Frequency Response vs Baseband Frequency and Supply Voltage Total Harmonic Distortion vs IF Input Power at 500mV P-P Differential Out IF Detector Output Voltage vs IF Input CW Power at 3V Supply IF Detector Output Voltage vs IF Input CW Power at 1.8V Supply TYPICAL PERFOR A CE CHARACTERISTICSUW VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30

5546 G07

–50 –40 –20 –10 –25 –30 –35 –40 –45 –50 –55 –60 85°C fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz 25°C –40°C IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30

5546 G08

–50 –40 –20 –10 –25 –30 –35 –40 –45 –50 –55 –60 fIF = 280MHz fIF = 40MHz 800mVP-P DIFFERENTIAL OUT 3V SUPPLY fIF = 500MHz IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30

5546 G09

–50 –40 –10 –20 –25 –30 –35 –40 –45 –50 –55 –60 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz –40°C 85°C 25°C IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30

5546 G10

–50 –40 –20 –10 –25 –30 –35 –40 –45 –50 –55 –60 1.8V 5.25V 800mVP-P DIFFERENTIAL OUT fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz IF INPUT POWER EACH TONE (dBm) THD (dBc) –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –40 –35 –30 –40°C 25°C 85°C –25

5546 G11

–20 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz VCC = 3V BASEBAND FREQUENCY (MHz) –10 MAGNITUDE (dB) 5 10 15 20 30 40 50

5546 G12

VCC = 3V –40°C 85°C 25°C BASEBAND FREQUENCY (MHz) –10 MAGNITUDE (dB) 5 10 15 20 30 40 50

5546 G13

TA = 25°C 1.8V 5.25V IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 85°C –40°C –20 –10 0

5546 G14

25°C fIF = 280MHz IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 85°C –40°C –20 –10 0

5546 G15

25°C fIF = 280MHz

IF Detector Output Voltage vs IF Input CW Power and IF Frequency IF Detector Output Voltage vs IF Input CW Power and Supply Voltage Phase Relation Between I and Q Outputs vs LO Input Power GND (Pins 1, 4 and 17): Ground. Pins 1 and 4 are connected to each other internally. The exposed pad (Pin 17) is not connected internally to Pins 1 and 4. For chip functionality, the exposed pad and either Pin 1 or Pin 4 must be connected to ground. For best RF performance, Pin 1, Pin␣ 4 and the exposed pad should be connected to RF ground. IF +, IF– (Pins 2, 3): Differential Inputs for the IF Signal. Each pin must be DC grounded through an external inductor or RF transformer with central ground tap. This path should have a DC resistance lower than 2Ω to ground. V CC (Pins 5 and 8): Power Supply. These pins should be decoupled to ground using 1000pF and 0.1µF capacitors. VCTRL (Pin 6): VGA Gain Control Input. This pin controls the IF gain and its typical input voltage range is 0.2V to 1.7V. It is internally biased via a 25k resistor to 0.2V, setting a low gain if the V CTRL pin is left floating. IF DET (Pin 7): IF Detector Output. For strong IF input signals, the DC level at this pin is a function of the IF input signal level. EN (Pin 9): Enable Input. When the enable pin voltage is higher than 1V, the IC is completely turned on. When the input voltage is less than 0.5V, the IC is turned off, except the part of the circuit associated with standby mode. 2xLO –, 2xLO+ (Pins 10, 11): Differential Inputs for the 2xLO Input. The 2xLO input frequency must be twice that of the IF frequency. The internal bias voltage is VCC – 0.4V. STBY (Pin 12): Standby Input. When the STBY pin is higher than 1V, the standby mode circuit is turned on to prebias the I/Q buffers. When the STBY pin is less than 0.5V, the standby mode circuit is turned off. Q OUT–, QOUT+ (Pins 13, 14): Differential Baseband Out- puts of the Q Channel. Internally biased at VCC – 1.19V. IOUT–, IOUT+ (Pins 15, 16): Differential Baseband Outputs of the I Channel. Internally biased at VCC – 1.19V. UUUPI FU CTIO S TYPICAL PERFOR A CE CHARACTERISTICSUW VCC = 3V, f2×LO = 570MHz, P2×LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kΩ differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 –20 –10 0

5546 G16

fIF = 280MHz 1.8V 5.25V IF INPUT CW POWER (dBm) –40 1.2 1.4

5546 G17

1.0 0.8 –30 –20 –10 10 0.6 0.4 0.2 IF DET OUTPUT (V) VCC = 3V fIF = 500MHz fIF = 40MHz fIF = 280MHz LO INPUT POWER (dBm) –20 –5 5

5546 G18

–15 –10 01 0 PHASE (DEG) fIF = 284MHz, 25°C fIF = 284MHz, –40°C fIF = 284MHz, 85°C fIF = 40MHz, 25°C fIF = 500MHz, 25°C VCC = 3V

2·LO+ 2·LO– IF+ IF– IF DET EN STBY IOUT+ IOUT– QOUT+ QOUT– 90° 5546 BD 5 8 9 1 4 17 12 VCTRL VCC VCC VGA I-MIXER Q-MIXER CLIPPER CLIPPERLPF LPF DETECTOR The LT5546 consists of a variable gain amplifier (VGA), I/Q demodulator, quadrature LO generator, lowpass fil- ters (LPFs), clipping amplifiers (clippers) and bias cir- cuitry. The IF signal is fed to the inputs of the VGA. The VGA gain is typically set by an external signal in such a way that the amplified IF signal delivered to the I/Q mixers is constant. The IF signal is then converted into I/Q baseband signals using the I/Q down-converting mixers. The quadrature LO signals that drive the mixers are internally generated from the on-chip divide-by-two circuit. The I/Q signals are passed through first-order low-pass filters and subse- quently a pair of hard-clipping amplifiers (clippers). After externally setting the required gain, these amplifiers should not clip. However, in the event of overload, they reduce the settling time of any (optional) external AC coupling capaci- tors by preventing asymmetrical charging and discharg- ing effects. The I/Q baseband outputs are buffered by output drivers. VGA and Input Matching The VGA has a nominal 60dB gain control range with a frequency range of 40MHz to 500MHz. The inputs of the VGA must have a DC return to ground. This can be done using a transformer with a central tap (on the secondary) or an LC matching circuit with a matched impedance at the frequency of interest and near zero impedance at DC. The differential AC input impedance of the LT5546 is about 200Ω , thus a 1:4 (impedance ratio) RF transformer with center tap can be used. In Figure 6, the evaluation board APPLICATIO S I FOR ATIOWU UU schematic is shown using a 1:4 transformer. The mea- sured input sensitivity of this board is about –80.5dBm for a 10dB signal-to-noise ratio. In the case of an L-C match- ing circuit, the circuit of Figure 1 can be used. In Table 1 the matching network component values are given for a range of IF frequencies. The matching circuit of Figure 1 approaches 180 ° phase shift between IF + and IF – in a broad range around its center frequency. However, some amplitude mismatch occurs if the circuit is not tuned to the center frequency. This leads to reduced circuit linearity performance, because one of the inputs carries a higher signal compared to the perfectly balanced case. A 10% frequency shift from the center frequency results in about a 2dB gain difference between the IF + and IF– inputs. This results in a 1.5dB higher IM3 contribution from the input stage which leads to a 0.75dB drop in IIP3. Moreover, the IIP2 of the circuit is also reduced which can lead to a higher second order harmonic contribution. The circuit can be driven single ended, but this is not recommended because it leads to a 3dB drop in gain and a considerable increase in IM5 and IM7 components. The single-ended noise figure increases by 4dB if one IF input is directly grounded and increases by 1.5dB if one IF input is grounded via a 1µH inductor. An IF input cannot be left open or connected via a resistor to ground because this will disturb the internal biasing, reducing the gain, noise and linearity performance. For optimal performance, it is important to keep the DC impedance to ground of both IF inputs lower than 2Ω . In the matching network of Figure 1, inductor L3 is used for supplying the DC bias current to the IF + input.

To keep the DC resistance of L3 below 2Ω , 120nH is used. frequency where the amplitudes of IF+ and IF– are equal. is lowered and will contribute some correcting reactance. and a gain reduction due to mismatch less than 0.3dB. Figure 1. Example L-C IF Input Matching Network at 280MHz

5546 F01

Table 1. The Component Values of Matching Network L1, L2, L3, degrees, depending on the quality factor of the network.

5546 F02

of I and Q are well matched and their phases are 90° apart. approach, the quadrature LO signals are well matched. of the three 2xLO matching networks.

5546 F03

Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band

5546 F04

Table 2. The Logic of Different Operating Modes response. The –3dB corner frequency is typically 17MHz. ground. The outputs are internally biased at VCC – 1.19V. outputs to nominal VCC – 1.19V at much reduced current. Figure 5. Simplified Circuit Schematic of I Channel

5546 F05

the STBY (or EN) input is shown. Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers COMPONENTS ARE INCLUDED FOR EVALUATION ONLY.

Figure 7. Component Side Silkscreen of Evaluation Board Figure 8. Component Side Layout of Evaluation Board Figure 9. Bottom Side Silkscreen of Evaluation Board Figure 10. Bottom Side Layout of Evaluation Board Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)

5546 F11

cluded to drive a 50Ω load for evaluation purposes only. Information furnished by Linear Technology Corporation is believed to be accurate and reliable. tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. when the evaluation board outputs are terminated in 50Ω .

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com RELATED PARTS PACKAGE DESCRIPTIO U 16-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1692) 4.00 – 0.10 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK 0.55 – 0.20 1615 BOTTOM VIEW—EXPOSED PAD 2.15 – 0.10 (4-SIDES) 0.75 – 0.05 R = 0.115 TYP 0.30 – 0.05

0.65 BSC

0.200 REF

0.00 – 0.05 (UF) QFN 0802 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.72 –0.05 0.30 –0.05

0.65 BCS

2.15 – 0.05 (4 SIDES)2.90 – 0.05 4.35 – 0.05 PACKAGE OUTLINE 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED  LINEAR TECHNOLOGY CORPORATION 2003 LT/TP 1003 1K • PRINTED IN USA PART NUMBER DESCRIPTION COMMENTS Infrastructure LT5511 High Signal Level Upconverting Mixer RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer LT5512 High Signal Level Downconverting Mixer DC-3GHz, 20dBm IIP3, Integrated LO Buffer LT5515 1.5GHz to 2.5GHz Direct-Conversion 20dBm IIP3, NF =16.8dB, Integrated LO Quadrature Generator Quadrature Demodulator LT5516 800MHz to 1.5GHz Direct-Conversion 4V to 5.25V Supply, 21.5dBm IIP3, NF = 12.8dB, Quadrature Demodulator Integrated LO Quadrature Generator LT5522 600MHz to 2.7GHz High Signal Level 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Ω Single-Ended Downconverting Mixer RF and LO Ports RF Power Detectors LT5504 800MHz to 2.7GHz RF Measuring Receiver 2.7V to 5.25V Supply, 80dB Dynamic Range, Temperature Compensated LTC5505 RF Power Detectors with >40dB Dynamic Range 2.7V to 6V Supply, 300MHz to 3.5GHz, Temperature Compensated LTC5507 100kHz to 1000MHz RF Power Detector 2.7V to 6V Supply, 48dB Dynamic Range, Temperature Compensated LTC5508 0.3GHz to 7GHz RF Power Detector 2.7V to 6V Supply, 44dB Dynamic Range, Temperature Compensated LTC5509 300MHz to 3GHz RF Power Detector –30dBm to 6dBm, 600 µA Supply Current, Temperature Compensated LTC5532 300MHz to 7GHz Precision RF Power Detector Precision V OUT Offset Control, Adjustable Gain and Offset RF Receiver Building Blocks LT5500 1.8GHz to 2.7GHz Receiver Front End 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer LT5502 400MHz Quadrature IF Demodulator with RSSI 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain, 90dB RSSI Range LT5503 1.2GHz to 2.7GHz Direct IQ Modulator and Mixer 1.8V to 5.25V Supply, Four Step RF Power Control, 120MHz Modulation Bandwid th LT5506 40MHz to 500MHz Quadrature IF Demodulator 1.8V to 5.25V, I/Q Baseband Bandwidth 8.8MHz, –40dB to 57dB Linear Power Gain with VGA