LT5517

Linear Technology

Dual 12-Bit 310Msps ADC

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 28

Technical content

LTC2158-12For more information www.linear .com/L TC2158-12 TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

n Testing and Measurement Instruments n 67.6dBFS SNR n 88dB SFDR n Low Power: 688mW Total n Single 1.8V Supply n DDR LVDS Outputs n 1.32VP-P Input Range n 1.25GHz Full Power Bandwidth S/H n Optional Clock Duty Cycle Stabilizer n Low Power Sleep and Nap Modes n Serial SPI Port for Configuration n Pin-Compatible 14-Bit Versions n 64-Lead (9mm × 9mm) QFN Package The LT C®2158-12 is a 2-channel simultaneous sampling 310Msps 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC per - formance that includes 67.6dB SNR and 88dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to undersample high frequencies with good performance. The latency is only six clock cycles. DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.6LSBRMS. The digital outputs are double data rate (DDR) LVDS. The ENC+ and ENC– inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. S/H CORRECTION LOGIC OUTPUT DRIVERS 12-BIT PIPELINED ADC CORE CLOCK/DUTY CYCLE CONTROL DA10_11 DA0_1 DB10_11 DB0_1 CLOCK ANALOG INPUT

215812 TA01

FREQUENCY (MHz) –120 AMPLITUDE (dBFS) –100 –80 –60 –40 20 40 60 80

215812 TA10b

–20 LTC2158-12 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 310Msps

215812fa For more information www.linear .com/L TC2158-12 ABSOLUTE MAXIMUM RATINGS Supply Voltage Analog Input Voltage AINA/B+, AINA/B–, PAR/SER, Digital Input Voltage CS, 0.3V to 3.9V 0.3V to 3.9V 0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2 40°C to 85°C 65°C to 150°C (Notes 1, 2) PIN CONFIGURATION TOP VIEW UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN GND V DD 1 V DD 2 GND 3 A INA+ 4 A INA– 5 GND 6 SENSE 7 V REF 8 GND 9 V CM 10 GND 11 A INB– 12 A INB+ 13 GND 14 V DD 15 V DD 16

48 OGND

47 DA2_3+

46 DA2_3–

45 DA0_1+

44 DA0_1–

41 CLKOUT

40 CLKOUT–

39 DB10_11+

38 DB10_11–

37 DB8_9+

36 DB8_9–

35 DB6_7+

34 DB6_7–

33 OGND

64 VDD

63 PAR/SER

61 SCK

60 SDI

59 SDO

58 GND

57 DA10_11

56 DA10_11–

55 DA8_9+

54 DA8_9–

53 DA6_7+

52 DA6_7–

51 DA4_5+

50 DA4_5 –

49 OVDD

ENC – 20 GND 21 OF – 22 OF + 23 NC 24 NC DB0_1 – 26 DB0_1 + 27 DB2_3 – 28 DB2_3 + 29 DB4_5 – 30 DB4_5 + 31 OV DD 32 TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2158CUP-12#PBF LTC2158CUP-12#TRPBF LTC2158UP-12 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2158IUP-12#PBF LTC2158IUP-12#TRPBF LTC2158UP-12 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2158-12For more information www.linear .com/L TC2158-12 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 Bits Integral Linearity Error Differential Analog Input (Note 6) l –2.2 ±0.6 2.2 LSB Differential Linearity Error Differential Analog Input l –0.67 ±0.1 0.67 LSB Offset Error (Note 7) l –12 ±5 12 mV Gain Error Internal Reference External Reference l –4.7 ±1.5 4.2 %FS %FS Offset Drift ±20 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±10 ppm/°C ppm/°C T ransition Noise 0.6 LSB RMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.74V < VDD < 1.9V 1.32 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l VCM – 20mV V CM VCM + 20mV V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 1.230 1.250 1.270 V IIN1 Analog Input Leakage Current 0 < AIN+, AIN– < VDD, No Encode l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –1 1 µA IIN3 SENSE Input Leakage Current 1.23V < SENSE < 1.27V l –1 1 µA tAP Sample-and-Hold Acquisition Delay Time 1 ns tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS CMRR Analog Input Common Mode Rejection Ratio 75 dB BW-3B Full-Power Bandwidth 1250 MHz DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 15MHz Input 70MHz Input 140MHz Input l 64.4 67.6 67.1 67.0 dBFS dBFS dBFS SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 15MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS Spurious Free Dynamic Range 4th Harmonic or Higher 15MHz Input 70MHz Input 140MHz Input l dBFS dBFS dBFS S/(N+D) Signal-to-Noise Plus Distortion Ratio 15MHz Input 70MHz Input 140MHz Input l 64.3 67.1 67.0 66.9 dBFS dBFS dBFS Crosstalk Crosstalk Between Channels Up to 315MHz Input –95 dB

215812fa For more information www.linear .com/L TC2158-12 INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 0.435 • VDD – 18mV 0.435 • VDD 0.435 • VDD + 18mV V VCM Output Temperature Drift ±37 ppm/°C VCM Output Resistance –1mA < IOUT < 1mA 4 Ω VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V VREF Output Temperature Drift ±30 ppm/°C VREF Output Resistance –400µA < IOUT < 1mA 7 Ω VREF Line Regulation 1.71V < VDD < 1.89V 0.6 mV/V DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) VID Differential Input Voltage (Note 8) l 0.2 V VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 1.2 1.5 V V R IN Input Resistance (See Figure 2) 10 kΩ CIN Input Capacitance (Note 8) 2 pF DIGITAL INPUTS (CS, SDI, SCK) VIH High Level Input Voltage VDD = 1.8V l 1.3 V VIL Low Level Input Voltage VDD = 1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance (Note 8) 3 pF SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) R OL Logic Low Output Resistance to GND V DD = 1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance (Note 8) 4 pF POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) l 1.74 1.8 1.9 V OVDD Output Supply Voltage (Note 9) l 1.74 1.8 1.9 V IVDD Analog Supply Current l 340 370 mA IOVDD Digital Supply Current 1.75mA LVDS Mode 3.5mA LVDS Mode l l mA mA P DISS Power Dissipation 1.75mA LVDS Mode 3.5mA LVDS Mode l l 688 738 756 812 mW mW P SLEEP Sleep Mode Power Clock Disabled Clocked at f S(MAX) mW mW P NAP Nap Mode Power Clocked at fS(MAX) 190 mW

LTC2158-12For more information www.linear .com/L TC2158-12 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fS Sampling Frequency (Note 9) l 10 310 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.5 1.2 1.6 1.6 ns ns t H ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.5 1.2 1.6 1.6 ns ns DIGITAL DATA OUTPUTS tD ENC to Data Delay CL = 5pF (Note 8) l 1.7 2 2.3 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1.3 1.6 2 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0.3 0.4 0.55 ns Pipeline Latency 6 6 Cycles SPI Port Timing (Note 8) tSCK SCK Period Write Mode Readback Mode CSDO= 20pF, RPULLUP = 2k l l 250 ns ns tS CS to SCK Set-Up Time l 5 ns tH SCK to CS Hold Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 310MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1.32VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV V OS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 V V R TERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

215812fa For more information www.linear .com/L TC2158-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2158-12: Integral Nonlinearity (INL) LTC2158-12: Differential Nonlinearity (DNL) LTC2158-12: 32K Point FFT, f IN = 15MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 70MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 150MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 383MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 421MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 223MHz, –1dBFS, 310Msps LTC2158-12: 32K Point FFT, fIN = 185MHz, –1dBFS, 310Msps OUTPUT CODE –2.0 –1.5 –1.0 –0.5INL ERROR (LSB) 0.5 2.0 1.5 1.0 4095

215812 G01

–0.50 –0.25DNL ERROR (LSB) 0.25 0.50 4095