LT5506 LINER
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Technical content
IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30 –35 –40 –45 –50 –55 –60 –50 –40 –30 –20
5506 TA01b
–10 fIF, 1 = 280MHz fIF, 2 = 280.1MHz f2xLO = 570MHz 800mVP-P DIFFERENTIAL OUT n Wide Range 1.8V to 5.25V Supply n Frequency Range: 40MHz to 500MHz n –4dB to 59dB Variable Power Gain n THD < 0.12% (–58dBc) at 800mVP-P Differential Output Level n 8.8MHz I/Q Lowpass Output Noise Filters n IF Overload Detector n Baseband I/Q Amplitude Imbalance: 0.2dB n Baseband I/Q Phase Imbalance: 0.6° n 6.8dB Noise Figure at Max Gain n Input IP3 at Low Gain: – 0.5dBm n Low Supply Current: 27mA n Low Delay Shift Over Gain Control Range: 2ps/dB n Outputs Biased Up While in Standby n 16-Lead QFN 4mm x 4mm Package with Exposed Pad 40MHz to 500MHz Quadrature Demodulator with VGA , LTC and LT are registered trademarks of Linear Technology Corporation. Total Harmonic Distortion vs IF Input Level at 1.8V Supply n IEEE802.11 n High Speed Wireless LAN n Wireless Local Loop 2xLO+ 2xLO– IF+ IF– EN STBY VCC IOUT+ IOUT– QOUT+ QOUT– GND 1.8VC2 1µF 1nF 1.8pF STANDBY 2xLO 560MHz INPUT 280MHz IF INPUT 10pF
5506 TA01
3.3pF 3.3pF GAIN CONTROL ENABLE IF DETVCTRL The LT 5506 is a 40MHz to 500MHz monolithic integrated quadrature demodulator with variable gain amplifier (VGA), designed for low voltage operation. It supports standards that use a linear modulation format. The chip consists of a VGA, quadrature down-converting mixers and lowpass noise filters. The LO port consists of a divide-by-two stage and LO buffers. The IC provides all building blocks for IF down-conversion to I and Q baseband signals with a single supply voltage of 1.8V to 5.25V. The VGA gain has a linear- in-dB relationship to the control input voltage. Hard-clip- ping amplifiers at the mixer outputs reduce the recovery time from a signal overload condition. The lowpass filters reduce the out-of-band noise and spurious frequency components. The cut-off frequency of the noise filters is approximately 8.8MHz. The external 2xLO frequency is required to be twice the IF input frequency for the mixers. The standby mode provides reduced supply current and fast transient response into the normal operating mode when the I/Q outputs are AC-coupled to a baseband chip. FEATURES DESCRIPTIO U APPLICATIO SU TYPICAL APPLICATIO U
Operating Ambient Temperature Voltage on Any Pin ORDER PART NUMBER TJMAX = 125°C, qJA = 37°C/W EXPOSED PAD (PIN 17) IS GROUND MUST BE SOLDERED TO PCB LT5506EUF ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W (Note 1) ELECTRICAL CHARACTERISTICSVCC = 3V. f2xLO = 570MHz, P2xLO = –5dBm (Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kW differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3) Consult LTC Marketing for parts specified with wider operating temperature ranges. 16 15 14 13 5 6 7 8 TOP VIEW UF PACKAGE 16-LEAD (4mm · 4mm) PLASTIC QFN 1GND IF+ IF– GND STBY 2xLO+ 2xLO– EN IOUT+ IOUT– QOUT+ QOUT– VCC VCTRL IF DET VCC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IF Input fIF Frequency Range 40 to 500 MHz Nominal Input Level R SOURCE = 200W Differential –79 to –22 dBm Input Impedance IF +, IF– to GND, EN = VCC 100W //1.2pF IF+, IF– to GND, EN = GND 1pF NF Noise Figure at Max Gain V CTRL = 1.7V 6.8 dB GL Min Gain (Note 4) V CTRL = 0.2V 0.9 8 dB GH Max Gain (Note 4) V CTRL = 1.7V 50 59 dB IIP3 Input IP3, Min Gain P IF = –22.5dBm (Note 7) –0.5 dBm Input IP3, Max Gain P IF = –75dBm (Note 7) –49 dBm IIP2 Input IP2, Max Gain V CTRL = 1.7V –8 dBm Demodulator I/Q Output Nominal Voltage Swing (Note 6) 0.8 V P-P Clipping Level (Note 6) 1.25 V P-P DC Common Mode Voltage V CC – 1.19 V I/Q Amplitude Imbalance (Note 8) 0.2 0.5 dB I/Q Phase Imbalance (Note 8) 0.6 3 Deg DC Offset (Notes 6, 8) 28 mV Output Driving Capability Single Ended, C LOAD £ 10pF 2 1.5 k W STBY to Turn-On Delay 0.3 ms I/Q Output 1dB Compression –11.5 dBm I/Q Output IM3 P IF, 1 = –25.5dBm, 280MHz – 50 dBc PIF, 2 = –25.5dBm, 280.1MHz (Note 7)
VCC = 3V. f2·LO = 570MHz, P2·LO = –5dBm (Note 5), f IF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kW differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Specifications over the –40°C to 85°C temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Tests are performed as shown in the configuration of Figure 6. The IF input transformer loss is substracted from the measured values. Note 4: Power gain is defined here as the I (or Q) output power into a 4kW differential load, divided by the IF input power in dB. To calculate the voltage gain between the differential I output (or Q output) and the IF input, including ideal matching network, 10 • log(4kW /50) = 19dB has to be added to this power gain. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Variable Gain Amplifier (VGA) Gain Slope Linearity Error V CTRL = 0V to 1.4V –0.5 dB Temperature Gain Shift T = –40 °C to 85°C, VCTRL = 0V to 1.4V –0.3 dB Gain Control Response Time Settled within 10% of Final Value 100 ns Gain Control Voltage Range 0 to 1.7 V Gain Control Slope 43 dB/V Gain Control Input Impedance To Internal 0.2V 25 k W Delay Shift Over Gain Control Measured Over 10dB Step 2 ps/dB Baseband Lowpass Filter –3dB Cutoff Frequency 7.2 8.8 10.4 MHz Group Delay Ripple 5n s 2xLO Input f2xLO Frequency Range 80 to 1000 MHz P2xLO Input Power 1:2 Transformer with 240 W Shunt Resistor (Note 5) –20 –5 dBm Input Power LC Balun (Note 5) –10 dBm Input Impedance Differential Between 2xLO + and 2xLO– 800W //0.4pF DC Common Mode Voltage V CC – 0.4 V IF Detector IF Detector Range Referred to IF Input –30 to 8 dBm Output Voltage Range For P IF = –30dBm to 8dBm 0.3 to 1.2 V Detector Response Time With External 1.8pF Load, 100 ns Settling within 10% of Final Value Power Supply VCC Supply Voltage 1.8 5.25 V ICC Supply Current EN = High, STBY = Low or High 26.5 36 mA IOFF Shutdown Current EN, STBY < 350mV 0.2 30 mA ISTBY Standby Current EN = Low; STBY = High 3.6 5.5 mA Mode Enable Enable Pin Voltage EN = High 1 V Disable Enable Pin Voltage EN = Low 0.5 V Standby Standby Pin Voltage STBY = High 1 V No Standby Standby Pin Voltage STBY = Low 0.5 V Note 5: If a narrow-band match is used in the 2xLO path instead of a 1:2 transformer with 240W shunt resistor, 2xLO input power can be reduced to –10dBm, without degrading the phase imbalance. See Figure 11 and Figure 6. Note 6: Differential between IOUT+ and IOUT– (or differential between QOUT+ and QOUT–). Note 7: The gain control voltage VCTRL is set in such a way that the differential output voltage between IOUT+ and IOUT– (or differential between QOUT+ and QOUT–) is 800mVP-P, with the given input power PIF. Note 8: The typical parameter is defined as the mean of the absolute values of the data distribution.
Supply Current vs Supply Voltage Gain and Noise Figure vs Control Voltage at 3V Supply Gain and Noise Figure vs Control Voltage at 1.8V Supply Gain Flatness vs Control Voltage at 1.8V Supply Gain and Noise Figure vs Control Voltage and VCC Gain and Noise Figure vs IF Frequency TYPICAL PERFOR A CE CHARACTERISTICSUW SUPPLY VOLTAGE (V) 1.75 SUPPLY CURRENT (mA) 2.25 2.75 3.25 3.75
5506 G01
4.25 4.75 5.25 –40°C 25°C 85°C VCTRL (V) G, NF (dB) 1.5
5506 G02
0.6 GAIN NF –10 0.3 0.9 1.2 1.8 GAIN AT 25°C NF AT 25°C GAIN AT –40°C NF AT –40°C GAIN AT 85°C NF AT 85°C fIF = 284MHz f2xLO = 570MHz VCTRL (V) G, NF (dB) 1.5
5506 G03
0.6 GAIN NF –10 0.3 0.9 1.2 1.8 GAIN AT –40°C NF AT –40°C GAIN AT 25°C NF AT 25°C GAIN AT 85°C NF AT 85°C fIF = 284MHz f2xLO = 570MHz VCTRL (V) –0.5 GAIN DEVIATIN FROM LINEAR FIT (dB) –0.3 –0.1 0.1 0.3 0.6 0.9
5506 G04
1.2 0.3 0.5 –0.4 –0.2 0.2 0.4 1.5 –40°C 85°C 25°C VCTRL (V) G, NF (dB) 1.2 1.8
5506 G05
0.3 GAIN NF 0.6 0.9 1.5 –10 GAIN AT 1.8V NF AT 1.8V GAIN AT 3V NF AT 3V GAIN AT 5.25V NF AT 5.25V fIF = 284MHz f2xLO = 570MHz IF FREQUENCY (MHz) –10 G, NF (dB) 100 1000
5506 G06
GAIN, VCTRL = 1.6V GAIN, VCTRL = 0.9V GAIN, VCTRL = 0.2V NF, VCTRL = 1.6V NF, VCTRL = 0.9V NF, VCTRL = 0.2V VCC = 3V. f2·LO = 570MHz, P2·LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kW differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
vs IF Input Power at 3V Supply and 800mVP-P Differential Out Total Harmonic Distortion vs IF Input Power and IF Frequency Total Harmonic Distortion vs IF Input Power at 1.8V Supply and 800mVP-P Differential Out IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30
5506 G07
–50 –40 –20 –30 –35 –40 –45 –50 –55 –60 –65 –40°C 25°C 85°C fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30
5506 G08
–50 –40 –20 –30 –35 –40 –45 –50 –55 –60 fIF = 280MHz fIF = 40MHz 800mVP-P DIFFERENTIAL OUT 3V SUPPLY fIF = 550MHz IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30
5506 G09
–50 –40 –20 –30 –35 –40 –45 –50 –55 –60 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz 25°C –40°C 85°C Total Harmonic Distortion vs IF Input Power and Supply Voltage IF INPUT POWER EACH TONE (dBm) –60 THD (dBc) –30
5506 G10
–50 –40 –20 –30 –35 –40 –45 –50 –55 –60 1.8V 5.25V 800mVP-P DIFFERENTIAL OUT fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz LPF Frequency Response vs Baseband Frequency and Temperature LPF Frequency Response vs Baseband Frequency and Supply Voltage Total Harmonic Distortion vs IF Input Power at 500mV P-P Differential Out IF INPUT POWER EACH TONE (dBm) –45 –70 THD (dBc) –65 –60 –55 –50 –45 –40 –40 –35 –30 –40°C 25°C 85°C –25
5506 G11
–20 fIF,1 = 280MHz fIF,2 = 280.1MHz f2xLO = 570MHz BASEBAND FREQUENCY (MHz) –25 MAGNITUDE (dB) –20 –15 –10 5 10 25°C 85°C –40°C 15 20
5505 G12
VCC = 3V BASEBAND FREQUENCY (MHz) –25 MAGNITUDE (dB) –20 –15 –10 5 10 1.8V 5.25V 15 20
5505 G13
IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 85°C–40°C –20 –10 0
5506 G14
25°C fIF = 280MHz IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 85°C–40°C –20 –10 0
5506 G15
25°C fIF = 280MHz IF Detector Output Voltage vs IF Input CW Power at 3V Supply IF Detector Output Voltage vs IF Input CW Power at 1.8V Supply TYPICAL PERFOR A CE CHARACTERISTICSUW VCC = 3V. f2·LO = 570MHz, P2·LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kW differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
IF Detector Output Voltage vs IF Input CW Power and IF Frequency IF Detector Output Voltage vs IF Input CW Power and Supply Voltage Phase Relation Between I and Q Outputs vs LO Input Power IF INPUT CW POWER (dBm) –40 0.2 IF DET OUTPUT (V) 0.4 0.6 0.8 1.0 1.2 1.4 –30 –20 –10 0
5506 G16
fIF = 280MHz 1.8V 5.25V IF INPUT CW POWER (dBm) –40 1.2 1.4 1.6
5506 G17
1.0 0.8 –30 –20 –10 10 0.6 0.4 0.2 IF DET OUTPUT (V) VCC = 3V fIF = 550MHz fIF = 280MHz fIF = 40MHz LO INPUT POWER (dBm) –20 –5 5
5506 G18
–15 –10 01 0 PHASE (DEG) fIF = 284MHz, 25°C fIF = 284MHz, –40°C fIF = 284MHz, 85°C fIF = 40MHz, 25°C fIF = 550MHz, 25°C GND (Pins 1, 4, 17): Ground. Pins 1 and 4 are connected to each other internally. The Exposed Pad (Pin 17) is not connected internally to Pins 1 and 4. For chip functionality, the Exposed Pad and either Pin 1 or Pin 4 must be connected to ground. For best RF performance, Pin 1, Pin␣ 4 and the Exposed Pad should be connected to RF ground. IF +, IF– (Pins 2, 3): Differential Inputs for the IF Signal. Each pin must be DC grounded through an external inductor or RF transformer with central ground tap. This path should have a DC resistance lower than 2W to ground. V CC (Pins 5 and 8): Power Supply. These pins should be decoupled to ground using 1000pF and 0.1mF capacitors. VCTRL (Pin 6): VGA Gain Control Input. This pin controls the IF gain and its typical input voltage range is 0.2V to 1.7V. It is internally biased via a 25k resistor to 0.2V, setting a low gain if the V CTRL pin is left floating. IF DET (Pin 7): IF Detector Output. For strong IF input signals, the DC level at this pin is a function of the IF input signal level. EN (Pin 9): Enable Input. When the enable pin voltage is higher than 1V, the IC is completely turned on. When the input voltage is less than 0.5V, the IC is turned off, except the part of the circuit associated with standby mode. 2xLO –, 2xLO+ (Pins 10, 11): Differential Inputs for the 2xLO Input. The 2xLO input frequency must be twice that of the IF frequency. The internal bias voltage is VCC – 0.4V. STBY (Pin 12): Standby Input. When the STBY pin is higher than 1V, the standby mode circuit is turned on to prebias the I/Q buffers. When the STBY pin is less than 0.5V, the standby mode circuit is turned off. Q OUT–, QOUT+ (Pins 13, 14): Differential Baseband Out- puts of the Q Channel. Internally biased at VCC – 1.19V. IOUT–, IOUT+ (Pins 15, 16): Differential Baseband Outputs of the I Channel. Internally biased at VCC – 1.19V. UUUPI FU CTIO S TYPICAL PERFOR A CE CHARACTERISTICSUW VCC = 3V. f2·LO = 570MHz, P2·LO = –5dBm (Note 5), fIF = 284MHz, PIF = –30dBm, I and Q outputs 800mVP-P into 4kW differential load, TA = 25°C, EN = VCC, STBY = VCC, unless otherwise noted. (Note 3)
2·LO+ 2·LO– IF+ IF– IF DET EN STBY IOUT+ IOUT– QOUT+ QOUT– 90° 5506 BD 9 12 VCTRL VGA I-MIXER Q-MIXER CLIPPER CLIPPER LPF LPF The LT5506 consists of variable gain amplifier (VGA), I/Q demodulator, quadrature LO generator, hard clipping amplifiers (clippers), lowpass filters (LPFs) and bias circuitry. The IF signal is fed to the inputs of the VGA. The VGA gain is typically set by an external signal in such a way that the amplified IF signal delivered to the I/Q mixers is constant. The IF signal is then converted into I/Q baseband signals using the I/Q down-converting mixers. The quadrature LO signals that drive the mixers are internally generated from the on-chip divide-by-two circuit. The I/Q signals are passed through a pair of hard-clipping amplifiers (clip- pers), which protect the subsequent lowpass filters from overloading. After externally setting the required gain, these amplifiers should not clip. However, in the event of overload, they reduce the settling time of the (optional) external AC coupling capacitors by preventing asymmetri- cal charging and discharging effects. The second order baseband lowpass filters remove the out-of-band noise and harmonic content generated by the mixers and the clippers. The I/Q baseband outputs are buffered by output drivers. VGA and Input Matching The VGA has a nominal 60dB gain control range with a frequency range of 40MHz to 500MHz. The inputs of the VGA must have a DC return to ground. This can be done using a transformer with a central tap (on secondary) or an LC matching circuit with a matched impedance at the frequency of interest and near zero impedance at DC. The APPLICATIO S I FOR ATIOWU UU differential AC input impedance of the LT5506 is about 200W , thus a 1:4 (impedance ratio) RF transformer with central tap can be used. In Figure 6, the evaluation board schematic is shown using a 1:4 transformer. The mea- sured input sensitivity of this board is about –82.6dBm for a 10dB signal-to-noise ratio. In the case of an LC matching circuit, the circuit of Figure 1 can be used. In Table 1 the values are given for a range of IF frequencies. The match- ing circuit of Figure 1 approaches 180 ° phase shift be- tween IF + and IF – in a broad range around its center frequency. However, some amplitude mismatch occurs if the circuit is not tuned to the center frequency. This leads to reduced circuit linearity performance, because one of the inputs carries a higher signal compared to the perfectly balanced case. A 10% frequency shift from the center frequency results in about a 2dB gain difference between the IF + and IF– inputs. This results in a 1.5dB higher IM3 contribution from the input stage which leads to a 0.75dB drop in IIP3. Moreover, the IIP2 of the circuit is also reduced which can lead to a higher second order harmonic contribution. The circuit can be driven single ended, but this is not recommended because it leads to a 3dB drop in gain and a considerable increase in IM5 and IM7 compo- nents. The single-ended noise figure increases by 4dB if one IF input is directly grounded and increases by 1.5dB if one IF input is grounded via a 1mH inductor. An IF input cannot be left open or connected via a resistor to ground because this will disturb the internal biasing, reducing the gain, noise and linearity performance. For optimal perfor- mance, it is important to keep the DC impedance to ground
reduction due to mismatch less than 0.3dB. Figure 1. IF Input Matching Network at 280MHz
5506 F01
Table 1. The Component Values of Matching Network L1, L2, L3, degrees, depending on the quality factor of the network.
5506 F02
of I and Q are well matched and their phases are 90° apart. approach, the quadrature LO signals are well matched. match, but the 2xLO input sensitivity is about 2dB lower. band match, but 2xLO input sensitivity drops by about 9dB. either of the three 2xLO matching networks.
5506 F03
Figure 4. 2xLO Input Matching Networks for 4a) Narrow Band
5506 F04
baseband signals for both the I channel and the Q channel. output circuit schematic of the I channel or Q channel. outputs to nominal VCC – 1.19V at much reduced current. Table 2. The Logic of Different Operating Modes Figure 5. Simplified Circuit Schematic of I Channel
5506 F05
the STBY (or EN) input is shown. Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers COMPONENTS ARE INCLUDED FOR MEASUREMENT PURPOSES ONLY.
Figure 11. 2.4GHz to 2.5GHz Receiver Application (RX IF = 280MHz)
5506 F11
- DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
- ALL DIMENSIONS ARE IN MILLIMETERS
- DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
- EXPOSED PAD SHALL BE SOLDER PLATED